1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36746c1aa4SDave Airlie #include <drm_dp_helper.h> 37771fe6b9SJerome Glisse #include <linux/i2c.h> 38771fe6b9SJerome Glisse #include <linux/i2c-id.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse #include "radeon_fixed.h" 41c93bb85bSJerome Glisse 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 49771fe6b9SJerome Glisse enum radeon_rmx_type { 50771fe6b9SJerome Glisse RMX_OFF, 51771fe6b9SJerome Glisse RMX_FULL, 52771fe6b9SJerome Glisse RMX_CENTER, 53771fe6b9SJerome Glisse RMX_ASPECT 54771fe6b9SJerome Glisse }; 55771fe6b9SJerome Glisse 56771fe6b9SJerome Glisse enum radeon_tv_std { 57771fe6b9SJerome Glisse TV_STD_NTSC, 58771fe6b9SJerome Glisse TV_STD_PAL, 59771fe6b9SJerome Glisse TV_STD_PAL_M, 60771fe6b9SJerome Glisse TV_STD_PAL_60, 61771fe6b9SJerome Glisse TV_STD_NTSC_J, 62771fe6b9SJerome Glisse TV_STD_SCART_PAL, 63771fe6b9SJerome Glisse TV_STD_SECAM, 64771fe6b9SJerome Glisse TV_STD_PAL_CN, 65d79766faSAlex Deucher TV_STD_PAL_N, 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 689b9fe724SAlex Deucher /* radeon gpio-based i2c 699b9fe724SAlex Deucher * 1. "mask" reg and bits 709b9fe724SAlex Deucher * grabs the gpio pins for software use 719b9fe724SAlex Deucher * 0=not held 1=held 729b9fe724SAlex Deucher * 2. "a" reg and bits 739b9fe724SAlex Deucher * output pin value 749b9fe724SAlex Deucher * 0=low 1=high 759b9fe724SAlex Deucher * 3. "en" reg and bits 769b9fe724SAlex Deucher * sets the pin direction 779b9fe724SAlex Deucher * 0=input 1=output 789b9fe724SAlex Deucher * 4. "y" reg and bits 799b9fe724SAlex Deucher * input pin value 809b9fe724SAlex Deucher * 0=low 1=high 819b9fe724SAlex Deucher */ 82771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 83771fe6b9SJerome Glisse bool valid; 846a93cb25SAlex Deucher /* id used by atom */ 856a93cb25SAlex Deucher uint8_t i2c_id; 86bcc1c2a1SAlex Deucher /* id used by atom */ 87bcc1c2a1SAlex Deucher uint8_t hpd_id; 886a93cb25SAlex Deucher /* can be used with hw i2c engine */ 896a93cb25SAlex Deucher bool hw_capable; 906a93cb25SAlex Deucher /* uses multi-media i2c engine */ 916a93cb25SAlex Deucher bool mm_i2c; 926a93cb25SAlex Deucher /* regs and bits */ 93771fe6b9SJerome Glisse uint32_t mask_clk_reg; 94771fe6b9SJerome Glisse uint32_t mask_data_reg; 95771fe6b9SJerome Glisse uint32_t a_clk_reg; 96771fe6b9SJerome Glisse uint32_t a_data_reg; 979b9fe724SAlex Deucher uint32_t en_clk_reg; 989b9fe724SAlex Deucher uint32_t en_data_reg; 999b9fe724SAlex Deucher uint32_t y_clk_reg; 1009b9fe724SAlex Deucher uint32_t y_data_reg; 101771fe6b9SJerome Glisse uint32_t mask_clk_mask; 102771fe6b9SJerome Glisse uint32_t mask_data_mask; 103771fe6b9SJerome Glisse uint32_t a_clk_mask; 104771fe6b9SJerome Glisse uint32_t a_data_mask; 1059b9fe724SAlex Deucher uint32_t en_clk_mask; 1069b9fe724SAlex Deucher uint32_t en_data_mask; 1079b9fe724SAlex Deucher uint32_t y_clk_mask; 1089b9fe724SAlex Deucher uint32_t y_data_mask; 109771fe6b9SJerome Glisse }; 110771fe6b9SJerome Glisse 111771fe6b9SJerome Glisse struct radeon_tmds_pll { 112771fe6b9SJerome Glisse uint32_t freq; 113771fe6b9SJerome Glisse uint32_t value; 114771fe6b9SJerome Glisse }; 115771fe6b9SJerome Glisse 116771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 117771fe6b9SJerome Glisse 1187c27f87dSAlex Deucher /* pll flags */ 119771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 120771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 121771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 122771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 123771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 124771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 125771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 126771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 127771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 128771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 129771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 130d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 131fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 132771fe6b9SJerome Glisse 1337c27f87dSAlex Deucher /* pll algo */ 1347c27f87dSAlex Deucher enum radeon_pll_algo { 1357c27f87dSAlex Deucher PLL_ALGO_LEGACY, 1367c27f87dSAlex Deucher PLL_ALGO_AVIVO 1377c27f87dSAlex Deucher }; 1387c27f87dSAlex Deucher 139771fe6b9SJerome Glisse struct radeon_pll { 140fc10332bSAlex Deucher /* reference frequency */ 141fc10332bSAlex Deucher uint32_t reference_freq; 142fc10332bSAlex Deucher 143fc10332bSAlex Deucher /* fixed dividers */ 144fc10332bSAlex Deucher uint32_t reference_div; 145fc10332bSAlex Deucher uint32_t post_div; 146fc10332bSAlex Deucher 147fc10332bSAlex Deucher /* pll in/out limits */ 148771fe6b9SJerome Glisse uint32_t pll_in_min; 149771fe6b9SJerome Glisse uint32_t pll_in_max; 150771fe6b9SJerome Glisse uint32_t pll_out_min; 151771fe6b9SJerome Glisse uint32_t pll_out_max; 152fc10332bSAlex Deucher uint32_t best_vco; 153771fe6b9SJerome Glisse 154fc10332bSAlex Deucher /* divider limits */ 155771fe6b9SJerome Glisse uint32_t min_ref_div; 156771fe6b9SJerome Glisse uint32_t max_ref_div; 157771fe6b9SJerome Glisse uint32_t min_post_div; 158771fe6b9SJerome Glisse uint32_t max_post_div; 159771fe6b9SJerome Glisse uint32_t min_feedback_div; 160771fe6b9SJerome Glisse uint32_t max_feedback_div; 161771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 162771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 163fc10332bSAlex Deucher 164fc10332bSAlex Deucher /* flags for the current clock */ 165fc10332bSAlex Deucher uint32_t flags; 166fc10332bSAlex Deucher 167fc10332bSAlex Deucher /* pll id */ 168fc10332bSAlex Deucher uint32_t id; 1697c27f87dSAlex Deucher /* pll algo */ 1707c27f87dSAlex Deucher enum radeon_pll_algo algo; 171771fe6b9SJerome Glisse }; 172771fe6b9SJerome Glisse 1735a6f98f5SAlex Deucher struct i2c_algo_radeon_data { 1745a6f98f5SAlex Deucher struct i2c_adapter bit_adapter; 1755a6f98f5SAlex Deucher struct i2c_algo_bit_data bit_data; 1765a6f98f5SAlex Deucher }; 1775a6f98f5SAlex Deucher 178771fe6b9SJerome Glisse struct radeon_i2c_chan { 179771fe6b9SJerome Glisse struct i2c_adapter adapter; 180746c1aa4SDave Airlie struct drm_device *dev; 181746c1aa4SDave Airlie union { 182746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 1835a6f98f5SAlex Deucher struct i2c_algo_radeon_data radeon; 184746c1aa4SDave Airlie } algo; 185771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 186771fe6b9SJerome Glisse }; 187771fe6b9SJerome Glisse 188771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 189771fe6b9SJerome Glisse enum radeon_connector_table { 190771fe6b9SJerome Glisse CT_NONE, 191771fe6b9SJerome Glisse CT_GENERIC, 192771fe6b9SJerome Glisse CT_IBOOK, 193771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 194771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 195771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 196771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 197771fe6b9SJerome Glisse CT_MINI_INTERNAL, 198771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 199771fe6b9SJerome Glisse CT_EMAC, 200771fe6b9SJerome Glisse }; 201771fe6b9SJerome Glisse 202fcec570bSAlex Deucher enum radeon_dvo_chip { 203fcec570bSAlex Deucher DVO_SIL164, 204fcec570bSAlex Deucher DVO_SIL1178, 205fcec570bSAlex Deucher }; 206fcec570bSAlex Deucher 207771fe6b9SJerome Glisse struct radeon_mode_info { 208771fe6b9SJerome Glisse struct atom_context *atom_context; 20961c4b24bSMathias Fröhlich struct card_info *atom_card_info; 210771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 211771fe6b9SJerome Glisse bool mode_config_initialized; 212bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 213445282dbSDave Airlie /* DVI-I properties */ 214445282dbSDave Airlie struct drm_property *coherent_mode_property; 215445282dbSDave Airlie /* DAC enable load detect */ 216445282dbSDave Airlie struct drm_property *load_detect_property; 217445282dbSDave Airlie /* TV standard load detect */ 218445282dbSDave Airlie struct drm_property *tv_std_property; 219445282dbSDave Airlie /* legacy TMDS PLL detect */ 220445282dbSDave Airlie struct drm_property *tmds_pll_property; 2213c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2223c537889SAlex Deucher struct edid *bios_hardcoded_edid; 223c93bb85bSJerome Glisse }; 224c93bb85bSJerome Glisse 2254ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2264ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2274ce001abSDave Airlie 2284ce001abSDave Airlie /* need to store these as reading 2294ce001abSDave Airlie back code tables is excessive */ 2304ce001abSDave Airlie struct radeon_tv_regs { 2314ce001abSDave Airlie uint32_t tv_uv_adr; 2324ce001abSDave Airlie uint32_t timing_cntl; 2334ce001abSDave Airlie uint32_t hrestart; 2344ce001abSDave Airlie uint32_t vrestart; 2354ce001abSDave Airlie uint32_t frestart; 2364ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2374ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2384ce001abSDave Airlie }; 2394ce001abSDave Airlie 240771fe6b9SJerome Glisse struct radeon_crtc { 241771fe6b9SJerome Glisse struct drm_crtc base; 242771fe6b9SJerome Glisse int crtc_id; 243771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 244771fe6b9SJerome Glisse bool enabled; 245771fe6b9SJerome Glisse bool can_tile; 246771fe6b9SJerome Glisse uint32_t crtc_offset; 247771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 248771fe6b9SJerome Glisse uint64_t cursor_addr; 249771fe6b9SJerome Glisse int cursor_width; 250771fe6b9SJerome Glisse int cursor_height; 2514162338aSDave Airlie uint32_t legacy_display_base_addr; 252c836e862SAlex Deucher uint32_t legacy_cursor_offset; 253c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 254c93bb85bSJerome Glisse fixed20_12 vsc; 255c93bb85bSJerome Glisse fixed20_12 hsc; 256de2103e4SAlex Deucher struct drm_display_mode native_mode; 257bcc1c2a1SAlex Deucher int pll_id; 258771fe6b9SJerome Glisse }; 259771fe6b9SJerome Glisse 260771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 261771fe6b9SJerome Glisse /* legacy primary dac */ 262771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 263771fe6b9SJerome Glisse }; 264771fe6b9SJerome Glisse 265771fe6b9SJerome Glisse struct radeon_encoder_lvds { 266771fe6b9SJerome Glisse /* legacy lvds */ 267771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 268771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 269771fe6b9SJerome Glisse uint8_t panel_digon_delay; 270771fe6b9SJerome Glisse uint8_t panel_blon_delay; 271771fe6b9SJerome Glisse uint16_t panel_ref_divider; 272771fe6b9SJerome Glisse uint8_t panel_post_divider; 273771fe6b9SJerome Glisse uint16_t panel_fb_divider; 274771fe6b9SJerome Glisse bool use_bios_dividers; 275771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 276771fe6b9SJerome Glisse /* panel mode */ 277de2103e4SAlex Deucher struct drm_display_mode native_mode; 278771fe6b9SJerome Glisse }; 279771fe6b9SJerome Glisse 280771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 281771fe6b9SJerome Glisse /* legacy tv dac */ 282771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 283771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 284771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 285771fe6b9SJerome Glisse 2864ce001abSDave Airlie int h_pos; 2874ce001abSDave Airlie int v_pos; 2884ce001abSDave Airlie int h_size; 2894ce001abSDave Airlie int supported_tv_stds; 2904ce001abSDave Airlie bool tv_on; 291771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 2924ce001abSDave Airlie struct radeon_tv_regs tv; 293771fe6b9SJerome Glisse }; 294771fe6b9SJerome Glisse 295771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 296771fe6b9SJerome Glisse /* legacy int tmds */ 297771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 298771fe6b9SJerome Glisse }; 299771fe6b9SJerome Glisse 300fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 301fcec570bSAlex Deucher /* tmds over dvo */ 302fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 303fcec570bSAlex Deucher uint8_t slave_addr; 304fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 305fcec570bSAlex Deucher }; 306fcec570bSAlex Deucher 307ebbe1cb9SAlex Deucher /* spread spectrum */ 308ebbe1cb9SAlex Deucher struct radeon_atom_ss { 309ebbe1cb9SAlex Deucher uint16_t percentage; 310ebbe1cb9SAlex Deucher uint8_t type; 311ebbe1cb9SAlex Deucher uint8_t step; 312ebbe1cb9SAlex Deucher uint8_t delay; 313ebbe1cb9SAlex Deucher uint8_t range; 314ebbe1cb9SAlex Deucher uint8_t refdiv; 315ebbe1cb9SAlex Deucher }; 316ebbe1cb9SAlex Deucher 317771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 318771fe6b9SJerome Glisse /* atom dig */ 319771fe6b9SJerome Glisse bool coherent_mode; 320f28cf339SDave Airlie int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ 321771fe6b9SJerome Glisse /* atom lvds */ 322771fe6b9SJerome Glisse uint32_t lvds_misc; 323771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 3247c27f87dSAlex Deucher enum radeon_pll_algo pll_algo; 325ebbe1cb9SAlex Deucher struct radeon_atom_ss *ss; 326771fe6b9SJerome Glisse /* panel mode */ 327de2103e4SAlex Deucher struct drm_display_mode native_mode; 328771fe6b9SJerome Glisse }; 329771fe6b9SJerome Glisse 3304ce001abSDave Airlie struct radeon_encoder_atom_dac { 3314ce001abSDave Airlie enum radeon_tv_std tv_std; 3324ce001abSDave Airlie }; 3334ce001abSDave Airlie 334771fe6b9SJerome Glisse struct radeon_encoder { 335771fe6b9SJerome Glisse struct drm_encoder base; 336771fe6b9SJerome Glisse uint32_t encoder_id; 337771fe6b9SJerome Glisse uint32_t devices; 3384ce001abSDave Airlie uint32_t active_device; 339771fe6b9SJerome Glisse uint32_t flags; 340771fe6b9SJerome Glisse uint32_t pixel_clock; 341771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 342de2103e4SAlex Deucher struct drm_display_mode native_mode; 343771fe6b9SJerome Glisse void *enc_priv; 344dafc3bd5SChristian Koenig int hdmi_offset; 345dafc3bd5SChristian Koenig int hdmi_audio_workaround; 346dafc3bd5SChristian Koenig int hdmi_buffer_status; 347771fe6b9SJerome Glisse }; 348771fe6b9SJerome Glisse 349771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 350771fe6b9SJerome Glisse uint32_t igp_lane_info; 351771fe6b9SJerome Glisse bool linkb; 3524143e919SAlex Deucher /* displayport */ 353746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 3541a66c95aSAlex Deucher u8 dpcd[8]; 3554143e919SAlex Deucher u8 dp_sink_type; 3565801ead6SAlex Deucher int dp_clock; 3575801ead6SAlex Deucher int dp_lane_count; 358771fe6b9SJerome Glisse }; 359771fe6b9SJerome Glisse 360eed45b30SAlex Deucher struct radeon_gpio_rec { 361eed45b30SAlex Deucher bool valid; 362eed45b30SAlex Deucher u8 id; 363eed45b30SAlex Deucher u32 reg; 364eed45b30SAlex Deucher u32 mask; 365eed45b30SAlex Deucher }; 366eed45b30SAlex Deucher 367eed45b30SAlex Deucher enum radeon_hpd_id { 368eed45b30SAlex Deucher RADEON_HPD_NONE = 0, 369eed45b30SAlex Deucher RADEON_HPD_1, 370eed45b30SAlex Deucher RADEON_HPD_2, 371eed45b30SAlex Deucher RADEON_HPD_3, 372eed45b30SAlex Deucher RADEON_HPD_4, 373eed45b30SAlex Deucher RADEON_HPD_5, 374eed45b30SAlex Deucher RADEON_HPD_6, 375eed45b30SAlex Deucher }; 376eed45b30SAlex Deucher 377eed45b30SAlex Deucher struct radeon_hpd { 378eed45b30SAlex Deucher enum radeon_hpd_id hpd; 379eed45b30SAlex Deucher u8 plugged_state; 380eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 381eed45b30SAlex Deucher }; 382eed45b30SAlex Deucher 383771fe6b9SJerome Glisse struct radeon_connector { 384771fe6b9SJerome Glisse struct drm_connector base; 385771fe6b9SJerome Glisse uint32_t connector_id; 386771fe6b9SJerome Glisse uint32_t devices; 387771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 3880294cf4fSAlex Deucher /* some systems have a an hdmi and vga port with a shared ddc line */ 3890294cf4fSAlex Deucher bool shared_ddc; 3904ce001abSDave Airlie bool use_digital; 3914ce001abSDave Airlie /* we need to mind the EDID between detect 3924ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 3934ce001abSDave Airlie struct edid *edid; 394771fe6b9SJerome Glisse void *con_priv; 395445282dbSDave Airlie bool dac_load_detect; 396b75fad06SAlex Deucher uint16_t connector_object_id; 397eed45b30SAlex Deucher struct radeon_hpd hpd; 398771fe6b9SJerome Glisse }; 399771fe6b9SJerome Glisse 400771fe6b9SJerome Glisse struct radeon_framebuffer { 401771fe6b9SJerome Glisse struct drm_framebuffer base; 402771fe6b9SJerome Glisse struct drm_gem_object *obj; 403771fe6b9SJerome Glisse }; 404771fe6b9SJerome Glisse 405d79766faSAlex Deucher extern enum radeon_tv_std 406d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 407d79766faSAlex Deucher extern enum radeon_tv_std 408d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 409d79766faSAlex Deucher 410d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 411d4877cf2SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 4125801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 4135801ead6SAlex Deucher struct drm_display_mode *mode); 4145801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 4155801ead6SAlex Deucher struct drm_display_mode *mode); 4165801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder, 4175801ead6SAlex Deucher struct drm_connector *connector); 4184143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 4199fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 420bcc1c2a1SAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); 4215801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 4225801ead6SAlex Deucher int action, uint8_t lane_num, 4235801ead6SAlex Deucher uint8_t lane_set); 424746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 425746c1aa4SDave Airlie uint8_t write_byte, uint8_t *read_byte); 426746c1aa4SDave Airlie 427746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 4286a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 4296a93cb25SAlex Deucher const char *name); 430771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 431771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 432771fe6b9SJerome Glisse const char *name); 433771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 4345a6f98f5SAlex Deucher extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c); 4355a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 436fcec570bSAlex Deucher u8 slave_addr, 437fcec570bSAlex Deucher u8 addr, 438fcec570bSAlex Deucher u8 *val); 4395a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 440fcec570bSAlex Deucher u8 slave_addr, 441fcec570bSAlex Deucher u8 addr, 442fcec570bSAlex Deucher u8 val); 443771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 444771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 445771fe6b9SJerome Glisse 446771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 447771fe6b9SJerome Glisse 448771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 449771fe6b9SJerome Glisse uint64_t freq, 450771fe6b9SJerome Glisse uint32_t *dot_clock_p, 451771fe6b9SJerome Glisse uint32_t *fb_div_p, 452771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 453771fe6b9SJerome Glisse uint32_t *ref_div_p, 454fc10332bSAlex Deucher uint32_t *post_div_p); 455771fe6b9SJerome Glisse 4561f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 4571f3b6a45SDave Airlie 458771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 459771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 460771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 461771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 462771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 463771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 46432f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 465771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 4664ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 467771fe6b9SJerome Glisse 468771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 469771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 470771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 471771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 472771fe6b9SJerome Glisse struct drm_display_mode *mode, 473771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 474771fe6b9SJerome Glisse int x, int y, 475771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 476771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 477771fe6b9SJerome Glisse 478771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 479771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 480771fe6b9SJerome Glisse 481771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 482771fe6b9SJerome Glisse struct drm_file *file_priv, 483771fe6b9SJerome Glisse uint32_t handle, 484771fe6b9SJerome Glisse uint32_t width, 485771fe6b9SJerome Glisse uint32_t height); 486771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 487771fe6b9SJerome Glisse int x, int y); 488771fe6b9SJerome Glisse 4893c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 4903c537889SAlex Deucher extern struct edid * 4913c537889SAlex Deucher radeon_combios_get_hardcoded_edid(struct radeon_device *rdev); 492771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 493771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 494771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 495771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 496fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 497445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 498fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 499445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 500fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 501445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 502fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 503fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 504fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 505fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 5066fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 5076fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 5086fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 5096fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 510771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 511771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 512771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 513771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 514771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 515771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 516771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 517fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 518fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 519771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 520771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 521771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 522771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 523f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 524f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 525771fe6b9SJerome Glisse extern void 526771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 527771fe6b9SJerome Glisse extern void 528771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 529771fe6b9SJerome Glisse extern void 530771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 531771fe6b9SJerome Glisse extern void 532771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 533771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 534771fe6b9SJerome Glisse u16 blue, int regno); 535b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 536b8c00ac5SDave Airlie u16 *blue, int regno); 537771fe6b9SJerome Glisse struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, 538771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 539771fe6b9SJerome Glisse struct drm_gem_object *obj); 540771fe6b9SJerome Glisse 541771fe6b9SJerome Glisse int radeonfb_probe(struct drm_device *dev); 542771fe6b9SJerome Glisse 543771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 544771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 545771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 546771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 547771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 548771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 549771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 550771fe6b9SJerome Glisse 551771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 552771fe6b9SJerome Glisse 553771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 554771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 555771fe6b9SJerome Glisse 556771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 557771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 558771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 559771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev); 560c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 561c93bb85bSJerome Glisse struct drm_display_mode *mode, 562c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 5634ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 564771fe6b9SJerome Glisse 5654ce001abSDave Airlie /* legacy tv */ 5664ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 5674ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 5684ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 5694ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 5704ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 5714ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 5724ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 5734ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 5744ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 5754ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 5764ce001abSDave Airlie struct drm_display_mode *mode, 5774ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 578771fe6b9SJerome Glisse #endif 579