1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36746c1aa4SDave Airlie #include <drm_dp_helper.h> 37771fe6b9SJerome Glisse #include <linux/i2c.h> 38771fe6b9SJerome Glisse #include <linux/i2c-id.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse #include "radeon_fixed.h" 41c93bb85bSJerome Glisse 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 49771fe6b9SJerome Glisse enum radeon_connector_type { 50771fe6b9SJerome Glisse CONNECTOR_NONE, 51771fe6b9SJerome Glisse CONNECTOR_VGA, 52771fe6b9SJerome Glisse CONNECTOR_DVI_I, 53771fe6b9SJerome Glisse CONNECTOR_DVI_D, 54771fe6b9SJerome Glisse CONNECTOR_DVI_A, 55771fe6b9SJerome Glisse CONNECTOR_STV, 56771fe6b9SJerome Glisse CONNECTOR_CTV, 57771fe6b9SJerome Glisse CONNECTOR_LVDS, 58771fe6b9SJerome Glisse CONNECTOR_DIGITAL, 59771fe6b9SJerome Glisse CONNECTOR_SCART, 60771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_A, 61771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_B, 62771fe6b9SJerome Glisse CONNECTOR_0XC, 63771fe6b9SJerome Glisse CONNECTOR_0XD, 64771fe6b9SJerome Glisse CONNECTOR_DIN, 65771fe6b9SJerome Glisse CONNECTOR_DISPLAY_PORT, 66771fe6b9SJerome Glisse CONNECTOR_UNSUPPORTED 67771fe6b9SJerome Glisse }; 68771fe6b9SJerome Glisse 69771fe6b9SJerome Glisse enum radeon_dvi_type { 70771fe6b9SJerome Glisse DVI_AUTO, 71771fe6b9SJerome Glisse DVI_DIGITAL, 72771fe6b9SJerome Glisse DVI_ANALOG 73771fe6b9SJerome Glisse }; 74771fe6b9SJerome Glisse 75771fe6b9SJerome Glisse enum radeon_rmx_type { 76771fe6b9SJerome Glisse RMX_OFF, 77771fe6b9SJerome Glisse RMX_FULL, 78771fe6b9SJerome Glisse RMX_CENTER, 79771fe6b9SJerome Glisse RMX_ASPECT 80771fe6b9SJerome Glisse }; 81771fe6b9SJerome Glisse 82771fe6b9SJerome Glisse enum radeon_tv_std { 83771fe6b9SJerome Glisse TV_STD_NTSC, 84771fe6b9SJerome Glisse TV_STD_PAL, 85771fe6b9SJerome Glisse TV_STD_PAL_M, 86771fe6b9SJerome Glisse TV_STD_PAL_60, 87771fe6b9SJerome Glisse TV_STD_NTSC_J, 88771fe6b9SJerome Glisse TV_STD_SCART_PAL, 89771fe6b9SJerome Glisse TV_STD_SECAM, 90771fe6b9SJerome Glisse TV_STD_PAL_CN, 91771fe6b9SJerome Glisse }; 92771fe6b9SJerome Glisse 939b9fe724SAlex Deucher /* radeon gpio-based i2c 949b9fe724SAlex Deucher * 1. "mask" reg and bits 959b9fe724SAlex Deucher * grabs the gpio pins for software use 969b9fe724SAlex Deucher * 0=not held 1=held 979b9fe724SAlex Deucher * 2. "a" reg and bits 989b9fe724SAlex Deucher * output pin value 999b9fe724SAlex Deucher * 0=low 1=high 1009b9fe724SAlex Deucher * 3. "en" reg and bits 1019b9fe724SAlex Deucher * sets the pin direction 1029b9fe724SAlex Deucher * 0=input 1=output 1039b9fe724SAlex Deucher * 4. "y" reg and bits 1049b9fe724SAlex Deucher * input pin value 1059b9fe724SAlex Deucher * 0=low 1=high 1069b9fe724SAlex Deucher */ 107771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 108771fe6b9SJerome Glisse bool valid; 1096a93cb25SAlex Deucher /* id used by atom */ 1106a93cb25SAlex Deucher uint8_t i2c_id; 1116a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1126a93cb25SAlex Deucher bool hw_capable; 1136a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1146a93cb25SAlex Deucher bool mm_i2c; 1156a93cb25SAlex Deucher /* regs and bits */ 116771fe6b9SJerome Glisse uint32_t mask_clk_reg; 117771fe6b9SJerome Glisse uint32_t mask_data_reg; 118771fe6b9SJerome Glisse uint32_t a_clk_reg; 119771fe6b9SJerome Glisse uint32_t a_data_reg; 1209b9fe724SAlex Deucher uint32_t en_clk_reg; 1219b9fe724SAlex Deucher uint32_t en_data_reg; 1229b9fe724SAlex Deucher uint32_t y_clk_reg; 1239b9fe724SAlex Deucher uint32_t y_data_reg; 124771fe6b9SJerome Glisse uint32_t mask_clk_mask; 125771fe6b9SJerome Glisse uint32_t mask_data_mask; 126771fe6b9SJerome Glisse uint32_t a_clk_mask; 127771fe6b9SJerome Glisse uint32_t a_data_mask; 1289b9fe724SAlex Deucher uint32_t en_clk_mask; 1299b9fe724SAlex Deucher uint32_t en_data_mask; 1309b9fe724SAlex Deucher uint32_t y_clk_mask; 1319b9fe724SAlex Deucher uint32_t y_data_mask; 132771fe6b9SJerome Glisse }; 133771fe6b9SJerome Glisse 134771fe6b9SJerome Glisse struct radeon_tmds_pll { 135771fe6b9SJerome Glisse uint32_t freq; 136771fe6b9SJerome Glisse uint32_t value; 137771fe6b9SJerome Glisse }; 138771fe6b9SJerome Glisse 139771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 140771fe6b9SJerome Glisse 141771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 142771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 143771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 144771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 147771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 148771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 149771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 150771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 151771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 152d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 153771fe6b9SJerome Glisse 154771fe6b9SJerome Glisse struct radeon_pll { 155771fe6b9SJerome Glisse uint16_t reference_freq; 156771fe6b9SJerome Glisse uint16_t reference_div; 157771fe6b9SJerome Glisse uint32_t pll_in_min; 158771fe6b9SJerome Glisse uint32_t pll_in_max; 159771fe6b9SJerome Glisse uint32_t pll_out_min; 160771fe6b9SJerome Glisse uint32_t pll_out_max; 161771fe6b9SJerome Glisse uint16_t xclk; 162771fe6b9SJerome Glisse 163771fe6b9SJerome Glisse uint32_t min_ref_div; 164771fe6b9SJerome Glisse uint32_t max_ref_div; 165771fe6b9SJerome Glisse uint32_t min_post_div; 166771fe6b9SJerome Glisse uint32_t max_post_div; 167771fe6b9SJerome Glisse uint32_t min_feedback_div; 168771fe6b9SJerome Glisse uint32_t max_feedback_div; 169771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 170771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 171771fe6b9SJerome Glisse uint32_t best_vco; 172771fe6b9SJerome Glisse }; 173771fe6b9SJerome Glisse 174771fe6b9SJerome Glisse struct radeon_i2c_chan { 175771fe6b9SJerome Glisse struct i2c_adapter adapter; 176746c1aa4SDave Airlie struct drm_device *dev; 177746c1aa4SDave Airlie union { 178746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 179746c1aa4SDave Airlie struct i2c_algo_bit_data bit; 180746c1aa4SDave Airlie } algo; 181771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 182771fe6b9SJerome Glisse }; 183771fe6b9SJerome Glisse 184771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 185771fe6b9SJerome Glisse enum radeon_connector_table { 186771fe6b9SJerome Glisse CT_NONE, 187771fe6b9SJerome Glisse CT_GENERIC, 188771fe6b9SJerome Glisse CT_IBOOK, 189771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 190771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 191771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 192771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 193771fe6b9SJerome Glisse CT_MINI_INTERNAL, 194771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 195771fe6b9SJerome Glisse CT_EMAC, 196771fe6b9SJerome Glisse }; 197771fe6b9SJerome Glisse 198fcec570bSAlex Deucher enum radeon_dvo_chip { 199fcec570bSAlex Deucher DVO_SIL164, 200fcec570bSAlex Deucher DVO_SIL1178, 201fcec570bSAlex Deucher }; 202fcec570bSAlex Deucher 203771fe6b9SJerome Glisse struct radeon_mode_info { 204771fe6b9SJerome Glisse struct atom_context *atom_context; 20561c4b24bSMathias Fröhlich struct card_info *atom_card_info; 206771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 207771fe6b9SJerome Glisse bool mode_config_initialized; 208c93bb85bSJerome Glisse struct radeon_crtc *crtcs[2]; 209445282dbSDave Airlie /* DVI-I properties */ 210445282dbSDave Airlie struct drm_property *coherent_mode_property; 211445282dbSDave Airlie /* DAC enable load detect */ 212445282dbSDave Airlie struct drm_property *load_detect_property; 213445282dbSDave Airlie /* TV standard load detect */ 214445282dbSDave Airlie struct drm_property *tv_std_property; 215445282dbSDave Airlie /* legacy TMDS PLL detect */ 216445282dbSDave Airlie struct drm_property *tmds_pll_property; 217445282dbSDave Airlie 218c93bb85bSJerome Glisse }; 219c93bb85bSJerome Glisse 2204ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2214ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2224ce001abSDave Airlie 2234ce001abSDave Airlie /* need to store these as reading 2244ce001abSDave Airlie back code tables is excessive */ 2254ce001abSDave Airlie struct radeon_tv_regs { 2264ce001abSDave Airlie uint32_t tv_uv_adr; 2274ce001abSDave Airlie uint32_t timing_cntl; 2284ce001abSDave Airlie uint32_t hrestart; 2294ce001abSDave Airlie uint32_t vrestart; 2304ce001abSDave Airlie uint32_t frestart; 2314ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2324ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2334ce001abSDave Airlie }; 2344ce001abSDave Airlie 235771fe6b9SJerome Glisse struct radeon_crtc { 236771fe6b9SJerome Glisse struct drm_crtc base; 237771fe6b9SJerome Glisse int crtc_id; 238771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 239771fe6b9SJerome Glisse bool enabled; 240771fe6b9SJerome Glisse bool can_tile; 241771fe6b9SJerome Glisse uint32_t crtc_offset; 242771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 243771fe6b9SJerome Glisse uint64_t cursor_addr; 244771fe6b9SJerome Glisse int cursor_width; 245771fe6b9SJerome Glisse int cursor_height; 2464162338aSDave Airlie uint32_t legacy_display_base_addr; 247c836e862SAlex Deucher uint32_t legacy_cursor_offset; 248c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 249c93bb85bSJerome Glisse fixed20_12 vsc; 250c93bb85bSJerome Glisse fixed20_12 hsc; 251de2103e4SAlex Deucher struct drm_display_mode native_mode; 252771fe6b9SJerome Glisse }; 253771fe6b9SJerome Glisse 254771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 255771fe6b9SJerome Glisse /* legacy primary dac */ 256771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 257771fe6b9SJerome Glisse }; 258771fe6b9SJerome Glisse 259771fe6b9SJerome Glisse struct radeon_encoder_lvds { 260771fe6b9SJerome Glisse /* legacy lvds */ 261771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 262771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 263771fe6b9SJerome Glisse uint8_t panel_digon_delay; 264771fe6b9SJerome Glisse uint8_t panel_blon_delay; 265771fe6b9SJerome Glisse uint16_t panel_ref_divider; 266771fe6b9SJerome Glisse uint8_t panel_post_divider; 267771fe6b9SJerome Glisse uint16_t panel_fb_divider; 268771fe6b9SJerome Glisse bool use_bios_dividers; 269771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 270771fe6b9SJerome Glisse /* panel mode */ 271de2103e4SAlex Deucher struct drm_display_mode native_mode; 272771fe6b9SJerome Glisse }; 273771fe6b9SJerome Glisse 274771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 275771fe6b9SJerome Glisse /* legacy tv dac */ 276771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 277771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 278771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 279771fe6b9SJerome Glisse 2804ce001abSDave Airlie int h_pos; 2814ce001abSDave Airlie int v_pos; 2824ce001abSDave Airlie int h_size; 2834ce001abSDave Airlie int supported_tv_stds; 2844ce001abSDave Airlie bool tv_on; 285771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 2864ce001abSDave Airlie struct radeon_tv_regs tv; 287771fe6b9SJerome Glisse }; 288771fe6b9SJerome Glisse 289771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 290771fe6b9SJerome Glisse /* legacy int tmds */ 291771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 292771fe6b9SJerome Glisse }; 293771fe6b9SJerome Glisse 294fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 295fcec570bSAlex Deucher /* tmds over dvo */ 296fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 297fcec570bSAlex Deucher uint8_t slave_addr; 298fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 299fcec570bSAlex Deucher }; 300fcec570bSAlex Deucher 301ebbe1cb9SAlex Deucher /* spread spectrum */ 302ebbe1cb9SAlex Deucher struct radeon_atom_ss { 303ebbe1cb9SAlex Deucher uint16_t percentage; 304ebbe1cb9SAlex Deucher uint8_t type; 305ebbe1cb9SAlex Deucher uint8_t step; 306ebbe1cb9SAlex Deucher uint8_t delay; 307ebbe1cb9SAlex Deucher uint8_t range; 308ebbe1cb9SAlex Deucher uint8_t refdiv; 309ebbe1cb9SAlex Deucher }; 310ebbe1cb9SAlex Deucher 311771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 312771fe6b9SJerome Glisse /* atom dig */ 313771fe6b9SJerome Glisse bool coherent_mode; 314771fe6b9SJerome Glisse int dig_block; 315771fe6b9SJerome Glisse /* atom lvds */ 316771fe6b9SJerome Glisse uint32_t lvds_misc; 317771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 318ebbe1cb9SAlex Deucher struct radeon_atom_ss *ss; 319771fe6b9SJerome Glisse /* panel mode */ 320de2103e4SAlex Deucher struct drm_display_mode native_mode; 321771fe6b9SJerome Glisse }; 322771fe6b9SJerome Glisse 3234ce001abSDave Airlie struct radeon_encoder_atom_dac { 3244ce001abSDave Airlie enum radeon_tv_std tv_std; 3254ce001abSDave Airlie }; 3264ce001abSDave Airlie 327771fe6b9SJerome Glisse struct radeon_encoder { 328771fe6b9SJerome Glisse struct drm_encoder base; 329771fe6b9SJerome Glisse uint32_t encoder_id; 330771fe6b9SJerome Glisse uint32_t devices; 3314ce001abSDave Airlie uint32_t active_device; 332771fe6b9SJerome Glisse uint32_t flags; 333771fe6b9SJerome Glisse uint32_t pixel_clock; 334771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 335de2103e4SAlex Deucher struct drm_display_mode native_mode; 336771fe6b9SJerome Glisse void *enc_priv; 337771fe6b9SJerome Glisse }; 338771fe6b9SJerome Glisse 339771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 340771fe6b9SJerome Glisse uint32_t igp_lane_info; 341771fe6b9SJerome Glisse bool linkb; 3424143e919SAlex Deucher /* displayport */ 343746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 3441a66c95aSAlex Deucher u8 dpcd[8]; 3454143e919SAlex Deucher u8 dp_sink_type; 3465801ead6SAlex Deucher int dp_clock; 3475801ead6SAlex Deucher int dp_lane_count; 348771fe6b9SJerome Glisse }; 349771fe6b9SJerome Glisse 350771fe6b9SJerome Glisse struct radeon_connector { 351771fe6b9SJerome Glisse struct drm_connector base; 352771fe6b9SJerome Glisse uint32_t connector_id; 353771fe6b9SJerome Glisse uint32_t devices; 354771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 3550294cf4fSAlex Deucher /* some systems have a an hdmi and vga port with a shared ddc line */ 3560294cf4fSAlex Deucher bool shared_ddc; 3574ce001abSDave Airlie bool use_digital; 3584ce001abSDave Airlie /* we need to mind the EDID between detect 3594ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 3604ce001abSDave Airlie struct edid *edid; 361771fe6b9SJerome Glisse void *con_priv; 362445282dbSDave Airlie bool dac_load_detect; 363b75fad06SAlex Deucher uint16_t connector_object_id; 364771fe6b9SJerome Glisse }; 365771fe6b9SJerome Glisse 366771fe6b9SJerome Glisse struct radeon_framebuffer { 367771fe6b9SJerome Glisse struct drm_framebuffer base; 368771fe6b9SJerome Glisse struct drm_gem_object *obj; 369771fe6b9SJerome Glisse }; 370771fe6b9SJerome Glisse 3715801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 3725801ead6SAlex Deucher struct drm_display_mode *mode); 3735801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 3745801ead6SAlex Deucher struct drm_display_mode *mode); 3755801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder, 3765801ead6SAlex Deucher struct drm_connector *connector); 3774143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 3789fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 3795801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 3805801ead6SAlex Deucher int action, uint8_t lane_num, 3815801ead6SAlex Deucher uint8_t lane_set); 382746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 383746c1aa4SDave Airlie uint8_t write_byte, uint8_t *read_byte); 384746c1aa4SDave Airlie 385746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 3866a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 3876a93cb25SAlex Deucher const char *name); 388771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 389771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 390771fe6b9SJerome Glisse const char *name); 391771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 392fcec570bSAlex Deucher extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, 393fcec570bSAlex Deucher u8 slave_addr, 394fcec570bSAlex Deucher u8 addr, 395fcec570bSAlex Deucher u8 *val); 396fcec570bSAlex Deucher extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c, 397fcec570bSAlex Deucher u8 slave_addr, 398fcec570bSAlex Deucher u8 addr, 399fcec570bSAlex Deucher u8 val); 400771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 401771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 402771fe6b9SJerome Glisse 403771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 404771fe6b9SJerome Glisse 405771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 406771fe6b9SJerome Glisse uint64_t freq, 407771fe6b9SJerome Glisse uint32_t *dot_clock_p, 408771fe6b9SJerome Glisse uint32_t *fb_div_p, 409771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 410771fe6b9SJerome Glisse uint32_t *ref_div_p, 411771fe6b9SJerome Glisse uint32_t *post_div_p, 412771fe6b9SJerome Glisse int flags); 413771fe6b9SJerome Glisse 4141f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 4151f3b6a45SDave Airlie 416771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 417771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 418771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 419771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 420771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 421771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 42232f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 423771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 4244ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 425771fe6b9SJerome Glisse 426771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 427771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 428771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 429771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 430771fe6b9SJerome Glisse struct drm_display_mode *mode, 431771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 432771fe6b9SJerome Glisse int x, int y, 433771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 434771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 435771fe6b9SJerome Glisse 436771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 437771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 438771fe6b9SJerome Glisse extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); 439771fe6b9SJerome Glisse 440771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 441771fe6b9SJerome Glisse struct drm_file *file_priv, 442771fe6b9SJerome Glisse uint32_t handle, 443771fe6b9SJerome Glisse uint32_t width, 444771fe6b9SJerome Glisse uint32_t height); 445771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 446771fe6b9SJerome Glisse int x, int y); 447771fe6b9SJerome Glisse 448771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 449771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 450771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 451771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 452fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 453445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 454fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 455445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 456fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 457445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 458fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 459fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 460fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 461fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 4626fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 4636fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 4646fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 4656fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 466771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 467771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 468771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 469771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 470771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 471771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 472771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 473fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 474fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 475771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 476771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 477771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 478771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 479f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 480f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 481771fe6b9SJerome Glisse extern void 482771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 483771fe6b9SJerome Glisse extern void 484771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 485771fe6b9SJerome Glisse extern void 486771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 487771fe6b9SJerome Glisse extern void 488771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 489771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 490771fe6b9SJerome Glisse u16 blue, int regno); 491b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 492b8c00ac5SDave Airlie u16 *blue, int regno); 493771fe6b9SJerome Glisse struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, 494771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 495771fe6b9SJerome Glisse struct drm_gem_object *obj); 496771fe6b9SJerome Glisse 497771fe6b9SJerome Glisse int radeonfb_probe(struct drm_device *dev); 498771fe6b9SJerome Glisse 499771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 500771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 501771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 502771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 503771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 504771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 505771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 506ab1e9ea0SAlex Deucher extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state); 507771fe6b9SJerome Glisse 508771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 509771fe6b9SJerome Glisse 510771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 511771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 512771fe6b9SJerome Glisse 513771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 514771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 515771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 516771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev); 517c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 518c93bb85bSJerome Glisse struct drm_display_mode *mode, 519c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 5204ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 521771fe6b9SJerome Glisse 5224ce001abSDave Airlie /* legacy tv */ 5234ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 5244ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 5254ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 5264ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 5274ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 5284ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 5294ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 5304ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 5314ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 5324ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 5334ce001abSDave Airlie struct drm_display_mode *mode, 5344ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 535771fe6b9SJerome Glisse #endif 536