1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33760285e7SDavid Howells #include <drm/drm_crtc.h> 34760285e7SDavid Howells #include <drm/drm_edid.h> 359338203cSLaurent Pinchart #include <drm/drm_encoder.h> 36760285e7SDavid Howells #include <drm/drm_dp_helper.h> 379843ead0SDave Airlie #include <drm/drm_dp_mst_helper.h> 38760285e7SDavid Howells #include <drm/drm_fixed.h> 39760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 40771fe6b9SJerome Glisse #include <linux/i2c.h> 41771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 42c93bb85bSJerome Glisse 4338651674SDave Airlie struct radeon_bo; 44c93bb85bSJerome Glisse struct radeon_device; 45771fe6b9SJerome Glisse 46771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 47771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 48771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 49771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 50771fe6b9SJerome Glisse 5188f39063SStefan Brüns #define RADEON_MAX_HPD_PINS 7 5288f39063SStefan Brüns #define RADEON_MAX_CRTCS 6 5388f39063SStefan Brüns #define RADEON_MAX_AFMT_BLOCKS 7 5488f39063SStefan Brüns 55771fe6b9SJerome Glisse enum radeon_rmx_type { 56771fe6b9SJerome Glisse RMX_OFF, 57771fe6b9SJerome Glisse RMX_FULL, 58771fe6b9SJerome Glisse RMX_CENTER, 59771fe6b9SJerome Glisse RMX_ASPECT 60771fe6b9SJerome Glisse }; 61771fe6b9SJerome Glisse 62771fe6b9SJerome Glisse enum radeon_tv_std { 63771fe6b9SJerome Glisse TV_STD_NTSC, 64771fe6b9SJerome Glisse TV_STD_PAL, 65771fe6b9SJerome Glisse TV_STD_PAL_M, 66771fe6b9SJerome Glisse TV_STD_PAL_60, 67771fe6b9SJerome Glisse TV_STD_NTSC_J, 68771fe6b9SJerome Glisse TV_STD_SCART_PAL, 69771fe6b9SJerome Glisse TV_STD_SECAM, 70771fe6b9SJerome Glisse TV_STD_PAL_CN, 71d79766faSAlex Deucher TV_STD_PAL_N, 72771fe6b9SJerome Glisse }; 73771fe6b9SJerome Glisse 745b1714d3SAlex Deucher enum radeon_underscan_type { 755b1714d3SAlex Deucher UNDERSCAN_OFF, 765b1714d3SAlex Deucher UNDERSCAN_ON, 775b1714d3SAlex Deucher UNDERSCAN_AUTO, 785b1714d3SAlex Deucher }; 795b1714d3SAlex Deucher 808e36ed00SAlex Deucher enum radeon_hpd_id { 818e36ed00SAlex Deucher RADEON_HPD_1 = 0, 828e36ed00SAlex Deucher RADEON_HPD_2, 838e36ed00SAlex Deucher RADEON_HPD_3, 848e36ed00SAlex Deucher RADEON_HPD_4, 858e36ed00SAlex Deucher RADEON_HPD_5, 868e36ed00SAlex Deucher RADEON_HPD_6, 878e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 888e36ed00SAlex Deucher }; 898e36ed00SAlex Deucher 9067ba31d3SAlex Deucher enum radeon_output_csc { 9167ba31d3SAlex Deucher RADEON_OUTPUT_CSC_BYPASS = 0, 9267ba31d3SAlex Deucher RADEON_OUTPUT_CSC_TVRGB = 1, 9367ba31d3SAlex Deucher RADEON_OUTPUT_CSC_YCBCR601 = 2, 9467ba31d3SAlex Deucher RADEON_OUTPUT_CSC_YCBCR709 = 3, 9567ba31d3SAlex Deucher }; 9667ba31d3SAlex Deucher 97f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 98f376b94fSAlex Deucher 999b9fe724SAlex Deucher /* radeon gpio-based i2c 1009b9fe724SAlex Deucher * 1. "mask" reg and bits 1019b9fe724SAlex Deucher * grabs the gpio pins for software use 1029b9fe724SAlex Deucher * 0=not held 1=held 1039b9fe724SAlex Deucher * 2. "a" reg and bits 1049b9fe724SAlex Deucher * output pin value 1059b9fe724SAlex Deucher * 0=low 1=high 1069b9fe724SAlex Deucher * 3. "en" reg and bits 1079b9fe724SAlex Deucher * sets the pin direction 1089b9fe724SAlex Deucher * 0=input 1=output 1099b9fe724SAlex Deucher * 4. "y" reg and bits 1109b9fe724SAlex Deucher * input pin value 1119b9fe724SAlex Deucher * 0=low 1=high 1129b9fe724SAlex Deucher */ 113771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 114771fe6b9SJerome Glisse bool valid; 1156a93cb25SAlex Deucher /* id used by atom */ 1166a93cb25SAlex Deucher uint8_t i2c_id; 117bcc1c2a1SAlex Deucher /* id used by atom */ 1188e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1196a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1206a93cb25SAlex Deucher bool hw_capable; 1216a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1226a93cb25SAlex Deucher bool mm_i2c; 1236a93cb25SAlex Deucher /* regs and bits */ 124771fe6b9SJerome Glisse uint32_t mask_clk_reg; 125771fe6b9SJerome Glisse uint32_t mask_data_reg; 126771fe6b9SJerome Glisse uint32_t a_clk_reg; 127771fe6b9SJerome Glisse uint32_t a_data_reg; 1289b9fe724SAlex Deucher uint32_t en_clk_reg; 1299b9fe724SAlex Deucher uint32_t en_data_reg; 1309b9fe724SAlex Deucher uint32_t y_clk_reg; 1319b9fe724SAlex Deucher uint32_t y_data_reg; 132771fe6b9SJerome Glisse uint32_t mask_clk_mask; 133771fe6b9SJerome Glisse uint32_t mask_data_mask; 134771fe6b9SJerome Glisse uint32_t a_clk_mask; 135771fe6b9SJerome Glisse uint32_t a_data_mask; 1369b9fe724SAlex Deucher uint32_t en_clk_mask; 1379b9fe724SAlex Deucher uint32_t en_data_mask; 1389b9fe724SAlex Deucher uint32_t y_clk_mask; 1399b9fe724SAlex Deucher uint32_t y_data_mask; 140771fe6b9SJerome Glisse }; 141771fe6b9SJerome Glisse 142771fe6b9SJerome Glisse struct radeon_tmds_pll { 143771fe6b9SJerome Glisse uint32_t freq; 144771fe6b9SJerome Glisse uint32_t value; 145771fe6b9SJerome Glisse }; 146771fe6b9SJerome Glisse 147771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 148771fe6b9SJerome Glisse 1497c27f87dSAlex Deucher /* pll flags */ 150771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 151771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 152771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 153771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 154771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 155771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 156771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 157771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 158771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 159771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 160771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 161d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 162fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 16386cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 164f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 165771fe6b9SJerome Glisse 166771fe6b9SJerome Glisse struct radeon_pll { 167fc10332bSAlex Deucher /* reference frequency */ 168fc10332bSAlex Deucher uint32_t reference_freq; 169fc10332bSAlex Deucher 170fc10332bSAlex Deucher /* fixed dividers */ 171fc10332bSAlex Deucher uint32_t reference_div; 172fc10332bSAlex Deucher uint32_t post_div; 173fc10332bSAlex Deucher 174fc10332bSAlex Deucher /* pll in/out limits */ 175771fe6b9SJerome Glisse uint32_t pll_in_min; 176771fe6b9SJerome Glisse uint32_t pll_in_max; 177771fe6b9SJerome Glisse uint32_t pll_out_min; 178771fe6b9SJerome Glisse uint32_t pll_out_max; 17986cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 18086cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 181fc10332bSAlex Deucher uint32_t best_vco; 182771fe6b9SJerome Glisse 183fc10332bSAlex Deucher /* divider limits */ 184771fe6b9SJerome Glisse uint32_t min_ref_div; 185771fe6b9SJerome Glisse uint32_t max_ref_div; 186771fe6b9SJerome Glisse uint32_t min_post_div; 187771fe6b9SJerome Glisse uint32_t max_post_div; 188771fe6b9SJerome Glisse uint32_t min_feedback_div; 189771fe6b9SJerome Glisse uint32_t max_feedback_div; 190771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 191771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 192fc10332bSAlex Deucher 193fc10332bSAlex Deucher /* flags for the current clock */ 194fc10332bSAlex Deucher uint32_t flags; 195fc10332bSAlex Deucher 196fc10332bSAlex Deucher /* pll id */ 197fc10332bSAlex Deucher uint32_t id; 198771fe6b9SJerome Glisse }; 199771fe6b9SJerome Glisse 200771fe6b9SJerome Glisse struct radeon_i2c_chan { 201771fe6b9SJerome Glisse struct i2c_adapter adapter; 202746c1aa4SDave Airlie struct drm_device *dev; 203ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 204771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 205496263bfSAlex Deucher struct drm_dp_aux aux; 206379dfc25SAlex Deucher bool has_aux; 207831719d6SAlex Deucher struct mutex mutex; 208771fe6b9SJerome Glisse }; 209771fe6b9SJerome Glisse 210771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 211771fe6b9SJerome Glisse enum radeon_connector_table { 212aa74fbb4SAlex Deucher CT_NONE = 0, 213771fe6b9SJerome Glisse CT_GENERIC, 214771fe6b9SJerome Glisse CT_IBOOK, 215771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 216771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 217771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 218771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 219771fe6b9SJerome Glisse CT_MINI_INTERNAL, 220771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 221771fe6b9SJerome Glisse CT_EMAC, 22276a7142aSDave Airlie CT_RN50_POWER, 223aa74fbb4SAlex Deucher CT_MAC_X800, 2249fad321aSAlex Deucher CT_MAC_G5_9600, 225cafa59b9SAlex Deucher CT_SAM440EP, 226cafa59b9SAlex Deucher CT_MAC_G4_SILVER 227771fe6b9SJerome Glisse }; 228771fe6b9SJerome Glisse 229fcec570bSAlex Deucher enum radeon_dvo_chip { 230fcec570bSAlex Deucher DVO_SIL164, 231fcec570bSAlex Deucher DVO_SIL1178, 232fcec570bSAlex Deucher }; 233fcec570bSAlex Deucher 2348be48d92SDave Airlie struct radeon_fbdev; 23538651674SDave Airlie 2360783986aSAlex Deucher struct radeon_afmt { 2370783986aSAlex Deucher bool enabled; 2380783986aSAlex Deucher int offset; 2390783986aSAlex Deucher bool last_buffer_filled_status; 2400783986aSAlex Deucher int id; 2410783986aSAlex Deucher }; 2420783986aSAlex Deucher 243771fe6b9SJerome Glisse struct radeon_mode_info { 244771fe6b9SJerome Glisse struct atom_context *atom_context; 24561c4b24bSMathias Fröhlich struct card_info *atom_card_info; 246771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 247771fe6b9SJerome Glisse bool mode_config_initialized; 24888f39063SStefan Brüns struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 24988f39063SStefan Brüns struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 250445282dbSDave Airlie /* DVI-I properties */ 251445282dbSDave Airlie struct drm_property *coherent_mode_property; 252445282dbSDave Airlie /* DAC enable load detect */ 253445282dbSDave Airlie struct drm_property *load_detect_property; 2545b1714d3SAlex Deucher /* TV standard */ 255445282dbSDave Airlie struct drm_property *tv_std_property; 256445282dbSDave Airlie /* legacy TMDS PLL detect */ 257445282dbSDave Airlie struct drm_property *tmds_pll_property; 2585b1714d3SAlex Deucher /* underscan */ 2595b1714d3SAlex Deucher struct drm_property *underscan_property; 2605bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2615bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2628666c076SAlex Deucher /* audio */ 2638666c076SAlex Deucher struct drm_property *audio_property; 2646214bb74SAlex Deucher /* FMT dithering */ 2656214bb74SAlex Deucher struct drm_property *dither_property; 26667ba31d3SAlex Deucher /* Output CSC */ 26767ba31d3SAlex Deucher struct drm_property *output_csc_property; 2683c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2693c537889SAlex Deucher struct edid *bios_hardcoded_edid; 270fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 27138651674SDave Airlie 27238651674SDave Airlie /* pointer to fbdev info structure */ 2738be48d92SDave Airlie struct radeon_fbdev *rfbdev; 274af7912e5SAlex Deucher /* firmware flags */ 275af7912e5SAlex Deucher u16 firmware_flags; 276bced76f2SAlex Deucher /* pointer to backlight encoder */ 277bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 2788f0fc088SDave Airlie 2798f0fc088SDave Airlie /* bitmask for active encoder frontends */ 2808f0fc088SDave Airlie uint32_t active_encoders; 281c93bb85bSJerome Glisse }; 282c93bb85bSJerome Glisse 28391030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 28491030880SAlex Deucher 285bced76f2SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 286bced76f2SAlex Deucher 28791030880SAlex Deucher struct radeon_backlight_privdata { 28891030880SAlex Deucher struct radeon_encoder *encoder; 28991030880SAlex Deucher uint8_t negative; 29091030880SAlex Deucher }; 29191030880SAlex Deucher 29291030880SAlex Deucher #endif 29391030880SAlex Deucher 2944ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2954ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2964ce001abSDave Airlie 2974ce001abSDave Airlie /* need to store these as reading 2984ce001abSDave Airlie back code tables is excessive */ 2994ce001abSDave Airlie struct radeon_tv_regs { 3004ce001abSDave Airlie uint32_t tv_uv_adr; 3014ce001abSDave Airlie uint32_t timing_cntl; 3024ce001abSDave Airlie uint32_t hrestart; 3034ce001abSDave Airlie uint32_t vrestart; 3044ce001abSDave Airlie uint32_t frestart; 3054ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 3064ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 3074ce001abSDave Airlie }; 3084ce001abSDave Airlie 30919eca43eSAlex Deucher struct radeon_atom_ss { 31019eca43eSAlex Deucher uint16_t percentage; 31118f8f52bSAlex Deucher uint16_t percentage_divider; 31219eca43eSAlex Deucher uint8_t type; 31319eca43eSAlex Deucher uint16_t step; 31419eca43eSAlex Deucher uint8_t delay; 31519eca43eSAlex Deucher uint8_t range; 31619eca43eSAlex Deucher uint8_t refdiv; 31719eca43eSAlex Deucher /* asic_ss */ 31819eca43eSAlex Deucher uint16_t rate; 31919eca43eSAlex Deucher uint16_t amount; 32019eca43eSAlex Deucher }; 32119eca43eSAlex Deucher 322a2b6d3b3SMichel Dänzer enum radeon_flip_status { 323a2b6d3b3SMichel Dänzer RADEON_FLIP_NONE, 324a2b6d3b3SMichel Dänzer RADEON_FLIP_PENDING, 325a2b6d3b3SMichel Dänzer RADEON_FLIP_SUBMITTED 326a2b6d3b3SMichel Dänzer }; 327a2b6d3b3SMichel Dänzer 328771fe6b9SJerome Glisse struct radeon_crtc { 329771fe6b9SJerome Glisse struct drm_crtc base; 330771fe6b9SJerome Glisse int crtc_id; 331771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 332771fe6b9SJerome Glisse bool enabled; 333771fe6b9SJerome Glisse bool can_tile; 3346b16cf77SMichel Dänzer bool cursor_out_of_bounds; 335771fe6b9SJerome Glisse uint32_t crtc_offset; 336771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 337771fe6b9SJerome Glisse uint64_t cursor_addr; 33878b1a601SMichel Dänzer int cursor_x; 33978b1a601SMichel Dänzer int cursor_y; 34078b1a601SMichel Dänzer int cursor_hot_x; 34178b1a601SMichel Dänzer int cursor_hot_y; 342771fe6b9SJerome Glisse int cursor_width; 343771fe6b9SJerome Glisse int cursor_height; 3449e05fa1dSAlex Deucher int max_cursor_width; 3459e05fa1dSAlex Deucher int max_cursor_height; 3464162338aSDave Airlie uint32_t legacy_display_base_addr; 347c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3485b1714d3SAlex Deucher u8 h_border; 3495b1714d3SAlex Deucher u8 v_border; 350c93bb85bSJerome Glisse fixed20_12 vsc; 351c93bb85bSJerome Glisse fixed20_12 hsc; 352de2103e4SAlex Deucher struct drm_display_mode native_mode; 353bcc1c2a1SAlex Deucher int pll_id; 3546f34be50SAlex Deucher /* page flipping */ 355fa7f517cSChristian König struct workqueue_struct *flip_queue; 356fa7f517cSChristian König struct radeon_flip_work *flip_work; 357a2b6d3b3SMichel Dänzer enum radeon_flip_status flip_status; 35819eca43eSAlex Deucher /* pll sharing */ 35919eca43eSAlex Deucher struct radeon_atom_ss ss; 36019eca43eSAlex Deucher bool ss_enabled; 36119eca43eSAlex Deucher u32 adjusted_clock; 36219eca43eSAlex Deucher int bpc; 36319eca43eSAlex Deucher u32 pll_reference_div; 36419eca43eSAlex Deucher u32 pll_post_div; 36519eca43eSAlex Deucher u32 pll_flags; 3665df3196bSAlex Deucher struct drm_encoder *encoder; 36757b35e29SAlex Deucher struct drm_connector *connector; 3687178d2a6SAlex Deucher /* for dpm */ 3697178d2a6SAlex Deucher u32 line_time; 3707178d2a6SAlex Deucher u32 wm_low; 3717178d2a6SAlex Deucher u32 wm_high; 3725b5561b3SMario Kleiner u32 lb_vblank_lead_lines; 37366edc1c9SAlex Deucher struct drm_display_mode hw_mode; 374643b1f56SAlex Deucher enum radeon_output_csc output_csc; 375771fe6b9SJerome Glisse }; 376771fe6b9SJerome Glisse 377771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 378771fe6b9SJerome Glisse /* legacy primary dac */ 379771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 380771fe6b9SJerome Glisse }; 381771fe6b9SJerome Glisse 382771fe6b9SJerome Glisse struct radeon_encoder_lvds { 383771fe6b9SJerome Glisse /* legacy lvds */ 384771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 385771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 386771fe6b9SJerome Glisse uint8_t panel_digon_delay; 387771fe6b9SJerome Glisse uint8_t panel_blon_delay; 388771fe6b9SJerome Glisse uint16_t panel_ref_divider; 389771fe6b9SJerome Glisse uint8_t panel_post_divider; 390771fe6b9SJerome Glisse uint16_t panel_fb_divider; 391771fe6b9SJerome Glisse bool use_bios_dividers; 392771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 393771fe6b9SJerome Glisse /* panel mode */ 394de2103e4SAlex Deucher struct drm_display_mode native_mode; 39563ec0119SMichel Dänzer struct backlight_device *bl_dev; 39663ec0119SMichel Dänzer int dpms_mode; 39763ec0119SMichel Dänzer uint8_t backlight_level; 398771fe6b9SJerome Glisse }; 399771fe6b9SJerome Glisse 400771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 401771fe6b9SJerome Glisse /* legacy tv dac */ 402771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 403771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 404771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 405771fe6b9SJerome Glisse 4064ce001abSDave Airlie int h_pos; 4074ce001abSDave Airlie int v_pos; 4084ce001abSDave Airlie int h_size; 4094ce001abSDave Airlie int supported_tv_stds; 4104ce001abSDave Airlie bool tv_on; 411771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 4124ce001abSDave Airlie struct radeon_tv_regs tv; 413771fe6b9SJerome Glisse }; 414771fe6b9SJerome Glisse 415771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 416771fe6b9SJerome Glisse /* legacy int tmds */ 417771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 418771fe6b9SJerome Glisse }; 419771fe6b9SJerome Glisse 420fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 421fcec570bSAlex Deucher /* tmds over dvo */ 422fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 423fcec570bSAlex Deucher uint8_t slave_addr; 424fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 425fcec570bSAlex Deucher }; 426fcec570bSAlex Deucher 427ebbe1cb9SAlex Deucher /* spread spectrum */ 428771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 4295137ee94SAlex Deucher bool linkb; 430771fe6b9SJerome Glisse /* atom dig */ 431771fe6b9SJerome Glisse bool coherent_mode; 432ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 433ba032a58SAlex Deucher /* atom lvds/edp */ 434ba032a58SAlex Deucher uint32_t lcd_misc; 435771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 436ba032a58SAlex Deucher uint32_t lcd_ss_id; 437771fe6b9SJerome Glisse /* panel mode */ 438de2103e4SAlex Deucher struct drm_display_mode native_mode; 43963ec0119SMichel Dänzer struct backlight_device *bl_dev; 44063ec0119SMichel Dänzer int dpms_mode; 44163ec0119SMichel Dänzer uint8_t backlight_level; 442386d4d75SAlex Deucher int panel_mode; 4430783986aSAlex Deucher struct radeon_afmt *afmt; 444d0ea397eSAlex Deucher struct r600_audio_pin *pin; 4459843ead0SDave Airlie int active_mst_links; 446771fe6b9SJerome Glisse }; 447771fe6b9SJerome Glisse 4484ce001abSDave Airlie struct radeon_encoder_atom_dac { 4494ce001abSDave Airlie enum radeon_tv_std tv_std; 4504ce001abSDave Airlie }; 4514ce001abSDave Airlie 4529843ead0SDave Airlie struct radeon_encoder_mst { 4539843ead0SDave Airlie int crtc; 4549843ead0SDave Airlie struct radeon_encoder *primary; 4559843ead0SDave Airlie struct radeon_connector *connector; 4569843ead0SDave Airlie struct drm_dp_mst_port *port; 4579843ead0SDave Airlie int pbn; 4589843ead0SDave Airlie int fe; 4599843ead0SDave Airlie bool fe_from_be; 4609843ead0SDave Airlie bool enc_active; 4619843ead0SDave Airlie }; 4629843ead0SDave Airlie 463771fe6b9SJerome Glisse struct radeon_encoder { 464771fe6b9SJerome Glisse struct drm_encoder base; 4655137ee94SAlex Deucher uint32_t encoder_enum; 466771fe6b9SJerome Glisse uint32_t encoder_id; 467771fe6b9SJerome Glisse uint32_t devices; 4684ce001abSDave Airlie uint32_t active_device; 469771fe6b9SJerome Glisse uint32_t flags; 470771fe6b9SJerome Glisse uint32_t pixel_clock; 471771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4725b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4735bccf5e3SMarius Gröger uint32_t underscan_hborder; 4745bccf5e3SMarius Gröger uint32_t underscan_vborder; 475de2103e4SAlex Deucher struct drm_display_mode native_mode; 476771fe6b9SJerome Glisse void *enc_priv; 47758bd0863SChristian König int audio_polling_active; 4783e4b9982SAlex Deucher bool is_ext_encoder; 47936868bdaSAlex Deucher u16 caps; 4801a626b68SSlava Grigorev struct radeon_audio_funcs *audio; 481643b1f56SAlex Deucher enum radeon_output_csc output_csc; 4829843ead0SDave Airlie bool can_mst; 4839843ead0SDave Airlie uint32_t offset; 4849843ead0SDave Airlie bool is_mst_encoder; 4859843ead0SDave Airlie /* front end for this mst encoder */ 486771fe6b9SJerome Glisse }; 487771fe6b9SJerome Glisse 488771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 489771fe6b9SJerome Glisse uint32_t igp_lane_info; 4904143e919SAlex Deucher /* displayport */ 4911a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4924143e919SAlex Deucher u8 dp_sink_type; 4935801ead6SAlex Deucher int dp_clock; 4945801ead6SAlex Deucher int dp_lane_count; 4958b834852SAlex Deucher bool edp_on; 4969843ead0SDave Airlie bool is_mst; 497771fe6b9SJerome Glisse }; 498771fe6b9SJerome Glisse 499eed45b30SAlex Deucher struct radeon_gpio_rec { 500eed45b30SAlex Deucher bool valid; 501eed45b30SAlex Deucher u8 id; 502eed45b30SAlex Deucher u32 reg; 503eed45b30SAlex Deucher u32 mask; 504727b3d25SAlex Deucher u32 shift; 505eed45b30SAlex Deucher }; 506eed45b30SAlex Deucher 507eed45b30SAlex Deucher struct radeon_hpd { 508eed45b30SAlex Deucher enum radeon_hpd_id hpd; 509eed45b30SAlex Deucher u8 plugged_state; 510eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 511eed45b30SAlex Deucher }; 512eed45b30SAlex Deucher 51326b5bc98SAlex Deucher struct radeon_router { 51426b5bc98SAlex Deucher u32 router_id; 51526b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 51626b5bc98SAlex Deucher u8 i2c_addr; 517fb939dfcSAlex Deucher /* i2c mux */ 518fb939dfcSAlex Deucher bool ddc_valid; 519fb939dfcSAlex Deucher u8 ddc_mux_type; 520fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 521fb939dfcSAlex Deucher u8 ddc_mux_state; 522fb939dfcSAlex Deucher /* clock/data mux */ 523fb939dfcSAlex Deucher bool cd_valid; 524fb939dfcSAlex Deucher u8 cd_mux_type; 525fb939dfcSAlex Deucher u8 cd_mux_control_pin; 526fb939dfcSAlex Deucher u8 cd_mux_state; 52726b5bc98SAlex Deucher }; 52826b5bc98SAlex Deucher 5298666c076SAlex Deucher enum radeon_connector_audio { 5308666c076SAlex Deucher RADEON_AUDIO_DISABLE = 0, 5318666c076SAlex Deucher RADEON_AUDIO_ENABLE = 1, 5328666c076SAlex Deucher RADEON_AUDIO_AUTO = 2 5338666c076SAlex Deucher }; 5348666c076SAlex Deucher 5356214bb74SAlex Deucher enum radeon_connector_dither { 5366214bb74SAlex Deucher RADEON_FMT_DITHER_DISABLE = 0, 5376214bb74SAlex Deucher RADEON_FMT_DITHER_ENABLE = 1, 5386214bb74SAlex Deucher }; 5396214bb74SAlex Deucher 5409843ead0SDave Airlie struct stream_attribs { 5419843ead0SDave Airlie uint16_t fe; 5429843ead0SDave Airlie uint16_t slots; 5439843ead0SDave Airlie }; 5449843ead0SDave Airlie 545771fe6b9SJerome Glisse struct radeon_connector { 546771fe6b9SJerome Glisse struct drm_connector base; 547771fe6b9SJerome Glisse uint32_t connector_id; 548771fe6b9SJerome Glisse uint32_t devices; 549771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 5505b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 5510294cf4fSAlex Deucher bool shared_ddc; 5524ce001abSDave Airlie bool use_digital; 5534ce001abSDave Airlie /* we need to mind the EDID between detect 5544ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 5554ce001abSDave Airlie struct edid *edid; 556771fe6b9SJerome Glisse void *con_priv; 557445282dbSDave Airlie bool dac_load_detect; 558d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 559cb5d4166SLyude bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 560b75fad06SAlex Deucher uint16_t connector_object_id; 561eed45b30SAlex Deucher struct radeon_hpd hpd; 56226b5bc98SAlex Deucher struct radeon_router router; 56326b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 5648666c076SAlex Deucher enum radeon_connector_audio audio; 5656214bb74SAlex Deucher enum radeon_connector_dither dither; 566ea292861SMario Kleiner int pixelclock_for_modeset; 5679843ead0SDave Airlie bool is_mst_connector; 5689843ead0SDave Airlie struct radeon_connector *mst_port; 5699843ead0SDave Airlie struct drm_dp_mst_port *port; 5709843ead0SDave Airlie struct drm_dp_mst_topology_mgr mst_mgr; 5719843ead0SDave Airlie 5729843ead0SDave Airlie struct radeon_encoder *mst_encoder; 5739843ead0SDave Airlie struct stream_attribs cur_stream_attribs[6]; 5749843ead0SDave Airlie int enabled_attribs; 575771fe6b9SJerome Glisse }; 576771fe6b9SJerome Glisse 577771fe6b9SJerome Glisse struct radeon_framebuffer { 578771fe6b9SJerome Glisse struct drm_framebuffer base; 579771fe6b9SJerome Glisse struct drm_gem_object *obj; 580771fe6b9SJerome Glisse }; 581771fe6b9SJerome Glisse 582996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 583996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 5846383cf7dSMario Kleiner 5857062ab67SChristian König struct atom_clock_dividers { 5867062ab67SChristian König u32 post_div; 5877062ab67SChristian König union { 5887062ab67SChristian König struct { 5897062ab67SChristian König #ifdef __BIG_ENDIAN 5907062ab67SChristian König u32 reserved : 6; 5917062ab67SChristian König u32 whole_fb_div : 12; 5927062ab67SChristian König u32 frac_fb_div : 14; 5937062ab67SChristian König #else 5947062ab67SChristian König u32 frac_fb_div : 14; 5957062ab67SChristian König u32 whole_fb_div : 12; 5967062ab67SChristian König u32 reserved : 6; 5977062ab67SChristian König #endif 5987062ab67SChristian König }; 5997062ab67SChristian König u32 fb_div; 6007062ab67SChristian König }; 6017062ab67SChristian König u32 ref_div; 6027062ab67SChristian König bool enable_post_div; 6037062ab67SChristian König bool enable_dithen; 6047062ab67SChristian König u32 vco_mode; 6057062ab67SChristian König u32 real_clock; 6069219ed65SAlex Deucher /* added for CI */ 6079219ed65SAlex Deucher u32 post_divider; 6089219ed65SAlex Deucher u32 flags; 6097062ab67SChristian König }; 6107062ab67SChristian König 611eaa778afSAlex Deucher struct atom_mpll_param { 612eaa778afSAlex Deucher union { 613eaa778afSAlex Deucher struct { 614eaa778afSAlex Deucher #ifdef __BIG_ENDIAN 615eaa778afSAlex Deucher u32 reserved : 8; 616eaa778afSAlex Deucher u32 clkfrac : 12; 617eaa778afSAlex Deucher u32 clkf : 12; 618eaa778afSAlex Deucher #else 619eaa778afSAlex Deucher u32 clkf : 12; 620eaa778afSAlex Deucher u32 clkfrac : 12; 621eaa778afSAlex Deucher u32 reserved : 8; 622eaa778afSAlex Deucher #endif 623eaa778afSAlex Deucher }; 624eaa778afSAlex Deucher u32 fb_div; 625eaa778afSAlex Deucher }; 626eaa778afSAlex Deucher u32 post_div; 627eaa778afSAlex Deucher u32 bwcntl; 628eaa778afSAlex Deucher u32 dll_speed; 629eaa778afSAlex Deucher u32 vco_mode; 630eaa778afSAlex Deucher u32 yclk_sel; 631eaa778afSAlex Deucher u32 qdr; 632eaa778afSAlex Deucher u32 half_rate; 633eaa778afSAlex Deucher }; 634eaa778afSAlex Deucher 635ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR5 0x50 636ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR4 0x40 637ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR3 0x30 638ae5b0abbSAlex Deucher #define MEM_TYPE_DDR2 0x20 639ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR1 0x10 640ae5b0abbSAlex Deucher #define MEM_TYPE_DDR3 0xb0 641ae5b0abbSAlex Deucher #define MEM_TYPE_MASK 0xf0 642ae5b0abbSAlex Deucher 643ae5b0abbSAlex Deucher struct atom_memory_info { 644ae5b0abbSAlex Deucher u8 mem_vendor; 645ae5b0abbSAlex Deucher u8 mem_type; 646ae5b0abbSAlex Deucher }; 647ae5b0abbSAlex Deucher 648ae5b0abbSAlex Deucher #define MAX_AC_TIMING_ENTRIES 16 649ae5b0abbSAlex Deucher 650ae5b0abbSAlex Deucher struct atom_memory_clock_range_table 651ae5b0abbSAlex Deucher { 652ae5b0abbSAlex Deucher u8 num_entries; 653ae5b0abbSAlex Deucher u8 rsv[3]; 654ae5b0abbSAlex Deucher u32 mclk[MAX_AC_TIMING_ENTRIES]; 655ae5b0abbSAlex Deucher }; 656ae5b0abbSAlex Deucher 657ae5b0abbSAlex Deucher #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 658ae5b0abbSAlex Deucher #define VBIOS_MAX_AC_TIMING_ENTRIES 20 659ae5b0abbSAlex Deucher 660ae5b0abbSAlex Deucher struct atom_mc_reg_entry { 661ae5b0abbSAlex Deucher u32 mclk_max; 662ae5b0abbSAlex Deucher u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 663ae5b0abbSAlex Deucher }; 664ae5b0abbSAlex Deucher 665ae5b0abbSAlex Deucher struct atom_mc_register_address { 666ae5b0abbSAlex Deucher u16 s1; 667ae5b0abbSAlex Deucher u8 pre_reg_data; 668ae5b0abbSAlex Deucher }; 669ae5b0abbSAlex Deucher 670ae5b0abbSAlex Deucher struct atom_mc_reg_table { 671ae5b0abbSAlex Deucher u8 last; 672ae5b0abbSAlex Deucher u8 num_entries; 673ae5b0abbSAlex Deucher struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 674ae5b0abbSAlex Deucher struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 675ae5b0abbSAlex Deucher }; 676ae5b0abbSAlex Deucher 677ae5b0abbSAlex Deucher #define MAX_VOLTAGE_ENTRIES 32 678ae5b0abbSAlex Deucher 679ae5b0abbSAlex Deucher struct atom_voltage_table_entry 680ae5b0abbSAlex Deucher { 681ae5b0abbSAlex Deucher u16 value; 682ae5b0abbSAlex Deucher u32 smio_low; 683ae5b0abbSAlex Deucher }; 684ae5b0abbSAlex Deucher 685ae5b0abbSAlex Deucher struct atom_voltage_table 686ae5b0abbSAlex Deucher { 687ae5b0abbSAlex Deucher u32 count; 688ae5b0abbSAlex Deucher u32 mask_low; 68965171944SAlex Deucher u32 phase_delay; 690ae5b0abbSAlex Deucher struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 691ae5b0abbSAlex Deucher }; 692ae5b0abbSAlex Deucher 6935b5561b3SMario Kleiner /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 6945b5561b3SMario Kleiner #define USE_REAL_VBLANKSTART (1 << 30) 6955b5561b3SMario Kleiner #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 696a38eab52SRashika Kheria 697a38eab52SRashika Kheria extern void 698a38eab52SRashika Kheria radeon_add_atom_connector(struct drm_device *dev, 699a38eab52SRashika Kheria uint32_t connector_id, 700a38eab52SRashika Kheria uint32_t supported_device, 701a38eab52SRashika Kheria int connector_type, 702a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 703a38eab52SRashika Kheria uint32_t igp_lane_info, 704a38eab52SRashika Kheria uint16_t connector_object_id, 705a38eab52SRashika Kheria struct radeon_hpd *hpd, 706a38eab52SRashika Kheria struct radeon_router *router); 707a38eab52SRashika Kheria extern void 708a38eab52SRashika Kheria radeon_add_legacy_connector(struct drm_device *dev, 709a38eab52SRashika Kheria uint32_t connector_id, 710a38eab52SRashika Kheria uint32_t supported_device, 711a38eab52SRashika Kheria int connector_type, 712a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 713a38eab52SRashika Kheria uint16_t connector_object_id, 714a38eab52SRashika Kheria struct radeon_hpd *hpd); 7150091fc13SRashika Kheria extern uint32_t 7160091fc13SRashika Kheria radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 7170091fc13SRashika Kheria uint8_t dac); 7180091fc13SRashika Kheria extern void radeon_link_encoder_connector(struct drm_device *dev); 719a38eab52SRashika Kheria 720d79766faSAlex Deucher extern enum radeon_tv_std 721d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 722d79766faSAlex Deucher extern enum radeon_tv_std 723d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 7244a6369e9SAlex Deucher extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 7252abba66eSAlex Deucher u16 *vddc, u16 *vddci, u16 *mvdd); 726d79766faSAlex Deucher 72784ac68e0SAlex Deucher extern void 72884ac68e0SAlex Deucher radeon_combios_connected_scratch_regs(struct drm_connector *connector, 72984ac68e0SAlex Deucher struct drm_encoder *encoder, 73084ac68e0SAlex Deucher bool connected); 73184ac68e0SAlex Deucher extern void 73284ac68e0SAlex Deucher radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 73384ac68e0SAlex Deucher struct drm_encoder *encoder, 73484ac68e0SAlex Deucher bool connected); 73584ac68e0SAlex Deucher 7365b1714d3SAlex Deucher extern struct drm_connector * 7375b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 7389aa59993SAlex Deucher extern struct drm_connector * 7399aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 7409aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 7419aa59993SAlex Deucher u32 pixel_clock); 7425b1714d3SAlex Deucher 7431d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 7441d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 745d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 746eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 747d7fa8bb3SAlex Deucher 748377bd8a9SAlex Deucher extern struct edid *radeon_connector_edid(struct drm_connector *connector); 749377bd8a9SAlex Deucher 750d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 751224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 7525801ead6SAlex Deucher struct drm_display_mode *mode); 7535801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 754e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 755224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 7565801ead6SAlex Deucher struct drm_connector *connector); 757d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 7584143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 7599fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 760386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 761386d4d75SAlex Deucher struct drm_connector *connector); 762092c96a8SAlex Deucher extern int radeon_dp_get_dp_link_config(struct drm_connector *connector, 763092c96a8SAlex Deucher const u8 *dpcd, 764092c96a8SAlex Deucher unsigned pix_clock, 765092c96a8SAlex Deucher unsigned *dp_lanes, unsigned *dp_rate); 7662953da15SAlex Deucher extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 7672953da15SAlex Deucher u8 power_state); 768496263bfSAlex Deucher extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 769875711f0SDave Airlie extern ssize_t 770875711f0SDave Airlie radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 771875711f0SDave Airlie 772558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 773bf071900SDave Airlie extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 774ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 775f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 7765801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 7775801ead6SAlex Deucher int action, uint8_t lane_num, 7785801ead6SAlex Deucher uint8_t lane_set); 779bf071900SDave Airlie extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 780bf071900SDave Airlie int action, uint8_t lane_num, 781bf071900SDave Airlie uint8_t lane_set, int fe); 7829843ead0SDave Airlie extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, 7839843ead0SDave Airlie int fe); 784591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 7853f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 7864cf3b494SRashika Kheria void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 787746c1aa4SDave Airlie 788f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 789f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 790f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 791f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 792f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 793f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 794f376b94fSAlex Deucher const char *name); 795f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 796f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 797771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 798771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 799771fe6b9SJerome Glisse const char *name); 800771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 8015a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 802fcec570bSAlex Deucher u8 slave_addr, 803fcec570bSAlex Deucher u8 addr, 804fcec570bSAlex Deucher u8 *val); 8055a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 806fcec570bSAlex Deucher u8 slave_addr, 807fcec570bSAlex Deucher u8 addr, 808fcec570bSAlex Deucher u8 val); 809fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 810fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 8110a9069d3SNiels Ole Salscheider extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 812771fe6b9SJerome Glisse 813ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 814ba032a58SAlex Deucher struct radeon_atom_ss *ss, 815ba032a58SAlex Deucher int id); 816ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 817ba032a58SAlex Deucher struct radeon_atom_ss *ss, 818ba032a58SAlex Deucher int id, u32 clock); 81909e619c0SAlex Deucher extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 82009e619c0SAlex Deucher u8 id); 821ba032a58SAlex Deucher 822f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 823771fe6b9SJerome Glisse uint64_t freq, 824771fe6b9SJerome Glisse uint32_t *dot_clock_p, 825771fe6b9SJerome Glisse uint32_t *fb_div_p, 826771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 827771fe6b9SJerome Glisse uint32_t *ref_div_p, 828fc10332bSAlex Deucher uint32_t *post_div_p); 829771fe6b9SJerome Glisse 830f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 831f523f74eSAlex Deucher u32 freq, 832f523f74eSAlex Deucher u32 *dot_clock_p, 833f523f74eSAlex Deucher u32 *fb_div_p, 834f523f74eSAlex Deucher u32 *frac_fb_div_p, 835f523f74eSAlex Deucher u32 *ref_div_p, 836f523f74eSAlex Deucher u32 *post_div_p); 837f523f74eSAlex Deucher 8381f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 8391f3b6a45SDave Airlie 840771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 841771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 842771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 843771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 844771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 84599999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 84632f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 847771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 8482dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 8494ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 850d740a933SAlex Deucher extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 851771fe6b9SJerome Glisse 852771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 853771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 854771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8554dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 8564dd19b0dSChris Ball struct drm_framebuffer *fb, 85721c74a8eSJason Wessel int x, int y, 85821c74a8eSJason Wessel enum mode_set_atomic state); 859771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 860771fe6b9SJerome Glisse struct drm_display_mode *mode, 861771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 862771fe6b9SJerome Glisse int x, int y, 863771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 864771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 865771fe6b9SJerome Glisse 866771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 867771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8684dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 8694dd19b0dSChris Ball struct drm_framebuffer *fb, 87021c74a8eSJason Wessel int x, int y, 87121c74a8eSJason Wessel enum mode_set_atomic state); 8724dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 8734dd19b0dSChris Ball struct drm_framebuffer *fb, 8744dd19b0dSChris Ball int x, int y, int atomic); 87578b1a601SMichel Dänzer extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 876771fe6b9SJerome Glisse struct drm_file *file_priv, 877771fe6b9SJerome Glisse uint32_t handle, 878771fe6b9SJerome Glisse uint32_t width, 87978b1a601SMichel Dänzer uint32_t height, 88078b1a601SMichel Dänzer int32_t hot_x, 88178b1a601SMichel Dänzer int32_t hot_y); 882771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 883771fe6b9SJerome Glisse int x, int y); 8846d3759faSMichel Dänzer extern void radeon_cursor_reset(struct drm_crtc *crtc); 885771fe6b9SJerome Glisse 88688e72717SThierry Reding extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 88788e72717SThierry Reding unsigned int flags, int *vpos, int *hpos, 8883bb403bfSVille Syrjälä ktime_t *stime, ktime_t *etime, 8893bb403bfSVille Syrjälä const struct drm_display_mode *mode); 8906383cf7dSMario Kleiner 8913c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 8923c537889SAlex Deucher extern struct edid * 893c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 894771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 895771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 896771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 897771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 898fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 899445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 900fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 901445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 902fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 903445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 904fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 905fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 906fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 907fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 9086fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 9096fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 9106fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 9116fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 912771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 913771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 914771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 915771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 916771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 917771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 918771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 919fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 920fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 921771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 922771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 923771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 924771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 925f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 926f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 927771fe6b9SJerome Glisse extern void 928771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 929771fe6b9SJerome Glisse extern void 930771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 931771fe6b9SJerome Glisse extern void 932771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 933771fe6b9SJerome Glisse extern void 934771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 935771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 936771fe6b9SJerome Glisse u16 blue, int regno); 937b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 938b8c00ac5SDave Airlie u16 *blue, int regno); 939aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 94038651674SDave Airlie struct radeon_framebuffer *rfb, 9411eb83451SVille Syrjälä const struct drm_mode_fb_cmd2 *mode_cmd, 942771fe6b9SJerome Glisse struct drm_gem_object *obj); 943771fe6b9SJerome Glisse 944771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 945771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 946771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 947771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 948771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 949771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 950771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 951771fe6b9SJerome Glisse 952771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 953771fe6b9SJerome Glisse 954771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 955771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 956771fe6b9SJerome Glisse 957771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 958771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 959771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 960c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 961e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 962c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 9633515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 9643515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 9654ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 966771fe6b9SJerome Glisse 9674ce001abSDave Airlie /* legacy tv */ 9684ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 9694ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 9704ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 9714ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 9724ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 9734ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 9744ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 9754ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 9764ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 9774ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 9784ce001abSDave Airlie struct drm_display_mode *mode, 9794ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 98038651674SDave Airlie 981134b480fSAlex Deucher /* fmt blocks */ 982134b480fSAlex Deucher void avivo_program_fmt(struct drm_encoder *encoder); 983134b480fSAlex Deucher void dce3_program_fmt(struct drm_encoder *encoder); 984134b480fSAlex Deucher void dce4_program_fmt(struct drm_encoder *encoder); 985134b480fSAlex Deucher void dce8_program_fmt(struct drm_encoder *encoder); 986134b480fSAlex Deucher 98738651674SDave Airlie /* fbdev layer */ 98838651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 98938651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 99038651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 99138651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 9928c70e1cdSAlex Deucher void radeon_fbdev_restore_mode(struct radeon_device *rdev); 993eb1f8e4fSDave Airlie 994eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 9956f34be50SAlex Deucher 9961a0e7918SChristian König void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 997bb26270eSDave Airlie 998bb26270eSDave Airlie void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); 999bb26270eSDave Airlie void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); 1000bb26270eSDave Airlie 10016f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 10026f34be50SAlex Deucher 1003ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 10048f0fc088SDave Airlie 10059843ead0SDave Airlie /* mst */ 10069843ead0SDave Airlie int radeon_dp_mst_init(struct radeon_connector *radeon_connector); 10079843ead0SDave Airlie int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); 10089843ead0SDave Airlie int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); 10099843ead0SDave Airlie int radeon_mst_debugfs_init(struct radeon_device *rdev); 10109843ead0SDave Airlie void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); 10119843ead0SDave Airlie 10129843ead0SDave Airlie void radeon_setup_mst_connector(struct drm_device *dev); 10139843ead0SDave Airlie 10148f0fc088SDave Airlie int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 10158f0fc088SDave Airlie void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 1016771fe6b9SJerome Glisse #endif 1017