1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3771fe6b9SJerome Glisse  *                VA Linux Systems Inc., Fremont, California.
4771fe6b9SJerome Glisse  * Copyright 2008 Red Hat Inc.
5771fe6b9SJerome Glisse  *
6771fe6b9SJerome Glisse  * Permission is hereby granted, free of charge, to any person obtaining a
7771fe6b9SJerome Glisse  * copy of this software and associated documentation files (the "Software"),
8771fe6b9SJerome Glisse  * to deal in the Software without restriction, including without limitation
9771fe6b9SJerome Glisse  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10771fe6b9SJerome Glisse  * and/or sell copies of the Software, and to permit persons to whom the
11771fe6b9SJerome Glisse  * Software is furnished to do so, subject to the following conditions:
12771fe6b9SJerome Glisse  *
13771fe6b9SJerome Glisse  * The above copyright notice and this permission notice shall be included in
14771fe6b9SJerome Glisse  * all copies or substantial portions of the Software.
15771fe6b9SJerome Glisse  *
16771fe6b9SJerome Glisse  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17771fe6b9SJerome Glisse  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18771fe6b9SJerome Glisse  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19771fe6b9SJerome Glisse  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20771fe6b9SJerome Glisse  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21771fe6b9SJerome Glisse  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22771fe6b9SJerome Glisse  * OTHER DEALINGS IN THE SOFTWARE.
23771fe6b9SJerome Glisse  *
24771fe6b9SJerome Glisse  * Original Authors:
25771fe6b9SJerome Glisse  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26771fe6b9SJerome Glisse  *
27771fe6b9SJerome Glisse  * Kernel port Author: Dave Airlie
28771fe6b9SJerome Glisse  */
29771fe6b9SJerome Glisse 
30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H
31771fe6b9SJerome Glisse #define RADEON_MODE_H
32771fe6b9SJerome Glisse 
33771fe6b9SJerome Glisse #include <drm_crtc.h>
34771fe6b9SJerome Glisse #include <drm_mode.h>
35771fe6b9SJerome Glisse #include <drm_edid.h>
36746c1aa4SDave Airlie #include <drm_dp_helper.h>
3768adac5eSBen Skeggs #include <drm_fixed.h>
38771fe6b9SJerome Glisse #include <linux/i2c.h>
39771fe6b9SJerome Glisse #include <linux/i2c-id.h>
40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h>
41c93bb85bSJerome Glisse 
4238651674SDave Airlie struct radeon_bo;
43c93bb85bSJerome Glisse struct radeon_device;
44771fe6b9SJerome Glisse 
45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49771fe6b9SJerome Glisse 
50771fe6b9SJerome Glisse enum radeon_rmx_type {
51771fe6b9SJerome Glisse 	RMX_OFF,
52771fe6b9SJerome Glisse 	RMX_FULL,
53771fe6b9SJerome Glisse 	RMX_CENTER,
54771fe6b9SJerome Glisse 	RMX_ASPECT
55771fe6b9SJerome Glisse };
56771fe6b9SJerome Glisse 
57771fe6b9SJerome Glisse enum radeon_tv_std {
58771fe6b9SJerome Glisse 	TV_STD_NTSC,
59771fe6b9SJerome Glisse 	TV_STD_PAL,
60771fe6b9SJerome Glisse 	TV_STD_PAL_M,
61771fe6b9SJerome Glisse 	TV_STD_PAL_60,
62771fe6b9SJerome Glisse 	TV_STD_NTSC_J,
63771fe6b9SJerome Glisse 	TV_STD_SCART_PAL,
64771fe6b9SJerome Glisse 	TV_STD_SECAM,
65771fe6b9SJerome Glisse 	TV_STD_PAL_CN,
66d79766faSAlex Deucher 	TV_STD_PAL_N,
67771fe6b9SJerome Glisse };
68771fe6b9SJerome Glisse 
698e36ed00SAlex Deucher enum radeon_hpd_id {
708e36ed00SAlex Deucher 	RADEON_HPD_1 = 0,
718e36ed00SAlex Deucher 	RADEON_HPD_2,
728e36ed00SAlex Deucher 	RADEON_HPD_3,
738e36ed00SAlex Deucher 	RADEON_HPD_4,
748e36ed00SAlex Deucher 	RADEON_HPD_5,
758e36ed00SAlex Deucher 	RADEON_HPD_6,
768e36ed00SAlex Deucher 	RADEON_HPD_NONE = 0xff,
778e36ed00SAlex Deucher };
788e36ed00SAlex Deucher 
799b9fe724SAlex Deucher /* radeon gpio-based i2c
809b9fe724SAlex Deucher  * 1. "mask" reg and bits
819b9fe724SAlex Deucher  *    grabs the gpio pins for software use
829b9fe724SAlex Deucher  *    0=not held  1=held
839b9fe724SAlex Deucher  * 2. "a" reg and bits
849b9fe724SAlex Deucher  *    output pin value
859b9fe724SAlex Deucher  *    0=low 1=high
869b9fe724SAlex Deucher  * 3. "en" reg and bits
879b9fe724SAlex Deucher  *    sets the pin direction
889b9fe724SAlex Deucher  *    0=input 1=output
899b9fe724SAlex Deucher  * 4. "y" reg and bits
909b9fe724SAlex Deucher  *    input pin value
919b9fe724SAlex Deucher  *    0=low 1=high
929b9fe724SAlex Deucher  */
93771fe6b9SJerome Glisse struct radeon_i2c_bus_rec {
94771fe6b9SJerome Glisse 	bool valid;
956a93cb25SAlex Deucher 	/* id used by atom */
966a93cb25SAlex Deucher 	uint8_t i2c_id;
97bcc1c2a1SAlex Deucher 	/* id used by atom */
988e36ed00SAlex Deucher 	enum radeon_hpd_id hpd;
996a93cb25SAlex Deucher 	/* can be used with hw i2c engine */
1006a93cb25SAlex Deucher 	bool hw_capable;
1016a93cb25SAlex Deucher 	/* uses multi-media i2c engine */
1026a93cb25SAlex Deucher 	bool mm_i2c;
1036a93cb25SAlex Deucher 	/* regs and bits */
104771fe6b9SJerome Glisse 	uint32_t mask_clk_reg;
105771fe6b9SJerome Glisse 	uint32_t mask_data_reg;
106771fe6b9SJerome Glisse 	uint32_t a_clk_reg;
107771fe6b9SJerome Glisse 	uint32_t a_data_reg;
1089b9fe724SAlex Deucher 	uint32_t en_clk_reg;
1099b9fe724SAlex Deucher 	uint32_t en_data_reg;
1109b9fe724SAlex Deucher 	uint32_t y_clk_reg;
1119b9fe724SAlex Deucher 	uint32_t y_data_reg;
112771fe6b9SJerome Glisse 	uint32_t mask_clk_mask;
113771fe6b9SJerome Glisse 	uint32_t mask_data_mask;
114771fe6b9SJerome Glisse 	uint32_t a_clk_mask;
115771fe6b9SJerome Glisse 	uint32_t a_data_mask;
1169b9fe724SAlex Deucher 	uint32_t en_clk_mask;
1179b9fe724SAlex Deucher 	uint32_t en_data_mask;
1189b9fe724SAlex Deucher 	uint32_t y_clk_mask;
1199b9fe724SAlex Deucher 	uint32_t y_data_mask;
120771fe6b9SJerome Glisse };
121771fe6b9SJerome Glisse 
122771fe6b9SJerome Glisse struct radeon_tmds_pll {
123771fe6b9SJerome Glisse     uint32_t freq;
124771fe6b9SJerome Glisse     uint32_t value;
125771fe6b9SJerome Glisse };
126771fe6b9SJerome Glisse 
127771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16
128771fe6b9SJerome Glisse 
1297c27f87dSAlex Deucher /* pll flags */
130771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
131771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
132771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV          (1 << 2)
133771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY               (1 << 3)
134771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
135771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
136771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
137771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
138771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
139771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
140771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
141d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
142fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV         (1 << 12)
14386cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD               (1 << 13)
144771fe6b9SJerome Glisse 
1457c27f87dSAlex Deucher /* pll algo */
1467c27f87dSAlex Deucher enum radeon_pll_algo {
1477c27f87dSAlex Deucher 	PLL_ALGO_LEGACY,
148383be5d1SAlex Deucher 	PLL_ALGO_NEW
1497c27f87dSAlex Deucher };
1507c27f87dSAlex Deucher 
151771fe6b9SJerome Glisse struct radeon_pll {
152fc10332bSAlex Deucher 	/* reference frequency */
153fc10332bSAlex Deucher 	uint32_t reference_freq;
154fc10332bSAlex Deucher 
155fc10332bSAlex Deucher 	/* fixed dividers */
156fc10332bSAlex Deucher 	uint32_t reference_div;
157fc10332bSAlex Deucher 	uint32_t post_div;
158fc10332bSAlex Deucher 
159fc10332bSAlex Deucher 	/* pll in/out limits */
160771fe6b9SJerome Glisse 	uint32_t pll_in_min;
161771fe6b9SJerome Glisse 	uint32_t pll_in_max;
162771fe6b9SJerome Glisse 	uint32_t pll_out_min;
163771fe6b9SJerome Glisse 	uint32_t pll_out_max;
16486cb2bbfSAlex Deucher 	uint32_t lcd_pll_out_min;
16586cb2bbfSAlex Deucher 	uint32_t lcd_pll_out_max;
166fc10332bSAlex Deucher 	uint32_t best_vco;
167771fe6b9SJerome Glisse 
168fc10332bSAlex Deucher 	/* divider limits */
169771fe6b9SJerome Glisse 	uint32_t min_ref_div;
170771fe6b9SJerome Glisse 	uint32_t max_ref_div;
171771fe6b9SJerome Glisse 	uint32_t min_post_div;
172771fe6b9SJerome Glisse 	uint32_t max_post_div;
173771fe6b9SJerome Glisse 	uint32_t min_feedback_div;
174771fe6b9SJerome Glisse 	uint32_t max_feedback_div;
175771fe6b9SJerome Glisse 	uint32_t min_frac_feedback_div;
176771fe6b9SJerome Glisse 	uint32_t max_frac_feedback_div;
177fc10332bSAlex Deucher 
178fc10332bSAlex Deucher 	/* flags for the current clock */
179fc10332bSAlex Deucher 	uint32_t flags;
180fc10332bSAlex Deucher 
181fc10332bSAlex Deucher 	/* pll id */
182fc10332bSAlex Deucher 	uint32_t id;
1837c27f87dSAlex Deucher 	/* pll algo */
1847c27f87dSAlex Deucher 	enum radeon_pll_algo algo;
185771fe6b9SJerome Glisse };
186771fe6b9SJerome Glisse 
187771fe6b9SJerome Glisse struct radeon_i2c_chan {
188771fe6b9SJerome Glisse 	struct i2c_adapter adapter;
189746c1aa4SDave Airlie 	struct drm_device *dev;
190746c1aa4SDave Airlie 	union {
191ac1aade6SAlex Deucher 		struct i2c_algo_bit_data bit;
192746c1aa4SDave Airlie 		struct i2c_algo_dp_aux_data dp;
193746c1aa4SDave Airlie 	} algo;
194771fe6b9SJerome Glisse 	struct radeon_i2c_bus_rec rec;
195771fe6b9SJerome Glisse };
196771fe6b9SJerome Glisse 
197771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */
198771fe6b9SJerome Glisse enum radeon_connector_table {
199771fe6b9SJerome Glisse 	CT_NONE,
200771fe6b9SJerome Glisse 	CT_GENERIC,
201771fe6b9SJerome Glisse 	CT_IBOOK,
202771fe6b9SJerome Glisse 	CT_POWERBOOK_EXTERNAL,
203771fe6b9SJerome Glisse 	CT_POWERBOOK_INTERNAL,
204771fe6b9SJerome Glisse 	CT_POWERBOOK_VGA,
205771fe6b9SJerome Glisse 	CT_MINI_EXTERNAL,
206771fe6b9SJerome Glisse 	CT_MINI_INTERNAL,
207771fe6b9SJerome Glisse 	CT_IMAC_G5_ISIGHT,
208771fe6b9SJerome Glisse 	CT_EMAC,
209771fe6b9SJerome Glisse };
210771fe6b9SJerome Glisse 
211fcec570bSAlex Deucher enum radeon_dvo_chip {
212fcec570bSAlex Deucher 	DVO_SIL164,
213fcec570bSAlex Deucher 	DVO_SIL1178,
214fcec570bSAlex Deucher };
215fcec570bSAlex Deucher 
2168be48d92SDave Airlie struct radeon_fbdev;
21738651674SDave Airlie 
218771fe6b9SJerome Glisse struct radeon_mode_info {
219771fe6b9SJerome Glisse 	struct atom_context *atom_context;
22061c4b24bSMathias Fröhlich 	struct card_info *atom_card_info;
221771fe6b9SJerome Glisse 	enum radeon_connector_table connector_table;
222771fe6b9SJerome Glisse 	bool mode_config_initialized;
223bcc1c2a1SAlex Deucher 	struct radeon_crtc *crtcs[6];
224445282dbSDave Airlie 	/* DVI-I properties */
225445282dbSDave Airlie 	struct drm_property *coherent_mode_property;
226445282dbSDave Airlie 	/* DAC enable load detect */
227445282dbSDave Airlie 	struct drm_property *load_detect_property;
228445282dbSDave Airlie 	/* TV standard load detect */
229445282dbSDave Airlie 	struct drm_property *tv_std_property;
230445282dbSDave Airlie 	/* legacy TMDS PLL detect */
231445282dbSDave Airlie 	struct drm_property *tmds_pll_property;
2323c537889SAlex Deucher 	/* hardcoded DFP edid from BIOS */
2333c537889SAlex Deucher 	struct edid *bios_hardcoded_edid;
23438651674SDave Airlie 
23538651674SDave Airlie 	/* pointer to fbdev info structure */
2368be48d92SDave Airlie 	struct radeon_fbdev *rfbdev;
237c93bb85bSJerome Glisse };
238c93bb85bSJerome Glisse 
2394ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32
2404ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32
2414ce001abSDave Airlie 
2424ce001abSDave Airlie /* need to store these as reading
2434ce001abSDave Airlie    back code tables is excessive */
2444ce001abSDave Airlie struct radeon_tv_regs {
2454ce001abSDave Airlie 	uint32_t tv_uv_adr;
2464ce001abSDave Airlie 	uint32_t timing_cntl;
2474ce001abSDave Airlie 	uint32_t hrestart;
2484ce001abSDave Airlie 	uint32_t vrestart;
2494ce001abSDave Airlie 	uint32_t frestart;
2504ce001abSDave Airlie 	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
2514ce001abSDave Airlie 	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
2524ce001abSDave Airlie };
2534ce001abSDave Airlie 
254771fe6b9SJerome Glisse struct radeon_crtc {
255771fe6b9SJerome Glisse 	struct drm_crtc base;
256771fe6b9SJerome Glisse 	int crtc_id;
257771fe6b9SJerome Glisse 	u16 lut_r[256], lut_g[256], lut_b[256];
258771fe6b9SJerome Glisse 	bool enabled;
259771fe6b9SJerome Glisse 	bool can_tile;
260771fe6b9SJerome Glisse 	uint32_t crtc_offset;
261771fe6b9SJerome Glisse 	struct drm_gem_object *cursor_bo;
262771fe6b9SJerome Glisse 	uint64_t cursor_addr;
263771fe6b9SJerome Glisse 	int cursor_width;
264771fe6b9SJerome Glisse 	int cursor_height;
2654162338aSDave Airlie 	uint32_t legacy_display_base_addr;
266c836e862SAlex Deucher 	uint32_t legacy_cursor_offset;
267c93bb85bSJerome Glisse 	enum radeon_rmx_type rmx_type;
268c93bb85bSJerome Glisse 	fixed20_12 vsc;
269c93bb85bSJerome Glisse 	fixed20_12 hsc;
270de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
271bcc1c2a1SAlex Deucher 	int pll_id;
272771fe6b9SJerome Glisse };
273771fe6b9SJerome Glisse 
274771fe6b9SJerome Glisse struct radeon_encoder_primary_dac {
275771fe6b9SJerome Glisse 	/* legacy primary dac */
276771fe6b9SJerome Glisse 	uint32_t ps2_pdac_adj;
277771fe6b9SJerome Glisse };
278771fe6b9SJerome Glisse 
279771fe6b9SJerome Glisse struct radeon_encoder_lvds {
280771fe6b9SJerome Glisse 	/* legacy lvds */
281771fe6b9SJerome Glisse 	uint16_t panel_vcc_delay;
282771fe6b9SJerome Glisse 	uint8_t  panel_pwr_delay;
283771fe6b9SJerome Glisse 	uint8_t  panel_digon_delay;
284771fe6b9SJerome Glisse 	uint8_t  panel_blon_delay;
285771fe6b9SJerome Glisse 	uint16_t panel_ref_divider;
286771fe6b9SJerome Glisse 	uint8_t  panel_post_divider;
287771fe6b9SJerome Glisse 	uint16_t panel_fb_divider;
288771fe6b9SJerome Glisse 	bool     use_bios_dividers;
289771fe6b9SJerome Glisse 	uint32_t lvds_gen_cntl;
290771fe6b9SJerome Glisse 	/* panel mode */
291de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
292771fe6b9SJerome Glisse };
293771fe6b9SJerome Glisse 
294771fe6b9SJerome Glisse struct radeon_encoder_tv_dac {
295771fe6b9SJerome Glisse 	/* legacy tv dac */
296771fe6b9SJerome Glisse 	uint32_t ps2_tvdac_adj;
297771fe6b9SJerome Glisse 	uint32_t ntsc_tvdac_adj;
298771fe6b9SJerome Glisse 	uint32_t pal_tvdac_adj;
299771fe6b9SJerome Glisse 
3004ce001abSDave Airlie 	int               h_pos;
3014ce001abSDave Airlie 	int               v_pos;
3024ce001abSDave Airlie 	int               h_size;
3034ce001abSDave Airlie 	int               supported_tv_stds;
3044ce001abSDave Airlie 	bool              tv_on;
305771fe6b9SJerome Glisse 	enum radeon_tv_std tv_std;
3064ce001abSDave Airlie 	struct radeon_tv_regs tv;
307771fe6b9SJerome Glisse };
308771fe6b9SJerome Glisse 
309771fe6b9SJerome Glisse struct radeon_encoder_int_tmds {
310771fe6b9SJerome Glisse 	/* legacy int tmds */
311771fe6b9SJerome Glisse 	struct radeon_tmds_pll tmds_pll[4];
312771fe6b9SJerome Glisse };
313771fe6b9SJerome Glisse 
314fcec570bSAlex Deucher struct radeon_encoder_ext_tmds {
315fcec570bSAlex Deucher 	/* tmds over dvo */
316fcec570bSAlex Deucher 	struct radeon_i2c_chan *i2c_bus;
317fcec570bSAlex Deucher 	uint8_t slave_addr;
318fcec570bSAlex Deucher 	enum radeon_dvo_chip dvo_chip;
319fcec570bSAlex Deucher };
320fcec570bSAlex Deucher 
321ebbe1cb9SAlex Deucher /* spread spectrum */
322ebbe1cb9SAlex Deucher struct radeon_atom_ss {
323ebbe1cb9SAlex Deucher 	uint16_t percentage;
324ebbe1cb9SAlex Deucher 	uint8_t type;
325ebbe1cb9SAlex Deucher 	uint8_t step;
326ebbe1cb9SAlex Deucher 	uint8_t delay;
327ebbe1cb9SAlex Deucher 	uint8_t range;
328ebbe1cb9SAlex Deucher 	uint8_t refdiv;
329ebbe1cb9SAlex Deucher };
330ebbe1cb9SAlex Deucher 
331771fe6b9SJerome Glisse struct radeon_encoder_atom_dig {
332771fe6b9SJerome Glisse 	/* atom dig */
333771fe6b9SJerome Glisse 	bool coherent_mode;
334f28cf339SDave Airlie 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
335771fe6b9SJerome Glisse 	/* atom lvds */
336771fe6b9SJerome Glisse 	uint32_t lvds_misc;
337771fe6b9SJerome Glisse 	uint16_t panel_pwr_delay;
3387c27f87dSAlex Deucher 	enum radeon_pll_algo pll_algo;
339ebbe1cb9SAlex Deucher 	struct radeon_atom_ss *ss;
340771fe6b9SJerome Glisse 	/* panel mode */
341de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
342771fe6b9SJerome Glisse };
343771fe6b9SJerome Glisse 
3444ce001abSDave Airlie struct radeon_encoder_atom_dac {
3454ce001abSDave Airlie 	enum radeon_tv_std tv_std;
3464ce001abSDave Airlie };
3474ce001abSDave Airlie 
348771fe6b9SJerome Glisse struct radeon_encoder {
349771fe6b9SJerome Glisse 	struct drm_encoder base;
350771fe6b9SJerome Glisse 	uint32_t encoder_id;
351771fe6b9SJerome Glisse 	uint32_t devices;
3524ce001abSDave Airlie 	uint32_t active_device;
353771fe6b9SJerome Glisse 	uint32_t flags;
354771fe6b9SJerome Glisse 	uint32_t pixel_clock;
355771fe6b9SJerome Glisse 	enum radeon_rmx_type rmx_type;
356de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
357771fe6b9SJerome Glisse 	void *enc_priv;
35858bd0863SChristian König 	int audio_polling_active;
359dafc3bd5SChristian Koenig 	int hdmi_offset;
360808032eeSRafał Miłecki 	int hdmi_config_offset;
361dafc3bd5SChristian Koenig 	int hdmi_audio_workaround;
362dafc3bd5SChristian Koenig 	int hdmi_buffer_status;
363771fe6b9SJerome Glisse };
364771fe6b9SJerome Glisse 
365771fe6b9SJerome Glisse struct radeon_connector_atom_dig {
366771fe6b9SJerome Glisse 	uint32_t igp_lane_info;
367771fe6b9SJerome Glisse 	bool linkb;
3684143e919SAlex Deucher 	/* displayport */
369746c1aa4SDave Airlie 	struct radeon_i2c_chan *dp_i2c_bus;
3701a66c95aSAlex Deucher 	u8 dpcd[8];
3714143e919SAlex Deucher 	u8 dp_sink_type;
3725801ead6SAlex Deucher 	int dp_clock;
3735801ead6SAlex Deucher 	int dp_lane_count;
374771fe6b9SJerome Glisse };
375771fe6b9SJerome Glisse 
376eed45b30SAlex Deucher struct radeon_gpio_rec {
377eed45b30SAlex Deucher 	bool valid;
378eed45b30SAlex Deucher 	u8 id;
379eed45b30SAlex Deucher 	u32 reg;
380eed45b30SAlex Deucher 	u32 mask;
381eed45b30SAlex Deucher };
382eed45b30SAlex Deucher 
383eed45b30SAlex Deucher struct radeon_hpd {
384eed45b30SAlex Deucher 	enum radeon_hpd_id hpd;
385eed45b30SAlex Deucher 	u8 plugged_state;
386eed45b30SAlex Deucher 	struct radeon_gpio_rec gpio;
387eed45b30SAlex Deucher };
388eed45b30SAlex Deucher 
389771fe6b9SJerome Glisse struct radeon_connector {
390771fe6b9SJerome Glisse 	struct drm_connector base;
391771fe6b9SJerome Glisse 	uint32_t connector_id;
392771fe6b9SJerome Glisse 	uint32_t devices;
393771fe6b9SJerome Glisse 	struct radeon_i2c_chan *ddc_bus;
3940294cf4fSAlex Deucher 	/* some systems have a an hdmi and vga port with a shared ddc line */
3950294cf4fSAlex Deucher 	bool shared_ddc;
3964ce001abSDave Airlie 	bool use_digital;
3974ce001abSDave Airlie 	/* we need to mind the EDID between detect
3984ce001abSDave Airlie 	   and get modes due to analog/digital/tvencoder */
3994ce001abSDave Airlie 	struct edid *edid;
400771fe6b9SJerome Glisse 	void *con_priv;
401445282dbSDave Airlie 	bool dac_load_detect;
402b75fad06SAlex Deucher 	uint16_t connector_object_id;
403eed45b30SAlex Deucher 	struct radeon_hpd hpd;
404771fe6b9SJerome Glisse };
405771fe6b9SJerome Glisse 
406771fe6b9SJerome Glisse struct radeon_framebuffer {
407771fe6b9SJerome Glisse 	struct drm_framebuffer base;
408771fe6b9SJerome Glisse 	struct drm_gem_object *obj;
409771fe6b9SJerome Glisse };
410771fe6b9SJerome Glisse 
411d79766faSAlex Deucher extern enum radeon_tv_std
412d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev);
413d79766faSAlex Deucher extern enum radeon_tv_std
414d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev);
415d79766faSAlex Deucher 
416d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector);
417d4877cf2SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4185801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
4195801ead6SAlex Deucher 				       struct drm_display_mode *mode);
4205801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector,
4215801ead6SAlex Deucher 				      struct drm_display_mode *mode);
4225801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder,
4235801ead6SAlex Deucher 			  struct drm_connector *connector);
4244143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
4259fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
426bcc1c2a1SAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
4275801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
4285801ead6SAlex Deucher 					   int action, uint8_t lane_num,
4295801ead6SAlex Deucher 					   uint8_t lane_set);
430746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
431746c1aa4SDave Airlie 				uint8_t write_byte, uint8_t *read_byte);
432746c1aa4SDave Airlie 
433746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
4346a93cb25SAlex Deucher 						    struct radeon_i2c_bus_rec *rec,
4356a93cb25SAlex Deucher 						    const char *name);
436771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
437771fe6b9SJerome Glisse 						 struct radeon_i2c_bus_rec *rec,
438771fe6b9SJerome Glisse 						 const char *name);
439771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
4405a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
441fcec570bSAlex Deucher 				u8 slave_addr,
442fcec570bSAlex Deucher 				u8 addr,
443fcec570bSAlex Deucher 				u8 *val);
4445a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
445fcec570bSAlex Deucher 				u8 slave_addr,
446fcec570bSAlex Deucher 				u8 addr,
447fcec570bSAlex Deucher 				u8 val);
448771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
449771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
450771fe6b9SJerome Glisse 
451771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
452771fe6b9SJerome Glisse 
453771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll,
454771fe6b9SJerome Glisse 			       uint64_t freq,
455771fe6b9SJerome Glisse 			       uint32_t *dot_clock_p,
456771fe6b9SJerome Glisse 			       uint32_t *fb_div_p,
457771fe6b9SJerome Glisse 			       uint32_t *frac_fb_div_p,
458771fe6b9SJerome Glisse 			       uint32_t *ref_div_p,
459fc10332bSAlex Deucher 			       uint32_t *post_div_p);
460771fe6b9SJerome Glisse 
4611f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev);
4621f3b6a45SDave Airlie 
463771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
464771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
465771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
466771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
467771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
468771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
46932f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
470771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4714ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
472771fe6b9SJerome Glisse 
473771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
474771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
475771fe6b9SJerome Glisse 				   struct drm_framebuffer *old_fb);
476771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
477771fe6b9SJerome Glisse 				   struct drm_display_mode *mode,
478771fe6b9SJerome Glisse 				   struct drm_display_mode *adjusted_mode,
479771fe6b9SJerome Glisse 				   int x, int y,
480771fe6b9SJerome Glisse 				   struct drm_framebuffer *old_fb);
481771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
482771fe6b9SJerome Glisse 
483771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
484771fe6b9SJerome Glisse 				 struct drm_framebuffer *old_fb);
485771fe6b9SJerome Glisse 
486771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
487771fe6b9SJerome Glisse 				  struct drm_file *file_priv,
488771fe6b9SJerome Glisse 				  uint32_t handle,
489771fe6b9SJerome Glisse 				  uint32_t width,
490771fe6b9SJerome Glisse 				  uint32_t height);
491771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
492771fe6b9SJerome Glisse 				   int x, int y);
493771fe6b9SJerome Glisse 
4943c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
4953c537889SAlex Deucher extern struct edid *
4963c537889SAlex Deucher radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
497771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev);
498771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev);
499771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig *
500771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
501fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
502445282dbSDave Airlie 					  struct radeon_encoder_int_tmds *tmds);
503fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
504445282dbSDave Airlie 						     struct radeon_encoder_int_tmds *tmds);
505fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
506445282dbSDave Airlie 						   struct radeon_encoder_int_tmds *tmds);
507fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
508fcec570bSAlex Deucher 							 struct radeon_encoder_ext_tmds *tmds);
509fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
510fcec570bSAlex Deucher 						       struct radeon_encoder_ext_tmds *tmds);
5116fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac *
5126fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
5136fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac *
5146fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
515771fe6b9SJerome Glisse extern struct radeon_encoder_lvds *
516771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
517771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
518771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac *
519771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
520771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac *
521771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
522fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
523fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
524771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
525771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
526771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
527771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
528f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
529f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
530771fe6b9SJerome Glisse extern void
531771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
532771fe6b9SJerome Glisse extern void
533771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
534771fe6b9SJerome Glisse extern void
535771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
536771fe6b9SJerome Glisse extern void
537771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
538771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
539771fe6b9SJerome Glisse 				     u16 blue, int regno);
540b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
541b8c00ac5SDave Airlie 				     u16 *blue, int regno);
54238651674SDave Airlie void radeon_framebuffer_init(struct drm_device *dev,
54338651674SDave Airlie 			     struct radeon_framebuffer *rfb,
544771fe6b9SJerome Glisse 			     struct drm_mode_fb_cmd *mode_cmd,
545771fe6b9SJerome Glisse 			     struct drm_gem_object *obj);
546771fe6b9SJerome Glisse 
547771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
548771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
549771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
550771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev,
551771fe6b9SJerome Glisse 			       struct radeon_crtc *radeon_crtc);
552771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev,
553771fe6b9SJerome Glisse 			     struct radeon_crtc *radeon_crtc);
554771fe6b9SJerome Glisse 
555771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev);
556771fe6b9SJerome Glisse 
557771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
558771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
559771fe6b9SJerome Glisse 
560771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder);
561771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
562771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev);
563771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev);
564c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
565c93bb85bSJerome Glisse 					struct drm_display_mode *mode,
566c93bb85bSJerome Glisse 					struct drm_display_mode *adjusted_mode);
5673515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder,
5683515387bSAlex Deucher 			     struct drm_display_mode *adjusted_mode);
5694ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
570771fe6b9SJerome Glisse 
5714ce001abSDave Airlie /* legacy tv */
5724ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
5734ce001abSDave Airlie 				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
5744ce001abSDave Airlie 				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
5754ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
5764ce001abSDave Airlie 				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
5774ce001abSDave Airlie 				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
5784ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
5794ce001abSDave Airlie 				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
5804ce001abSDave Airlie 				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
5814ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
5824ce001abSDave Airlie 			       struct drm_display_mode *mode,
5834ce001abSDave Airlie 			       struct drm_display_mode *adjusted_mode);
58438651674SDave Airlie 
58538651674SDave Airlie /* fbdev layer */
58638651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev);
58738651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev);
58838651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
58938651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev);
59038651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
591eb1f8e4fSDave Airlie 
592eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev);
593771fe6b9SJerome Glisse #endif
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