1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36771fe6b9SJerome Glisse #include <linux/i2c.h> 37771fe6b9SJerome Glisse #include <linux/i2c-id.h> 38771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 39771fe6b9SJerome Glisse 40771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 41771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 42771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 43771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 44771fe6b9SJerome Glisse 45771fe6b9SJerome Glisse enum radeon_connector_type { 46771fe6b9SJerome Glisse CONNECTOR_NONE, 47771fe6b9SJerome Glisse CONNECTOR_VGA, 48771fe6b9SJerome Glisse CONNECTOR_DVI_I, 49771fe6b9SJerome Glisse CONNECTOR_DVI_D, 50771fe6b9SJerome Glisse CONNECTOR_DVI_A, 51771fe6b9SJerome Glisse CONNECTOR_STV, 52771fe6b9SJerome Glisse CONNECTOR_CTV, 53771fe6b9SJerome Glisse CONNECTOR_LVDS, 54771fe6b9SJerome Glisse CONNECTOR_DIGITAL, 55771fe6b9SJerome Glisse CONNECTOR_SCART, 56771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_A, 57771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_B, 58771fe6b9SJerome Glisse CONNECTOR_0XC, 59771fe6b9SJerome Glisse CONNECTOR_0XD, 60771fe6b9SJerome Glisse CONNECTOR_DIN, 61771fe6b9SJerome Glisse CONNECTOR_DISPLAY_PORT, 62771fe6b9SJerome Glisse CONNECTOR_UNSUPPORTED 63771fe6b9SJerome Glisse }; 64771fe6b9SJerome Glisse 65771fe6b9SJerome Glisse enum radeon_dvi_type { 66771fe6b9SJerome Glisse DVI_AUTO, 67771fe6b9SJerome Glisse DVI_DIGITAL, 68771fe6b9SJerome Glisse DVI_ANALOG 69771fe6b9SJerome Glisse }; 70771fe6b9SJerome Glisse 71771fe6b9SJerome Glisse enum radeon_rmx_type { 72771fe6b9SJerome Glisse RMX_OFF, 73771fe6b9SJerome Glisse RMX_FULL, 74771fe6b9SJerome Glisse RMX_CENTER, 75771fe6b9SJerome Glisse RMX_ASPECT 76771fe6b9SJerome Glisse }; 77771fe6b9SJerome Glisse 78771fe6b9SJerome Glisse enum radeon_tv_std { 79771fe6b9SJerome Glisse TV_STD_NTSC, 80771fe6b9SJerome Glisse TV_STD_PAL, 81771fe6b9SJerome Glisse TV_STD_PAL_M, 82771fe6b9SJerome Glisse TV_STD_PAL_60, 83771fe6b9SJerome Glisse TV_STD_NTSC_J, 84771fe6b9SJerome Glisse TV_STD_SCART_PAL, 85771fe6b9SJerome Glisse TV_STD_SECAM, 86771fe6b9SJerome Glisse TV_STD_PAL_CN, 87771fe6b9SJerome Glisse }; 88771fe6b9SJerome Glisse 89771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 90771fe6b9SJerome Glisse bool valid; 91771fe6b9SJerome Glisse uint32_t mask_clk_reg; 92771fe6b9SJerome Glisse uint32_t mask_data_reg; 93771fe6b9SJerome Glisse uint32_t a_clk_reg; 94771fe6b9SJerome Glisse uint32_t a_data_reg; 95771fe6b9SJerome Glisse uint32_t put_clk_reg; 96771fe6b9SJerome Glisse uint32_t put_data_reg; 97771fe6b9SJerome Glisse uint32_t get_clk_reg; 98771fe6b9SJerome Glisse uint32_t get_data_reg; 99771fe6b9SJerome Glisse uint32_t mask_clk_mask; 100771fe6b9SJerome Glisse uint32_t mask_data_mask; 101771fe6b9SJerome Glisse uint32_t put_clk_mask; 102771fe6b9SJerome Glisse uint32_t put_data_mask; 103771fe6b9SJerome Glisse uint32_t get_clk_mask; 104771fe6b9SJerome Glisse uint32_t get_data_mask; 105771fe6b9SJerome Glisse uint32_t a_clk_mask; 106771fe6b9SJerome Glisse uint32_t a_data_mask; 107771fe6b9SJerome Glisse }; 108771fe6b9SJerome Glisse 109771fe6b9SJerome Glisse struct radeon_tmds_pll { 110771fe6b9SJerome Glisse uint32_t freq; 111771fe6b9SJerome Glisse uint32_t value; 112771fe6b9SJerome Glisse }; 113771fe6b9SJerome Glisse 114771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 115771fe6b9SJerome Glisse 116771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 117771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 118771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 119771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 120771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 121771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 122771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 123771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 124771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 125771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 126771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 127771fe6b9SJerome Glisse 128771fe6b9SJerome Glisse struct radeon_pll { 129771fe6b9SJerome Glisse uint16_t reference_freq; 130771fe6b9SJerome Glisse uint16_t reference_div; 131771fe6b9SJerome Glisse uint32_t pll_in_min; 132771fe6b9SJerome Glisse uint32_t pll_in_max; 133771fe6b9SJerome Glisse uint32_t pll_out_min; 134771fe6b9SJerome Glisse uint32_t pll_out_max; 135771fe6b9SJerome Glisse uint16_t xclk; 136771fe6b9SJerome Glisse 137771fe6b9SJerome Glisse uint32_t min_ref_div; 138771fe6b9SJerome Glisse uint32_t max_ref_div; 139771fe6b9SJerome Glisse uint32_t min_post_div; 140771fe6b9SJerome Glisse uint32_t max_post_div; 141771fe6b9SJerome Glisse uint32_t min_feedback_div; 142771fe6b9SJerome Glisse uint32_t max_feedback_div; 143771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 144771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 145771fe6b9SJerome Glisse uint32_t best_vco; 146771fe6b9SJerome Glisse }; 147771fe6b9SJerome Glisse 148771fe6b9SJerome Glisse struct radeon_i2c_chan { 149771fe6b9SJerome Glisse struct drm_device *dev; 150771fe6b9SJerome Glisse struct i2c_adapter adapter; 151771fe6b9SJerome Glisse struct i2c_algo_bit_data algo; 152771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 153771fe6b9SJerome Glisse }; 154771fe6b9SJerome Glisse 155771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 156771fe6b9SJerome Glisse enum radeon_connector_table { 157771fe6b9SJerome Glisse CT_NONE, 158771fe6b9SJerome Glisse CT_GENERIC, 159771fe6b9SJerome Glisse CT_IBOOK, 160771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 161771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 162771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 163771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 164771fe6b9SJerome Glisse CT_MINI_INTERNAL, 165771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 166771fe6b9SJerome Glisse CT_EMAC, 167771fe6b9SJerome Glisse }; 168771fe6b9SJerome Glisse 169771fe6b9SJerome Glisse struct radeon_mode_info { 170771fe6b9SJerome Glisse struct atom_context *atom_context; 171771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 172771fe6b9SJerome Glisse bool mode_config_initialized; 173771fe6b9SJerome Glisse }; 174771fe6b9SJerome Glisse 175771fe6b9SJerome Glisse struct radeon_crtc { 176771fe6b9SJerome Glisse struct drm_crtc base; 177771fe6b9SJerome Glisse int crtc_id; 178771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 179771fe6b9SJerome Glisse bool enabled; 180771fe6b9SJerome Glisse bool can_tile; 181771fe6b9SJerome Glisse uint32_t crtc_offset; 182771fe6b9SJerome Glisse struct radeon_framebuffer *fbdev_fb; 183771fe6b9SJerome Glisse struct drm_mode_set mode_set; 184771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 185771fe6b9SJerome Glisse uint64_t cursor_addr; 186771fe6b9SJerome Glisse int cursor_width; 187771fe6b9SJerome Glisse int cursor_height; 188771fe6b9SJerome Glisse }; 189771fe6b9SJerome Glisse 190771fe6b9SJerome Glisse #define RADEON_USE_RMX 1 191771fe6b9SJerome Glisse 192771fe6b9SJerome Glisse struct radeon_native_mode { 193771fe6b9SJerome Glisse /* preferred mode */ 194771fe6b9SJerome Glisse uint32_t panel_xres, panel_yres; 195771fe6b9SJerome Glisse uint32_t hoverplus, hsync_width; 196771fe6b9SJerome Glisse uint32_t hblank; 197771fe6b9SJerome Glisse uint32_t voverplus, vsync_width; 198771fe6b9SJerome Glisse uint32_t vblank; 199771fe6b9SJerome Glisse uint32_t dotclock; 200771fe6b9SJerome Glisse uint32_t flags; 201771fe6b9SJerome Glisse }; 202771fe6b9SJerome Glisse 203771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 204771fe6b9SJerome Glisse /* legacy primary dac */ 205771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 206771fe6b9SJerome Glisse }; 207771fe6b9SJerome Glisse 208771fe6b9SJerome Glisse struct radeon_encoder_lvds { 209771fe6b9SJerome Glisse /* legacy lvds */ 210771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 211771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 212771fe6b9SJerome Glisse uint8_t panel_digon_delay; 213771fe6b9SJerome Glisse uint8_t panel_blon_delay; 214771fe6b9SJerome Glisse uint16_t panel_ref_divider; 215771fe6b9SJerome Glisse uint8_t panel_post_divider; 216771fe6b9SJerome Glisse uint16_t panel_fb_divider; 217771fe6b9SJerome Glisse bool use_bios_dividers; 218771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 219771fe6b9SJerome Glisse /* panel mode */ 220771fe6b9SJerome Glisse struct radeon_native_mode native_mode; 221771fe6b9SJerome Glisse }; 222771fe6b9SJerome Glisse 223771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 224771fe6b9SJerome Glisse /* legacy tv dac */ 225771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 226771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 227771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 228771fe6b9SJerome Glisse 229771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 230771fe6b9SJerome Glisse }; 231771fe6b9SJerome Glisse 232771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 233771fe6b9SJerome Glisse /* legacy int tmds */ 234771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 235771fe6b9SJerome Glisse }; 236771fe6b9SJerome Glisse 237771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 238771fe6b9SJerome Glisse /* atom dig */ 239771fe6b9SJerome Glisse bool coherent_mode; 240771fe6b9SJerome Glisse int dig_block; 241771fe6b9SJerome Glisse /* atom lvds */ 242771fe6b9SJerome Glisse uint32_t lvds_misc; 243771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 244771fe6b9SJerome Glisse /* panel mode */ 245771fe6b9SJerome Glisse struct radeon_native_mode native_mode; 246771fe6b9SJerome Glisse }; 247771fe6b9SJerome Glisse 248771fe6b9SJerome Glisse struct radeon_encoder { 249771fe6b9SJerome Glisse struct drm_encoder base; 250771fe6b9SJerome Glisse uint32_t encoder_id; 251771fe6b9SJerome Glisse uint32_t devices; 252771fe6b9SJerome Glisse uint32_t flags; 253771fe6b9SJerome Glisse uint32_t pixel_clock; 254771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 255771fe6b9SJerome Glisse struct radeon_native_mode native_mode; 256771fe6b9SJerome Glisse void *enc_priv; 257771fe6b9SJerome Glisse }; 258771fe6b9SJerome Glisse 259771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 260771fe6b9SJerome Glisse uint32_t igp_lane_info; 261771fe6b9SJerome Glisse bool linkb; 262771fe6b9SJerome Glisse }; 263771fe6b9SJerome Glisse 264771fe6b9SJerome Glisse struct radeon_connector { 265771fe6b9SJerome Glisse struct drm_connector base; 266771fe6b9SJerome Glisse uint32_t connector_id; 267771fe6b9SJerome Glisse uint32_t devices; 268771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 269771fe6b9SJerome Glisse int use_digital; 270771fe6b9SJerome Glisse void *con_priv; 271771fe6b9SJerome Glisse }; 272771fe6b9SJerome Glisse 273771fe6b9SJerome Glisse struct radeon_framebuffer { 274771fe6b9SJerome Glisse struct drm_framebuffer base; 275771fe6b9SJerome Glisse struct drm_gem_object *obj; 276771fe6b9SJerome Glisse }; 277771fe6b9SJerome Glisse 278771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 279771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 280771fe6b9SJerome Glisse const char *name); 281771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 282771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 283771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 284771fe6b9SJerome Glisse 285771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 286771fe6b9SJerome Glisse 287771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 288771fe6b9SJerome Glisse uint64_t freq, 289771fe6b9SJerome Glisse uint32_t *dot_clock_p, 290771fe6b9SJerome Glisse uint32_t *fb_div_p, 291771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 292771fe6b9SJerome Glisse uint32_t *ref_div_p, 293771fe6b9SJerome Glisse uint32_t *post_div_p, 294771fe6b9SJerome Glisse int flags); 295771fe6b9SJerome Glisse 296771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 297771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 298771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 299771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 300771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 301771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 302771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 303771fe6b9SJerome Glisse 304771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 305771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 306771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 307771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 308771fe6b9SJerome Glisse struct drm_display_mode *mode, 309771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 310771fe6b9SJerome Glisse int x, int y, 311771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 312771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 313771fe6b9SJerome Glisse 314771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 315771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 316771fe6b9SJerome Glisse extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); 317771fe6b9SJerome Glisse 318771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 319771fe6b9SJerome Glisse struct drm_file *file_priv, 320771fe6b9SJerome Glisse uint32_t handle, 321771fe6b9SJerome Glisse uint32_t width, 322771fe6b9SJerome Glisse uint32_t height); 323771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 324771fe6b9SJerome Glisse int x, int y); 325771fe6b9SJerome Glisse 326771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 327771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 328771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 329771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 330771fe6b9SJerome Glisse extern struct radeon_encoder_int_tmds * 331771fe6b9SJerome Glisse radeon_atombios_get_tmds_info(struct radeon_encoder *encoder); 3326fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 3336fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 3346fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 3356fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 336771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 337771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 338771fe6b9SJerome Glisse extern struct radeon_encoder_int_tmds * 339771fe6b9SJerome Glisse radeon_combios_get_tmds_info(struct radeon_encoder *encoder); 340771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 341771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 342771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 343771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 344771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 345771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 346771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 347771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 348771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 349771fe6b9SJerome Glisse extern void 350771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 351771fe6b9SJerome Glisse extern void 352771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 353771fe6b9SJerome Glisse extern void 354771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 355771fe6b9SJerome Glisse extern void 356771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 357771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 358771fe6b9SJerome Glisse u16 blue, int regno); 359771fe6b9SJerome Glisse struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, 360771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 361771fe6b9SJerome Glisse struct drm_gem_object *obj); 362771fe6b9SJerome Glisse 363771fe6b9SJerome Glisse int radeonfb_probe(struct drm_device *dev); 364771fe6b9SJerome Glisse 365771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 366771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 367771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 368771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 369771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 370771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 371771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 372771fe6b9SJerome Glisse void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state); 373771fe6b9SJerome Glisse 374771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 375771fe6b9SJerome Glisse 376771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 377771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 378771fe6b9SJerome Glisse 379771fe6b9SJerome Glisse void radeon_rmx_mode_fixup(struct drm_encoder *encoder, 380771fe6b9SJerome Glisse struct drm_display_mode *mode, 381771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode); 382771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 383771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 384771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 385771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev); 386771fe6b9SJerome Glisse void radeon_init_disp_bw_legacy(struct drm_device *dev, 387771fe6b9SJerome Glisse struct drm_display_mode *mode1, 388771fe6b9SJerome Glisse uint32_t pixel_bytes1, 389771fe6b9SJerome Glisse struct drm_display_mode *mode2, 390771fe6b9SJerome Glisse uint32_t pixel_bytes2); 391771fe6b9SJerome Glisse void radeon_init_disp_bw_avivo(struct drm_device *dev, 392771fe6b9SJerome Glisse struct drm_display_mode *mode1, 393771fe6b9SJerome Glisse uint32_t pixel_bytes1, 394771fe6b9SJerome Glisse struct drm_display_mode *mode2, 395771fe6b9SJerome Glisse uint32_t pixel_bytes2); 396771fe6b9SJerome Glisse void radeon_init_disp_bandwidth(struct drm_device *dev); 397771fe6b9SJerome Glisse 398771fe6b9SJerome Glisse #endif 399