1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3771fe6b9SJerome Glisse  *                VA Linux Systems Inc., Fremont, California.
4771fe6b9SJerome Glisse  * Copyright 2008 Red Hat Inc.
5771fe6b9SJerome Glisse  *
6771fe6b9SJerome Glisse  * Permission is hereby granted, free of charge, to any person obtaining a
7771fe6b9SJerome Glisse  * copy of this software and associated documentation files (the "Software"),
8771fe6b9SJerome Glisse  * to deal in the Software without restriction, including without limitation
9771fe6b9SJerome Glisse  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10771fe6b9SJerome Glisse  * and/or sell copies of the Software, and to permit persons to whom the
11771fe6b9SJerome Glisse  * Software is furnished to do so, subject to the following conditions:
12771fe6b9SJerome Glisse  *
13771fe6b9SJerome Glisse  * The above copyright notice and this permission notice shall be included in
14771fe6b9SJerome Glisse  * all copies or substantial portions of the Software.
15771fe6b9SJerome Glisse  *
16771fe6b9SJerome Glisse  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17771fe6b9SJerome Glisse  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18771fe6b9SJerome Glisse  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19771fe6b9SJerome Glisse  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20771fe6b9SJerome Glisse  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21771fe6b9SJerome Glisse  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22771fe6b9SJerome Glisse  * OTHER DEALINGS IN THE SOFTWARE.
23771fe6b9SJerome Glisse  *
24771fe6b9SJerome Glisse  * Original Authors:
25771fe6b9SJerome Glisse  *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26771fe6b9SJerome Glisse  *
27771fe6b9SJerome Glisse  * Kernel port Author: Dave Airlie
28771fe6b9SJerome Glisse  */
29771fe6b9SJerome Glisse 
30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H
31771fe6b9SJerome Glisse #define RADEON_MODE_H
32771fe6b9SJerome Glisse 
33771fe6b9SJerome Glisse #include <drm_crtc.h>
34771fe6b9SJerome Glisse #include <drm_mode.h>
35771fe6b9SJerome Glisse #include <drm_edid.h>
36746c1aa4SDave Airlie #include <drm_dp_helper.h>
3768adac5eSBen Skeggs #include <drm_fixed.h>
38771fe6b9SJerome Glisse #include <linux/i2c.h>
39771fe6b9SJerome Glisse #include <linux/i2c-id.h>
40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h>
41c93bb85bSJerome Glisse 
4238651674SDave Airlie struct radeon_bo;
43c93bb85bSJerome Glisse struct radeon_device;
44771fe6b9SJerome Glisse 
45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49771fe6b9SJerome Glisse 
50771fe6b9SJerome Glisse enum radeon_rmx_type {
51771fe6b9SJerome Glisse 	RMX_OFF,
52771fe6b9SJerome Glisse 	RMX_FULL,
53771fe6b9SJerome Glisse 	RMX_CENTER,
54771fe6b9SJerome Glisse 	RMX_ASPECT
55771fe6b9SJerome Glisse };
56771fe6b9SJerome Glisse 
57771fe6b9SJerome Glisse enum radeon_tv_std {
58771fe6b9SJerome Glisse 	TV_STD_NTSC,
59771fe6b9SJerome Glisse 	TV_STD_PAL,
60771fe6b9SJerome Glisse 	TV_STD_PAL_M,
61771fe6b9SJerome Glisse 	TV_STD_PAL_60,
62771fe6b9SJerome Glisse 	TV_STD_NTSC_J,
63771fe6b9SJerome Glisse 	TV_STD_SCART_PAL,
64771fe6b9SJerome Glisse 	TV_STD_SECAM,
65771fe6b9SJerome Glisse 	TV_STD_PAL_CN,
66d79766faSAlex Deucher 	TV_STD_PAL_N,
67771fe6b9SJerome Glisse };
68771fe6b9SJerome Glisse 
695b1714d3SAlex Deucher enum radeon_underscan_type {
705b1714d3SAlex Deucher 	UNDERSCAN_OFF,
715b1714d3SAlex Deucher 	UNDERSCAN_ON,
725b1714d3SAlex Deucher 	UNDERSCAN_AUTO,
735b1714d3SAlex Deucher };
745b1714d3SAlex Deucher 
758e36ed00SAlex Deucher enum radeon_hpd_id {
768e36ed00SAlex Deucher 	RADEON_HPD_1 = 0,
778e36ed00SAlex Deucher 	RADEON_HPD_2,
788e36ed00SAlex Deucher 	RADEON_HPD_3,
798e36ed00SAlex Deucher 	RADEON_HPD_4,
808e36ed00SAlex Deucher 	RADEON_HPD_5,
818e36ed00SAlex Deucher 	RADEON_HPD_6,
828e36ed00SAlex Deucher 	RADEON_HPD_NONE = 0xff,
838e36ed00SAlex Deucher };
848e36ed00SAlex Deucher 
85f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16
86f376b94fSAlex Deucher 
879b9fe724SAlex Deucher /* radeon gpio-based i2c
889b9fe724SAlex Deucher  * 1. "mask" reg and bits
899b9fe724SAlex Deucher  *    grabs the gpio pins for software use
909b9fe724SAlex Deucher  *    0=not held  1=held
919b9fe724SAlex Deucher  * 2. "a" reg and bits
929b9fe724SAlex Deucher  *    output pin value
939b9fe724SAlex Deucher  *    0=low 1=high
949b9fe724SAlex Deucher  * 3. "en" reg and bits
959b9fe724SAlex Deucher  *    sets the pin direction
969b9fe724SAlex Deucher  *    0=input 1=output
979b9fe724SAlex Deucher  * 4. "y" reg and bits
989b9fe724SAlex Deucher  *    input pin value
999b9fe724SAlex Deucher  *    0=low 1=high
1009b9fe724SAlex Deucher  */
101771fe6b9SJerome Glisse struct radeon_i2c_bus_rec {
102771fe6b9SJerome Glisse 	bool valid;
1036a93cb25SAlex Deucher 	/* id used by atom */
1046a93cb25SAlex Deucher 	uint8_t i2c_id;
105bcc1c2a1SAlex Deucher 	/* id used by atom */
1068e36ed00SAlex Deucher 	enum radeon_hpd_id hpd;
1076a93cb25SAlex Deucher 	/* can be used with hw i2c engine */
1086a93cb25SAlex Deucher 	bool hw_capable;
1096a93cb25SAlex Deucher 	/* uses multi-media i2c engine */
1106a93cb25SAlex Deucher 	bool mm_i2c;
1116a93cb25SAlex Deucher 	/* regs and bits */
112771fe6b9SJerome Glisse 	uint32_t mask_clk_reg;
113771fe6b9SJerome Glisse 	uint32_t mask_data_reg;
114771fe6b9SJerome Glisse 	uint32_t a_clk_reg;
115771fe6b9SJerome Glisse 	uint32_t a_data_reg;
1169b9fe724SAlex Deucher 	uint32_t en_clk_reg;
1179b9fe724SAlex Deucher 	uint32_t en_data_reg;
1189b9fe724SAlex Deucher 	uint32_t y_clk_reg;
1199b9fe724SAlex Deucher 	uint32_t y_data_reg;
120771fe6b9SJerome Glisse 	uint32_t mask_clk_mask;
121771fe6b9SJerome Glisse 	uint32_t mask_data_mask;
122771fe6b9SJerome Glisse 	uint32_t a_clk_mask;
123771fe6b9SJerome Glisse 	uint32_t a_data_mask;
1249b9fe724SAlex Deucher 	uint32_t en_clk_mask;
1259b9fe724SAlex Deucher 	uint32_t en_data_mask;
1269b9fe724SAlex Deucher 	uint32_t y_clk_mask;
1279b9fe724SAlex Deucher 	uint32_t y_data_mask;
128771fe6b9SJerome Glisse };
129771fe6b9SJerome Glisse 
130771fe6b9SJerome Glisse struct radeon_tmds_pll {
131771fe6b9SJerome Glisse     uint32_t freq;
132771fe6b9SJerome Glisse     uint32_t value;
133771fe6b9SJerome Glisse };
134771fe6b9SJerome Glisse 
135771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16
136771fe6b9SJerome Glisse 
1377c27f87dSAlex Deucher /* pll flags */
138771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
139771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
140771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV          (1 << 2)
141771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY               (1 << 3)
142f28488c2SAlex Deucher #define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 4)
143f28488c2SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 5)
144f28488c2SAlex Deucher #define RADEON_PLL_USE_POST_DIV         (1 << 6)
145f28488c2SAlex Deucher #define RADEON_PLL_IS_LCD               (1 << 7)
146771fe6b9SJerome Glisse 
147771fe6b9SJerome Glisse struct radeon_pll {
148fc10332bSAlex Deucher 	/* reference frequency */
149fc10332bSAlex Deucher 	uint32_t reference_freq;
150fc10332bSAlex Deucher 
151fc10332bSAlex Deucher 	/* fixed dividers */
152fc10332bSAlex Deucher 	uint32_t reference_div;
153fc10332bSAlex Deucher 	uint32_t post_div;
154fc10332bSAlex Deucher 
155fc10332bSAlex Deucher 	/* pll in/out limits */
156771fe6b9SJerome Glisse 	uint32_t pll_in_min;
157771fe6b9SJerome Glisse 	uint32_t pll_in_max;
158771fe6b9SJerome Glisse 	uint32_t pll_out_min;
159771fe6b9SJerome Glisse 	uint32_t pll_out_max;
16086cb2bbfSAlex Deucher 	uint32_t lcd_pll_out_min;
16186cb2bbfSAlex Deucher 	uint32_t lcd_pll_out_max;
162fc10332bSAlex Deucher 	uint32_t best_vco;
163771fe6b9SJerome Glisse 
164fc10332bSAlex Deucher 	/* divider limits */
165771fe6b9SJerome Glisse 	uint32_t min_ref_div;
166771fe6b9SJerome Glisse 	uint32_t max_ref_div;
167771fe6b9SJerome Glisse 	uint32_t min_post_div;
168771fe6b9SJerome Glisse 	uint32_t max_post_div;
169771fe6b9SJerome Glisse 	uint32_t min_feedback_div;
170771fe6b9SJerome Glisse 	uint32_t max_feedback_div;
171771fe6b9SJerome Glisse 	uint32_t min_frac_feedback_div;
172771fe6b9SJerome Glisse 	uint32_t max_frac_feedback_div;
173fc10332bSAlex Deucher 
174fc10332bSAlex Deucher 	/* flags for the current clock */
175fc10332bSAlex Deucher 	uint32_t flags;
176fc10332bSAlex Deucher 
177fc10332bSAlex Deucher 	/* pll id */
178fc10332bSAlex Deucher 	uint32_t id;
179771fe6b9SJerome Glisse };
180771fe6b9SJerome Glisse 
181771fe6b9SJerome Glisse struct radeon_i2c_chan {
182771fe6b9SJerome Glisse 	struct i2c_adapter adapter;
183746c1aa4SDave Airlie 	struct drm_device *dev;
184746c1aa4SDave Airlie 	union {
185ac1aade6SAlex Deucher 		struct i2c_algo_bit_data bit;
186746c1aa4SDave Airlie 		struct i2c_algo_dp_aux_data dp;
187746c1aa4SDave Airlie 	} algo;
188771fe6b9SJerome Glisse 	struct radeon_i2c_bus_rec rec;
189771fe6b9SJerome Glisse };
190771fe6b9SJerome Glisse 
191771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */
192771fe6b9SJerome Glisse enum radeon_connector_table {
193aa74fbb4SAlex Deucher 	CT_NONE = 0,
194771fe6b9SJerome Glisse 	CT_GENERIC,
195771fe6b9SJerome Glisse 	CT_IBOOK,
196771fe6b9SJerome Glisse 	CT_POWERBOOK_EXTERNAL,
197771fe6b9SJerome Glisse 	CT_POWERBOOK_INTERNAL,
198771fe6b9SJerome Glisse 	CT_POWERBOOK_VGA,
199771fe6b9SJerome Glisse 	CT_MINI_EXTERNAL,
200771fe6b9SJerome Glisse 	CT_MINI_INTERNAL,
201771fe6b9SJerome Glisse 	CT_IMAC_G5_ISIGHT,
202771fe6b9SJerome Glisse 	CT_EMAC,
20376a7142aSDave Airlie 	CT_RN50_POWER,
204aa74fbb4SAlex Deucher 	CT_MAC_X800,
205771fe6b9SJerome Glisse };
206771fe6b9SJerome Glisse 
207fcec570bSAlex Deucher enum radeon_dvo_chip {
208fcec570bSAlex Deucher 	DVO_SIL164,
209fcec570bSAlex Deucher 	DVO_SIL1178,
210fcec570bSAlex Deucher };
211fcec570bSAlex Deucher 
2128be48d92SDave Airlie struct radeon_fbdev;
21338651674SDave Airlie 
214771fe6b9SJerome Glisse struct radeon_mode_info {
215771fe6b9SJerome Glisse 	struct atom_context *atom_context;
21661c4b24bSMathias Fröhlich 	struct card_info *atom_card_info;
217771fe6b9SJerome Glisse 	enum radeon_connector_table connector_table;
218771fe6b9SJerome Glisse 	bool mode_config_initialized;
219bcc1c2a1SAlex Deucher 	struct radeon_crtc *crtcs[6];
220445282dbSDave Airlie 	/* DVI-I properties */
221445282dbSDave Airlie 	struct drm_property *coherent_mode_property;
222445282dbSDave Airlie 	/* DAC enable load detect */
223445282dbSDave Airlie 	struct drm_property *load_detect_property;
2245b1714d3SAlex Deucher 	/* TV standard */
225445282dbSDave Airlie 	struct drm_property *tv_std_property;
226445282dbSDave Airlie 	/* legacy TMDS PLL detect */
227445282dbSDave Airlie 	struct drm_property *tmds_pll_property;
2285b1714d3SAlex Deucher 	/* underscan */
2295b1714d3SAlex Deucher 	struct drm_property *underscan_property;
2305bccf5e3SMarius Gröger 	struct drm_property *underscan_hborder_property;
2315bccf5e3SMarius Gröger 	struct drm_property *underscan_vborder_property;
2323c537889SAlex Deucher 	/* hardcoded DFP edid from BIOS */
2333c537889SAlex Deucher 	struct edid *bios_hardcoded_edid;
23438651674SDave Airlie 
23538651674SDave Airlie 	/* pointer to fbdev info structure */
2368be48d92SDave Airlie 	struct radeon_fbdev *rfbdev;
237c93bb85bSJerome Glisse };
238c93bb85bSJerome Glisse 
2394ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32
2404ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32
2414ce001abSDave Airlie 
2424ce001abSDave Airlie /* need to store these as reading
2434ce001abSDave Airlie    back code tables is excessive */
2444ce001abSDave Airlie struct radeon_tv_regs {
2454ce001abSDave Airlie 	uint32_t tv_uv_adr;
2464ce001abSDave Airlie 	uint32_t timing_cntl;
2474ce001abSDave Airlie 	uint32_t hrestart;
2484ce001abSDave Airlie 	uint32_t vrestart;
2494ce001abSDave Airlie 	uint32_t frestart;
2504ce001abSDave Airlie 	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
2514ce001abSDave Airlie 	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
2524ce001abSDave Airlie };
2534ce001abSDave Airlie 
254771fe6b9SJerome Glisse struct radeon_crtc {
255771fe6b9SJerome Glisse 	struct drm_crtc base;
256771fe6b9SJerome Glisse 	int crtc_id;
257771fe6b9SJerome Glisse 	u16 lut_r[256], lut_g[256], lut_b[256];
258771fe6b9SJerome Glisse 	bool enabled;
259771fe6b9SJerome Glisse 	bool can_tile;
260771fe6b9SJerome Glisse 	uint32_t crtc_offset;
261771fe6b9SJerome Glisse 	struct drm_gem_object *cursor_bo;
262771fe6b9SJerome Glisse 	uint64_t cursor_addr;
263771fe6b9SJerome Glisse 	int cursor_width;
264771fe6b9SJerome Glisse 	int cursor_height;
2654162338aSDave Airlie 	uint32_t legacy_display_base_addr;
266c836e862SAlex Deucher 	uint32_t legacy_cursor_offset;
267c93bb85bSJerome Glisse 	enum radeon_rmx_type rmx_type;
2685b1714d3SAlex Deucher 	u8 h_border;
2695b1714d3SAlex Deucher 	u8 v_border;
270c93bb85bSJerome Glisse 	fixed20_12 vsc;
271c93bb85bSJerome Glisse 	fixed20_12 hsc;
272de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
273bcc1c2a1SAlex Deucher 	int pll_id;
274771fe6b9SJerome Glisse };
275771fe6b9SJerome Glisse 
276771fe6b9SJerome Glisse struct radeon_encoder_primary_dac {
277771fe6b9SJerome Glisse 	/* legacy primary dac */
278771fe6b9SJerome Glisse 	uint32_t ps2_pdac_adj;
279771fe6b9SJerome Glisse };
280771fe6b9SJerome Glisse 
281771fe6b9SJerome Glisse struct radeon_encoder_lvds {
282771fe6b9SJerome Glisse 	/* legacy lvds */
283771fe6b9SJerome Glisse 	uint16_t panel_vcc_delay;
284771fe6b9SJerome Glisse 	uint8_t  panel_pwr_delay;
285771fe6b9SJerome Glisse 	uint8_t  panel_digon_delay;
286771fe6b9SJerome Glisse 	uint8_t  panel_blon_delay;
287771fe6b9SJerome Glisse 	uint16_t panel_ref_divider;
288771fe6b9SJerome Glisse 	uint8_t  panel_post_divider;
289771fe6b9SJerome Glisse 	uint16_t panel_fb_divider;
290771fe6b9SJerome Glisse 	bool     use_bios_dividers;
291771fe6b9SJerome Glisse 	uint32_t lvds_gen_cntl;
292771fe6b9SJerome Glisse 	/* panel mode */
293de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
294771fe6b9SJerome Glisse };
295771fe6b9SJerome Glisse 
296771fe6b9SJerome Glisse struct radeon_encoder_tv_dac {
297771fe6b9SJerome Glisse 	/* legacy tv dac */
298771fe6b9SJerome Glisse 	uint32_t ps2_tvdac_adj;
299771fe6b9SJerome Glisse 	uint32_t ntsc_tvdac_adj;
300771fe6b9SJerome Glisse 	uint32_t pal_tvdac_adj;
301771fe6b9SJerome Glisse 
3024ce001abSDave Airlie 	int               h_pos;
3034ce001abSDave Airlie 	int               v_pos;
3044ce001abSDave Airlie 	int               h_size;
3054ce001abSDave Airlie 	int               supported_tv_stds;
3064ce001abSDave Airlie 	bool              tv_on;
307771fe6b9SJerome Glisse 	enum radeon_tv_std tv_std;
3084ce001abSDave Airlie 	struct radeon_tv_regs tv;
309771fe6b9SJerome Glisse };
310771fe6b9SJerome Glisse 
311771fe6b9SJerome Glisse struct radeon_encoder_int_tmds {
312771fe6b9SJerome Glisse 	/* legacy int tmds */
313771fe6b9SJerome Glisse 	struct radeon_tmds_pll tmds_pll[4];
314771fe6b9SJerome Glisse };
315771fe6b9SJerome Glisse 
316fcec570bSAlex Deucher struct radeon_encoder_ext_tmds {
317fcec570bSAlex Deucher 	/* tmds over dvo */
318fcec570bSAlex Deucher 	struct radeon_i2c_chan *i2c_bus;
319fcec570bSAlex Deucher 	uint8_t slave_addr;
320fcec570bSAlex Deucher 	enum radeon_dvo_chip dvo_chip;
321fcec570bSAlex Deucher };
322fcec570bSAlex Deucher 
323ebbe1cb9SAlex Deucher /* spread spectrum */
324ebbe1cb9SAlex Deucher struct radeon_atom_ss {
325ebbe1cb9SAlex Deucher 	uint16_t percentage;
326ebbe1cb9SAlex Deucher 	uint8_t type;
327ba032a58SAlex Deucher 	uint16_t step;
328ebbe1cb9SAlex Deucher 	uint8_t delay;
329ebbe1cb9SAlex Deucher 	uint8_t range;
330ebbe1cb9SAlex Deucher 	uint8_t refdiv;
331ba032a58SAlex Deucher 	/* asic_ss */
332ba032a58SAlex Deucher 	uint16_t rate;
333ba032a58SAlex Deucher 	uint16_t amount;
334ebbe1cb9SAlex Deucher };
335ebbe1cb9SAlex Deucher 
336771fe6b9SJerome Glisse struct radeon_encoder_atom_dig {
3375137ee94SAlex Deucher 	bool linkb;
338771fe6b9SJerome Glisse 	/* atom dig */
339771fe6b9SJerome Glisse 	bool coherent_mode;
340ba032a58SAlex Deucher 	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
341ba032a58SAlex Deucher 	/* atom lvds/edp */
342ba032a58SAlex Deucher 	uint32_t lcd_misc;
343771fe6b9SJerome Glisse 	uint16_t panel_pwr_delay;
344ba032a58SAlex Deucher 	uint32_t lcd_ss_id;
345771fe6b9SJerome Glisse 	/* panel mode */
346de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
347771fe6b9SJerome Glisse };
348771fe6b9SJerome Glisse 
3494ce001abSDave Airlie struct radeon_encoder_atom_dac {
3504ce001abSDave Airlie 	enum radeon_tv_std tv_std;
3514ce001abSDave Airlie };
3524ce001abSDave Airlie 
353771fe6b9SJerome Glisse struct radeon_encoder {
354771fe6b9SJerome Glisse 	struct drm_encoder base;
3555137ee94SAlex Deucher 	uint32_t encoder_enum;
356771fe6b9SJerome Glisse 	uint32_t encoder_id;
357771fe6b9SJerome Glisse 	uint32_t devices;
3584ce001abSDave Airlie 	uint32_t active_device;
359771fe6b9SJerome Glisse 	uint32_t flags;
360771fe6b9SJerome Glisse 	uint32_t pixel_clock;
361771fe6b9SJerome Glisse 	enum radeon_rmx_type rmx_type;
3625b1714d3SAlex Deucher 	enum radeon_underscan_type underscan_type;
3635bccf5e3SMarius Gröger 	uint32_t underscan_hborder;
3645bccf5e3SMarius Gröger 	uint32_t underscan_vborder;
365de2103e4SAlex Deucher 	struct drm_display_mode native_mode;
366771fe6b9SJerome Glisse 	void *enc_priv;
36758bd0863SChristian König 	int audio_polling_active;
368dafc3bd5SChristian Koenig 	int hdmi_offset;
369808032eeSRafał Miłecki 	int hdmi_config_offset;
370dafc3bd5SChristian Koenig 	int hdmi_audio_workaround;
371dafc3bd5SChristian Koenig 	int hdmi_buffer_status;
372771fe6b9SJerome Glisse };
373771fe6b9SJerome Glisse 
374771fe6b9SJerome Glisse struct radeon_connector_atom_dig {
375771fe6b9SJerome Glisse 	uint32_t igp_lane_info;
3764143e919SAlex Deucher 	/* displayport */
377746c1aa4SDave Airlie 	struct radeon_i2c_chan *dp_i2c_bus;
3781a66c95aSAlex Deucher 	u8 dpcd[8];
3794143e919SAlex Deucher 	u8 dp_sink_type;
3805801ead6SAlex Deucher 	int dp_clock;
3815801ead6SAlex Deucher 	int dp_lane_count;
382771fe6b9SJerome Glisse };
383771fe6b9SJerome Glisse 
384eed45b30SAlex Deucher struct radeon_gpio_rec {
385eed45b30SAlex Deucher 	bool valid;
386eed45b30SAlex Deucher 	u8 id;
387eed45b30SAlex Deucher 	u32 reg;
388eed45b30SAlex Deucher 	u32 mask;
389eed45b30SAlex Deucher };
390eed45b30SAlex Deucher 
391eed45b30SAlex Deucher struct radeon_hpd {
392eed45b30SAlex Deucher 	enum radeon_hpd_id hpd;
393eed45b30SAlex Deucher 	u8 plugged_state;
394eed45b30SAlex Deucher 	struct radeon_gpio_rec gpio;
395eed45b30SAlex Deucher };
396eed45b30SAlex Deucher 
39726b5bc98SAlex Deucher struct radeon_router {
39826b5bc98SAlex Deucher 	bool valid;
39926b5bc98SAlex Deucher 	u32 router_id;
40026b5bc98SAlex Deucher 	struct radeon_i2c_bus_rec i2c_info;
40126b5bc98SAlex Deucher 	u8 i2c_addr;
40226b5bc98SAlex Deucher 	u8 mux_type;
40326b5bc98SAlex Deucher 	u8 mux_control_pin;
40426b5bc98SAlex Deucher 	u8 mux_state;
40526b5bc98SAlex Deucher };
40626b5bc98SAlex Deucher 
407771fe6b9SJerome Glisse struct radeon_connector {
408771fe6b9SJerome Glisse 	struct drm_connector base;
409771fe6b9SJerome Glisse 	uint32_t connector_id;
410771fe6b9SJerome Glisse 	uint32_t devices;
411771fe6b9SJerome Glisse 	struct radeon_i2c_chan *ddc_bus;
4125b1714d3SAlex Deucher 	/* some systems have an hdmi and vga port with a shared ddc line */
4130294cf4fSAlex Deucher 	bool shared_ddc;
4144ce001abSDave Airlie 	bool use_digital;
4154ce001abSDave Airlie 	/* we need to mind the EDID between detect
4164ce001abSDave Airlie 	   and get modes due to analog/digital/tvencoder */
4174ce001abSDave Airlie 	struct edid *edid;
418771fe6b9SJerome Glisse 	void *con_priv;
419445282dbSDave Airlie 	bool dac_load_detect;
420b75fad06SAlex Deucher 	uint16_t connector_object_id;
421eed45b30SAlex Deucher 	struct radeon_hpd hpd;
42226b5bc98SAlex Deucher 	struct radeon_router router;
42326b5bc98SAlex Deucher 	struct radeon_i2c_chan *router_bus;
424771fe6b9SJerome Glisse };
425771fe6b9SJerome Glisse 
426771fe6b9SJerome Glisse struct radeon_framebuffer {
427771fe6b9SJerome Glisse 	struct drm_framebuffer base;
428771fe6b9SJerome Glisse 	struct drm_gem_object *obj;
429771fe6b9SJerome Glisse };
430771fe6b9SJerome Glisse 
4316383cf7dSMario Kleiner /* radeon_get_crtc_scanoutpos() return flags */
4326383cf7dSMario Kleiner #define RADEON_SCANOUTPOS_VALID        (1 << 0)
4336383cf7dSMario Kleiner #define RADEON_SCANOUTPOS_INVBL        (1 << 1)
4346383cf7dSMario Kleiner #define RADEON_SCANOUTPOS_ACCURATE     (1 << 2)
4356383cf7dSMario Kleiner 
436d79766faSAlex Deucher extern enum radeon_tv_std
437d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev);
438d79766faSAlex Deucher extern enum radeon_tv_std
439d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev);
440d79766faSAlex Deucher 
4415b1714d3SAlex Deucher extern struct drm_connector *
4425b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder);
4435b1714d3SAlex Deucher 
444d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector);
445d4877cf2SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
4465801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
4475801ead6SAlex Deucher 				       struct drm_display_mode *mode);
4485801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector,
4495801ead6SAlex Deucher 				      struct drm_display_mode *mode);
4505801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder,
4515801ead6SAlex Deucher 			  struct drm_connector *connector);
4524143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
4539fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
454bcc1c2a1SAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
4555801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
4565801ead6SAlex Deucher 					   int action, uint8_t lane_num,
4575801ead6SAlex Deucher 					   uint8_t lane_set);
458746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
459746c1aa4SDave Airlie 				uint8_t write_byte, uint8_t *read_byte);
460746c1aa4SDave Airlie 
461f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev);
462f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev);
463f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev);
464f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
465f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev,
466f376b94fSAlex Deucher 			   struct radeon_i2c_bus_rec *rec,
467f376b94fSAlex Deucher 			   const char *name);
468f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
469f376b94fSAlex Deucher 						 struct radeon_i2c_bus_rec *i2c_bus);
470746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
4716a93cb25SAlex Deucher 						    struct radeon_i2c_bus_rec *rec,
4726a93cb25SAlex Deucher 						    const char *name);
473771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
474771fe6b9SJerome Glisse 						 struct radeon_i2c_bus_rec *rec,
475771fe6b9SJerome Glisse 						 const char *name);
476771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
4775a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
478fcec570bSAlex Deucher 				u8 slave_addr,
479fcec570bSAlex Deucher 				u8 addr,
480fcec570bSAlex Deucher 				u8 *val);
4815a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
482fcec570bSAlex Deucher 				u8 slave_addr,
483fcec570bSAlex Deucher 				u8 addr,
484fcec570bSAlex Deucher 				u8 val);
48526b5bc98SAlex Deucher extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
486771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
487771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
488771fe6b9SJerome Glisse 
489771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
490771fe6b9SJerome Glisse 
491ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
492ba032a58SAlex Deucher 					     struct radeon_atom_ss *ss,
493ba032a58SAlex Deucher 					     int id);
494ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
495ba032a58SAlex Deucher 					     struct radeon_atom_ss *ss,
496ba032a58SAlex Deucher 					     int id, u32 clock);
497ba032a58SAlex Deucher 
498771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll,
499771fe6b9SJerome Glisse 			       uint64_t freq,
500771fe6b9SJerome Glisse 			       uint32_t *dot_clock_p,
501771fe6b9SJerome Glisse 			       uint32_t *fb_div_p,
502771fe6b9SJerome Glisse 			       uint32_t *frac_fb_div_p,
503771fe6b9SJerome Glisse 			       uint32_t *ref_div_p,
504fc10332bSAlex Deucher 			       uint32_t *post_div_p);
505771fe6b9SJerome Glisse 
5061f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev);
5071f3b6a45SDave Airlie 
508771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
509771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
510771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
511771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
512771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
513771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
51432f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
515771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
5164ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
517771fe6b9SJerome Glisse 
518771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
519771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
520771fe6b9SJerome Glisse 				   struct drm_framebuffer *old_fb);
521771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
522771fe6b9SJerome Glisse 				   struct drm_display_mode *mode,
523771fe6b9SJerome Glisse 				   struct drm_display_mode *adjusted_mode,
524771fe6b9SJerome Glisse 				   int x, int y,
525771fe6b9SJerome Glisse 				   struct drm_framebuffer *old_fb);
526771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
527771fe6b9SJerome Glisse 
528771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
529771fe6b9SJerome Glisse 				 struct drm_framebuffer *old_fb);
530771fe6b9SJerome Glisse 
531771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
532771fe6b9SJerome Glisse 				  struct drm_file *file_priv,
533771fe6b9SJerome Glisse 				  uint32_t handle,
534771fe6b9SJerome Glisse 				  uint32_t width,
535771fe6b9SJerome Glisse 				  uint32_t height);
536771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
537771fe6b9SJerome Glisse 				   int x, int y);
538771fe6b9SJerome Glisse 
5396383cf7dSMario Kleiner extern int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos);
5406383cf7dSMario Kleiner 
5413c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
5423c537889SAlex Deucher extern struct edid *
5433c537889SAlex Deucher radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
544771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev);
545771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev);
546771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig *
547771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
548fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
549445282dbSDave Airlie 					  struct radeon_encoder_int_tmds *tmds);
550fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
551445282dbSDave Airlie 						     struct radeon_encoder_int_tmds *tmds);
552fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
553445282dbSDave Airlie 						   struct radeon_encoder_int_tmds *tmds);
554fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
555fcec570bSAlex Deucher 							 struct radeon_encoder_ext_tmds *tmds);
556fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
557fcec570bSAlex Deucher 						       struct radeon_encoder_ext_tmds *tmds);
5586fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac *
5596fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
5606fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac *
5616fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
562771fe6b9SJerome Glisse extern struct radeon_encoder_lvds *
563771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
564771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
565771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac *
566771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
567771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac *
568771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
569fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
570fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
571771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
572771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
573771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
574771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
575f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
576f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
577771fe6b9SJerome Glisse extern void
578771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
579771fe6b9SJerome Glisse extern void
580771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
581771fe6b9SJerome Glisse extern void
582771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
583771fe6b9SJerome Glisse extern void
584771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
585771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
586771fe6b9SJerome Glisse 				     u16 blue, int regno);
587b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
588b8c00ac5SDave Airlie 				     u16 *blue, int regno);
58938651674SDave Airlie void radeon_framebuffer_init(struct drm_device *dev,
59038651674SDave Airlie 			     struct radeon_framebuffer *rfb,
591771fe6b9SJerome Glisse 			     struct drm_mode_fb_cmd *mode_cmd,
592771fe6b9SJerome Glisse 			     struct drm_gem_object *obj);
593771fe6b9SJerome Glisse 
594771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
595771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
596771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
597771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev,
598771fe6b9SJerome Glisse 			       struct radeon_crtc *radeon_crtc);
599771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev,
600771fe6b9SJerome Glisse 			     struct radeon_crtc *radeon_crtc);
601771fe6b9SJerome Glisse 
602771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev);
603771fe6b9SJerome Glisse 
604771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
605771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
606771fe6b9SJerome Glisse 
607771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder);
608771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
609771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev);
610c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
611c93bb85bSJerome Glisse 					struct drm_display_mode *mode,
612c93bb85bSJerome Glisse 					struct drm_display_mode *adjusted_mode);
6133515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder,
6143515387bSAlex Deucher 			     struct drm_display_mode *adjusted_mode);
6154ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
616771fe6b9SJerome Glisse 
6174ce001abSDave Airlie /* legacy tv */
6184ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
6194ce001abSDave Airlie 				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
6204ce001abSDave Airlie 				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
6214ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
6224ce001abSDave Airlie 				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
6234ce001abSDave Airlie 				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
6244ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
6254ce001abSDave Airlie 				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
6264ce001abSDave Airlie 				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
6274ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
6284ce001abSDave Airlie 			       struct drm_display_mode *mode,
6294ce001abSDave Airlie 			       struct drm_display_mode *adjusted_mode);
63038651674SDave Airlie 
63138651674SDave Airlie /* fbdev layer */
63238651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev);
63338651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev);
63438651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
63538651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev);
63638651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
637eb1f8e4fSDave Airlie 
638eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev);
639771fe6b9SJerome Glisse #endif
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