1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36771fe6b9SJerome Glisse #include <linux/i2c.h> 37771fe6b9SJerome Glisse #include <linux/i2c-id.h> 38771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 39c93bb85bSJerome Glisse #include "radeon_fixed.h" 40c93bb85bSJerome Glisse 41c93bb85bSJerome Glisse struct radeon_device; 42771fe6b9SJerome Glisse 43771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 44771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 45771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 46771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 47771fe6b9SJerome Glisse 48771fe6b9SJerome Glisse enum radeon_connector_type { 49771fe6b9SJerome Glisse CONNECTOR_NONE, 50771fe6b9SJerome Glisse CONNECTOR_VGA, 51771fe6b9SJerome Glisse CONNECTOR_DVI_I, 52771fe6b9SJerome Glisse CONNECTOR_DVI_D, 53771fe6b9SJerome Glisse CONNECTOR_DVI_A, 54771fe6b9SJerome Glisse CONNECTOR_STV, 55771fe6b9SJerome Glisse CONNECTOR_CTV, 56771fe6b9SJerome Glisse CONNECTOR_LVDS, 57771fe6b9SJerome Glisse CONNECTOR_DIGITAL, 58771fe6b9SJerome Glisse CONNECTOR_SCART, 59771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_A, 60771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_B, 61771fe6b9SJerome Glisse CONNECTOR_0XC, 62771fe6b9SJerome Glisse CONNECTOR_0XD, 63771fe6b9SJerome Glisse CONNECTOR_DIN, 64771fe6b9SJerome Glisse CONNECTOR_DISPLAY_PORT, 65771fe6b9SJerome Glisse CONNECTOR_UNSUPPORTED 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 68771fe6b9SJerome Glisse enum radeon_dvi_type { 69771fe6b9SJerome Glisse DVI_AUTO, 70771fe6b9SJerome Glisse DVI_DIGITAL, 71771fe6b9SJerome Glisse DVI_ANALOG 72771fe6b9SJerome Glisse }; 73771fe6b9SJerome Glisse 74771fe6b9SJerome Glisse enum radeon_rmx_type { 75771fe6b9SJerome Glisse RMX_OFF, 76771fe6b9SJerome Glisse RMX_FULL, 77771fe6b9SJerome Glisse RMX_CENTER, 78771fe6b9SJerome Glisse RMX_ASPECT 79771fe6b9SJerome Glisse }; 80771fe6b9SJerome Glisse 81771fe6b9SJerome Glisse enum radeon_tv_std { 82771fe6b9SJerome Glisse TV_STD_NTSC, 83771fe6b9SJerome Glisse TV_STD_PAL, 84771fe6b9SJerome Glisse TV_STD_PAL_M, 85771fe6b9SJerome Glisse TV_STD_PAL_60, 86771fe6b9SJerome Glisse TV_STD_NTSC_J, 87771fe6b9SJerome Glisse TV_STD_SCART_PAL, 88771fe6b9SJerome Glisse TV_STD_SECAM, 89771fe6b9SJerome Glisse TV_STD_PAL_CN, 90771fe6b9SJerome Glisse }; 91771fe6b9SJerome Glisse 92771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 93771fe6b9SJerome Glisse bool valid; 94771fe6b9SJerome Glisse uint32_t mask_clk_reg; 95771fe6b9SJerome Glisse uint32_t mask_data_reg; 96771fe6b9SJerome Glisse uint32_t a_clk_reg; 97771fe6b9SJerome Glisse uint32_t a_data_reg; 98771fe6b9SJerome Glisse uint32_t put_clk_reg; 99771fe6b9SJerome Glisse uint32_t put_data_reg; 100771fe6b9SJerome Glisse uint32_t get_clk_reg; 101771fe6b9SJerome Glisse uint32_t get_data_reg; 102771fe6b9SJerome Glisse uint32_t mask_clk_mask; 103771fe6b9SJerome Glisse uint32_t mask_data_mask; 104771fe6b9SJerome Glisse uint32_t put_clk_mask; 105771fe6b9SJerome Glisse uint32_t put_data_mask; 106771fe6b9SJerome Glisse uint32_t get_clk_mask; 107771fe6b9SJerome Glisse uint32_t get_data_mask; 108771fe6b9SJerome Glisse uint32_t a_clk_mask; 109771fe6b9SJerome Glisse uint32_t a_data_mask; 110771fe6b9SJerome Glisse }; 111771fe6b9SJerome Glisse 112771fe6b9SJerome Glisse struct radeon_tmds_pll { 113771fe6b9SJerome Glisse uint32_t freq; 114771fe6b9SJerome Glisse uint32_t value; 115771fe6b9SJerome Glisse }; 116771fe6b9SJerome Glisse 117771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 118771fe6b9SJerome Glisse 119771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 120771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 121771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 122771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 123771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 124771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 125771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 126771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 127771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 128771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 129771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 130d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 131771fe6b9SJerome Glisse 132771fe6b9SJerome Glisse struct radeon_pll { 133771fe6b9SJerome Glisse uint16_t reference_freq; 134771fe6b9SJerome Glisse uint16_t reference_div; 135771fe6b9SJerome Glisse uint32_t pll_in_min; 136771fe6b9SJerome Glisse uint32_t pll_in_max; 137771fe6b9SJerome Glisse uint32_t pll_out_min; 138771fe6b9SJerome Glisse uint32_t pll_out_max; 139771fe6b9SJerome Glisse uint16_t xclk; 140771fe6b9SJerome Glisse 141771fe6b9SJerome Glisse uint32_t min_ref_div; 142771fe6b9SJerome Glisse uint32_t max_ref_div; 143771fe6b9SJerome Glisse uint32_t min_post_div; 144771fe6b9SJerome Glisse uint32_t max_post_div; 145771fe6b9SJerome Glisse uint32_t min_feedback_div; 146771fe6b9SJerome Glisse uint32_t max_feedback_div; 147771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 148771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 149771fe6b9SJerome Glisse uint32_t best_vco; 150771fe6b9SJerome Glisse }; 151771fe6b9SJerome Glisse 152771fe6b9SJerome Glisse struct radeon_i2c_chan { 153771fe6b9SJerome Glisse struct drm_device *dev; 154771fe6b9SJerome Glisse struct i2c_adapter adapter; 155771fe6b9SJerome Glisse struct i2c_algo_bit_data algo; 156771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 157771fe6b9SJerome Glisse }; 158771fe6b9SJerome Glisse 159771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 160771fe6b9SJerome Glisse enum radeon_connector_table { 161771fe6b9SJerome Glisse CT_NONE, 162771fe6b9SJerome Glisse CT_GENERIC, 163771fe6b9SJerome Glisse CT_IBOOK, 164771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 165771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 166771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 167771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 168771fe6b9SJerome Glisse CT_MINI_INTERNAL, 169771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 170771fe6b9SJerome Glisse CT_EMAC, 171771fe6b9SJerome Glisse }; 172771fe6b9SJerome Glisse 173771fe6b9SJerome Glisse struct radeon_mode_info { 174771fe6b9SJerome Glisse struct atom_context *atom_context; 175771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 176771fe6b9SJerome Glisse bool mode_config_initialized; 177c93bb85bSJerome Glisse struct radeon_crtc *crtcs[2]; 178c93bb85bSJerome Glisse }; 179c93bb85bSJerome Glisse 180c93bb85bSJerome Glisse struct radeon_native_mode { 181c93bb85bSJerome Glisse /* preferred mode */ 182c93bb85bSJerome Glisse uint32_t panel_xres, panel_yres; 183c93bb85bSJerome Glisse uint32_t hoverplus, hsync_width; 184c93bb85bSJerome Glisse uint32_t hblank; 185c93bb85bSJerome Glisse uint32_t voverplus, vsync_width; 186c93bb85bSJerome Glisse uint32_t vblank; 187c93bb85bSJerome Glisse uint32_t dotclock; 188c93bb85bSJerome Glisse uint32_t flags; 189771fe6b9SJerome Glisse }; 190771fe6b9SJerome Glisse 1914ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 1924ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 1934ce001abSDave Airlie 1944ce001abSDave Airlie /* need to store these as reading 1954ce001abSDave Airlie back code tables is excessive */ 1964ce001abSDave Airlie struct radeon_tv_regs { 1974ce001abSDave Airlie uint32_t tv_uv_adr; 1984ce001abSDave Airlie uint32_t timing_cntl; 1994ce001abSDave Airlie uint32_t hrestart; 2004ce001abSDave Airlie uint32_t vrestart; 2014ce001abSDave Airlie uint32_t frestart; 2024ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2034ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2044ce001abSDave Airlie }; 2054ce001abSDave Airlie 206771fe6b9SJerome Glisse struct radeon_crtc { 207771fe6b9SJerome Glisse struct drm_crtc base; 208771fe6b9SJerome Glisse int crtc_id; 209771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 210771fe6b9SJerome Glisse bool enabled; 211771fe6b9SJerome Glisse bool can_tile; 212771fe6b9SJerome Glisse uint32_t crtc_offset; 213771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 214771fe6b9SJerome Glisse uint64_t cursor_addr; 215771fe6b9SJerome Glisse int cursor_width; 216771fe6b9SJerome Glisse int cursor_height; 2174162338aSDave Airlie uint32_t legacy_display_base_addr; 218c836e862SAlex Deucher uint32_t legacy_cursor_offset; 219c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 220c93bb85bSJerome Glisse fixed20_12 vsc; 221c93bb85bSJerome Glisse fixed20_12 hsc; 222c93bb85bSJerome Glisse struct radeon_native_mode native_mode; 223771fe6b9SJerome Glisse }; 224771fe6b9SJerome Glisse 225771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 226771fe6b9SJerome Glisse /* legacy primary dac */ 227771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 228771fe6b9SJerome Glisse }; 229771fe6b9SJerome Glisse 230771fe6b9SJerome Glisse struct radeon_encoder_lvds { 231771fe6b9SJerome Glisse /* legacy lvds */ 232771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 233771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 234771fe6b9SJerome Glisse uint8_t panel_digon_delay; 235771fe6b9SJerome Glisse uint8_t panel_blon_delay; 236771fe6b9SJerome Glisse uint16_t panel_ref_divider; 237771fe6b9SJerome Glisse uint8_t panel_post_divider; 238771fe6b9SJerome Glisse uint16_t panel_fb_divider; 239771fe6b9SJerome Glisse bool use_bios_dividers; 240771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 241771fe6b9SJerome Glisse /* panel mode */ 242771fe6b9SJerome Glisse struct radeon_native_mode native_mode; 243771fe6b9SJerome Glisse }; 244771fe6b9SJerome Glisse 245771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 246771fe6b9SJerome Glisse /* legacy tv dac */ 247771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 248771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 249771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 250771fe6b9SJerome Glisse 2514ce001abSDave Airlie int h_pos; 2524ce001abSDave Airlie int v_pos; 2534ce001abSDave Airlie int h_size; 2544ce001abSDave Airlie int supported_tv_stds; 2554ce001abSDave Airlie bool tv_on; 256771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 2574ce001abSDave Airlie struct radeon_tv_regs tv; 258771fe6b9SJerome Glisse }; 259771fe6b9SJerome Glisse 260771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 261771fe6b9SJerome Glisse /* legacy int tmds */ 262771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 263771fe6b9SJerome Glisse }; 264771fe6b9SJerome Glisse 265771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 266771fe6b9SJerome Glisse /* atom dig */ 267771fe6b9SJerome Glisse bool coherent_mode; 268771fe6b9SJerome Glisse int dig_block; 269771fe6b9SJerome Glisse /* atom lvds */ 270771fe6b9SJerome Glisse uint32_t lvds_misc; 271771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 272771fe6b9SJerome Glisse /* panel mode */ 273771fe6b9SJerome Glisse struct radeon_native_mode native_mode; 274771fe6b9SJerome Glisse }; 275771fe6b9SJerome Glisse 2764ce001abSDave Airlie struct radeon_encoder_atom_dac { 2774ce001abSDave Airlie enum radeon_tv_std tv_std; 2784ce001abSDave Airlie }; 2794ce001abSDave Airlie 280771fe6b9SJerome Glisse struct radeon_encoder { 281771fe6b9SJerome Glisse struct drm_encoder base; 282771fe6b9SJerome Glisse uint32_t encoder_id; 283771fe6b9SJerome Glisse uint32_t devices; 2844ce001abSDave Airlie uint32_t active_device; 285771fe6b9SJerome Glisse uint32_t flags; 286771fe6b9SJerome Glisse uint32_t pixel_clock; 287771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 288771fe6b9SJerome Glisse struct radeon_native_mode native_mode; 289771fe6b9SJerome Glisse void *enc_priv; 290771fe6b9SJerome Glisse }; 291771fe6b9SJerome Glisse 292771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 293771fe6b9SJerome Glisse uint32_t igp_lane_info; 294771fe6b9SJerome Glisse bool linkb; 295771fe6b9SJerome Glisse }; 296771fe6b9SJerome Glisse 297771fe6b9SJerome Glisse struct radeon_connector { 298771fe6b9SJerome Glisse struct drm_connector base; 299771fe6b9SJerome Glisse uint32_t connector_id; 300771fe6b9SJerome Glisse uint32_t devices; 301771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 3024ce001abSDave Airlie bool use_digital; 3034ce001abSDave Airlie /* we need to mind the EDID between detect 3044ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 3054ce001abSDave Airlie struct edid *edid; 306771fe6b9SJerome Glisse void *con_priv; 307771fe6b9SJerome Glisse }; 308771fe6b9SJerome Glisse 309771fe6b9SJerome Glisse struct radeon_framebuffer { 310771fe6b9SJerome Glisse struct drm_framebuffer base; 311771fe6b9SJerome Glisse struct drm_gem_object *obj; 312771fe6b9SJerome Glisse }; 313771fe6b9SJerome Glisse 314771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 315771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 316771fe6b9SJerome Glisse const char *name); 317771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 318771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 319771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 320771fe6b9SJerome Glisse 321771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 322771fe6b9SJerome Glisse 323771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 324771fe6b9SJerome Glisse uint64_t freq, 325771fe6b9SJerome Glisse uint32_t *dot_clock_p, 326771fe6b9SJerome Glisse uint32_t *fb_div_p, 327771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 328771fe6b9SJerome Glisse uint32_t *ref_div_p, 329771fe6b9SJerome Glisse uint32_t *post_div_p, 330771fe6b9SJerome Glisse int flags); 331771fe6b9SJerome Glisse 332771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 333771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 334771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 335771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 336771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 337771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 338771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 3394ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 340771fe6b9SJerome Glisse 341771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 342771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 343771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 344771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 345771fe6b9SJerome Glisse struct drm_display_mode *mode, 346771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 347771fe6b9SJerome Glisse int x, int y, 348771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 349771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 350771fe6b9SJerome Glisse 351771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 352771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 353771fe6b9SJerome Glisse extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); 354771fe6b9SJerome Glisse 355771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 356771fe6b9SJerome Glisse struct drm_file *file_priv, 357771fe6b9SJerome Glisse uint32_t handle, 358771fe6b9SJerome Glisse uint32_t width, 359771fe6b9SJerome Glisse uint32_t height); 360771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 361771fe6b9SJerome Glisse int x, int y); 362771fe6b9SJerome Glisse 363771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 364771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 365771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 366771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 367771fe6b9SJerome Glisse extern struct radeon_encoder_int_tmds * 368771fe6b9SJerome Glisse radeon_atombios_get_tmds_info(struct radeon_encoder *encoder); 3696fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 3706fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 3716fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 3726fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 373771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 374771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 375771fe6b9SJerome Glisse extern struct radeon_encoder_int_tmds * 376771fe6b9SJerome Glisse radeon_combios_get_tmds_info(struct radeon_encoder *encoder); 377771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 378771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 379771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 380771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 381771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 382771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 383771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 384771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 385771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 386771fe6b9SJerome Glisse extern void 387771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 388771fe6b9SJerome Glisse extern void 389771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 390771fe6b9SJerome Glisse extern void 391771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 392771fe6b9SJerome Glisse extern void 393771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 394771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 395771fe6b9SJerome Glisse u16 blue, int regno); 396771fe6b9SJerome Glisse struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, 397771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 398771fe6b9SJerome Glisse struct drm_gem_object *obj); 399771fe6b9SJerome Glisse 400771fe6b9SJerome Glisse int radeonfb_probe(struct drm_device *dev); 401771fe6b9SJerome Glisse 402771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 403771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 404771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 405771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 406771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 407771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 408771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 409771fe6b9SJerome Glisse void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state); 410771fe6b9SJerome Glisse 411771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 412771fe6b9SJerome Glisse 413771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 414771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 415771fe6b9SJerome Glisse 416771fe6b9SJerome Glisse void radeon_rmx_mode_fixup(struct drm_encoder *encoder, 417771fe6b9SJerome Glisse struct drm_display_mode *mode, 418771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode); 419771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 420771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 421771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 422771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev); 423c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 424c93bb85bSJerome Glisse struct drm_display_mode *mode, 425c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 4264ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 427771fe6b9SJerome Glisse 4284ce001abSDave Airlie /* legacy tv */ 4294ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 4304ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 4314ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 4324ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 4334ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 4344ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 4354ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 4364ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 4374ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 4384ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 4394ce001abSDave Airlie struct drm_display_mode *mode, 4404ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 441771fe6b9SJerome Glisse #endif 442