1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36746c1aa4SDave Airlie #include <drm_dp_helper.h> 37771fe6b9SJerome Glisse #include <linux/i2c.h> 38771fe6b9SJerome Glisse #include <linux/i2c-id.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse #include "radeon_fixed.h" 41c93bb85bSJerome Glisse 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 49771fe6b9SJerome Glisse enum radeon_rmx_type { 50771fe6b9SJerome Glisse RMX_OFF, 51771fe6b9SJerome Glisse RMX_FULL, 52771fe6b9SJerome Glisse RMX_CENTER, 53771fe6b9SJerome Glisse RMX_ASPECT 54771fe6b9SJerome Glisse }; 55771fe6b9SJerome Glisse 56771fe6b9SJerome Glisse enum radeon_tv_std { 57771fe6b9SJerome Glisse TV_STD_NTSC, 58771fe6b9SJerome Glisse TV_STD_PAL, 59771fe6b9SJerome Glisse TV_STD_PAL_M, 60771fe6b9SJerome Glisse TV_STD_PAL_60, 61771fe6b9SJerome Glisse TV_STD_NTSC_J, 62771fe6b9SJerome Glisse TV_STD_SCART_PAL, 63771fe6b9SJerome Glisse TV_STD_SECAM, 64771fe6b9SJerome Glisse TV_STD_PAL_CN, 65d79766faSAlex Deucher TV_STD_PAL_N, 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 689b9fe724SAlex Deucher /* radeon gpio-based i2c 699b9fe724SAlex Deucher * 1. "mask" reg and bits 709b9fe724SAlex Deucher * grabs the gpio pins for software use 719b9fe724SAlex Deucher * 0=not held 1=held 729b9fe724SAlex Deucher * 2. "a" reg and bits 739b9fe724SAlex Deucher * output pin value 749b9fe724SAlex Deucher * 0=low 1=high 759b9fe724SAlex Deucher * 3. "en" reg and bits 769b9fe724SAlex Deucher * sets the pin direction 779b9fe724SAlex Deucher * 0=input 1=output 789b9fe724SAlex Deucher * 4. "y" reg and bits 799b9fe724SAlex Deucher * input pin value 809b9fe724SAlex Deucher * 0=low 1=high 819b9fe724SAlex Deucher */ 82771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 83771fe6b9SJerome Glisse bool valid; 846a93cb25SAlex Deucher /* id used by atom */ 856a93cb25SAlex Deucher uint8_t i2c_id; 866a93cb25SAlex Deucher /* can be used with hw i2c engine */ 876a93cb25SAlex Deucher bool hw_capable; 886a93cb25SAlex Deucher /* uses multi-media i2c engine */ 896a93cb25SAlex Deucher bool mm_i2c; 906a93cb25SAlex Deucher /* regs and bits */ 91771fe6b9SJerome Glisse uint32_t mask_clk_reg; 92771fe6b9SJerome Glisse uint32_t mask_data_reg; 93771fe6b9SJerome Glisse uint32_t a_clk_reg; 94771fe6b9SJerome Glisse uint32_t a_data_reg; 959b9fe724SAlex Deucher uint32_t en_clk_reg; 969b9fe724SAlex Deucher uint32_t en_data_reg; 979b9fe724SAlex Deucher uint32_t y_clk_reg; 989b9fe724SAlex Deucher uint32_t y_data_reg; 99771fe6b9SJerome Glisse uint32_t mask_clk_mask; 100771fe6b9SJerome Glisse uint32_t mask_data_mask; 101771fe6b9SJerome Glisse uint32_t a_clk_mask; 102771fe6b9SJerome Glisse uint32_t a_data_mask; 1039b9fe724SAlex Deucher uint32_t en_clk_mask; 1049b9fe724SAlex Deucher uint32_t en_data_mask; 1059b9fe724SAlex Deucher uint32_t y_clk_mask; 1069b9fe724SAlex Deucher uint32_t y_data_mask; 107771fe6b9SJerome Glisse }; 108771fe6b9SJerome Glisse 109771fe6b9SJerome Glisse struct radeon_tmds_pll { 110771fe6b9SJerome Glisse uint32_t freq; 111771fe6b9SJerome Glisse uint32_t value; 112771fe6b9SJerome Glisse }; 113771fe6b9SJerome Glisse 114771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 115771fe6b9SJerome Glisse 116771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 117771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 118771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 119771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 120771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 121771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 122771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 123771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 124771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 125771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 126771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 127d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 128fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 129771fe6b9SJerome Glisse 130771fe6b9SJerome Glisse struct radeon_pll { 131fc10332bSAlex Deucher /* reference frequency */ 132fc10332bSAlex Deucher uint32_t reference_freq; 133fc10332bSAlex Deucher 134fc10332bSAlex Deucher /* fixed dividers */ 135fc10332bSAlex Deucher uint32_t reference_div; 136fc10332bSAlex Deucher uint32_t post_div; 137fc10332bSAlex Deucher 138fc10332bSAlex Deucher /* pll in/out limits */ 139771fe6b9SJerome Glisse uint32_t pll_in_min; 140771fe6b9SJerome Glisse uint32_t pll_in_max; 141771fe6b9SJerome Glisse uint32_t pll_out_min; 142771fe6b9SJerome Glisse uint32_t pll_out_max; 143fc10332bSAlex Deucher uint32_t best_vco; 144771fe6b9SJerome Glisse 145fc10332bSAlex Deucher /* divider limits */ 146771fe6b9SJerome Glisse uint32_t min_ref_div; 147771fe6b9SJerome Glisse uint32_t max_ref_div; 148771fe6b9SJerome Glisse uint32_t min_post_div; 149771fe6b9SJerome Glisse uint32_t max_post_div; 150771fe6b9SJerome Glisse uint32_t min_feedback_div; 151771fe6b9SJerome Glisse uint32_t max_feedback_div; 152771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 153771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 154fc10332bSAlex Deucher 155fc10332bSAlex Deucher /* flags for the current clock */ 156fc10332bSAlex Deucher uint32_t flags; 157fc10332bSAlex Deucher 158fc10332bSAlex Deucher /* pll id */ 159fc10332bSAlex Deucher uint32_t id; 160771fe6b9SJerome Glisse }; 161771fe6b9SJerome Glisse 1625a6f98f5SAlex Deucher struct i2c_algo_radeon_data { 1635a6f98f5SAlex Deucher struct i2c_adapter bit_adapter; 1645a6f98f5SAlex Deucher struct i2c_algo_bit_data bit_data; 1655a6f98f5SAlex Deucher }; 1665a6f98f5SAlex Deucher 167771fe6b9SJerome Glisse struct radeon_i2c_chan { 168771fe6b9SJerome Glisse struct i2c_adapter adapter; 169746c1aa4SDave Airlie struct drm_device *dev; 170746c1aa4SDave Airlie union { 171746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 1725a6f98f5SAlex Deucher struct i2c_algo_radeon_data radeon; 173746c1aa4SDave Airlie } algo; 174771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 175771fe6b9SJerome Glisse }; 176771fe6b9SJerome Glisse 177771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 178771fe6b9SJerome Glisse enum radeon_connector_table { 179771fe6b9SJerome Glisse CT_NONE, 180771fe6b9SJerome Glisse CT_GENERIC, 181771fe6b9SJerome Glisse CT_IBOOK, 182771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 183771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 184771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 185771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 186771fe6b9SJerome Glisse CT_MINI_INTERNAL, 187771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 188771fe6b9SJerome Glisse CT_EMAC, 189771fe6b9SJerome Glisse }; 190771fe6b9SJerome Glisse 191fcec570bSAlex Deucher enum radeon_dvo_chip { 192fcec570bSAlex Deucher DVO_SIL164, 193fcec570bSAlex Deucher DVO_SIL1178, 194fcec570bSAlex Deucher }; 195fcec570bSAlex Deucher 196771fe6b9SJerome Glisse struct radeon_mode_info { 197771fe6b9SJerome Glisse struct atom_context *atom_context; 19861c4b24bSMathias Fröhlich struct card_info *atom_card_info; 199771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 200771fe6b9SJerome Glisse bool mode_config_initialized; 201c93bb85bSJerome Glisse struct radeon_crtc *crtcs[2]; 202445282dbSDave Airlie /* DVI-I properties */ 203445282dbSDave Airlie struct drm_property *coherent_mode_property; 204445282dbSDave Airlie /* DAC enable load detect */ 205445282dbSDave Airlie struct drm_property *load_detect_property; 206445282dbSDave Airlie /* TV standard load detect */ 207445282dbSDave Airlie struct drm_property *tv_std_property; 208445282dbSDave Airlie /* legacy TMDS PLL detect */ 209445282dbSDave Airlie struct drm_property *tmds_pll_property; 2103c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2113c537889SAlex Deucher struct edid *bios_hardcoded_edid; 212c93bb85bSJerome Glisse }; 213c93bb85bSJerome Glisse 2144ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2154ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2164ce001abSDave Airlie 2174ce001abSDave Airlie /* need to store these as reading 2184ce001abSDave Airlie back code tables is excessive */ 2194ce001abSDave Airlie struct radeon_tv_regs { 2204ce001abSDave Airlie uint32_t tv_uv_adr; 2214ce001abSDave Airlie uint32_t timing_cntl; 2224ce001abSDave Airlie uint32_t hrestart; 2234ce001abSDave Airlie uint32_t vrestart; 2244ce001abSDave Airlie uint32_t frestart; 2254ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2264ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2274ce001abSDave Airlie }; 2284ce001abSDave Airlie 229771fe6b9SJerome Glisse struct radeon_crtc { 230771fe6b9SJerome Glisse struct drm_crtc base; 231771fe6b9SJerome Glisse int crtc_id; 232771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 233771fe6b9SJerome Glisse bool enabled; 234771fe6b9SJerome Glisse bool can_tile; 235771fe6b9SJerome Glisse uint32_t crtc_offset; 236771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 237771fe6b9SJerome Glisse uint64_t cursor_addr; 238771fe6b9SJerome Glisse int cursor_width; 239771fe6b9SJerome Glisse int cursor_height; 2404162338aSDave Airlie uint32_t legacy_display_base_addr; 241c836e862SAlex Deucher uint32_t legacy_cursor_offset; 242c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 243c93bb85bSJerome Glisse fixed20_12 vsc; 244c93bb85bSJerome Glisse fixed20_12 hsc; 245de2103e4SAlex Deucher struct drm_display_mode native_mode; 246771fe6b9SJerome Glisse }; 247771fe6b9SJerome Glisse 248771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 249771fe6b9SJerome Glisse /* legacy primary dac */ 250771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 251771fe6b9SJerome Glisse }; 252771fe6b9SJerome Glisse 253771fe6b9SJerome Glisse struct radeon_encoder_lvds { 254771fe6b9SJerome Glisse /* legacy lvds */ 255771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 256771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 257771fe6b9SJerome Glisse uint8_t panel_digon_delay; 258771fe6b9SJerome Glisse uint8_t panel_blon_delay; 259771fe6b9SJerome Glisse uint16_t panel_ref_divider; 260771fe6b9SJerome Glisse uint8_t panel_post_divider; 261771fe6b9SJerome Glisse uint16_t panel_fb_divider; 262771fe6b9SJerome Glisse bool use_bios_dividers; 263771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 264771fe6b9SJerome Glisse /* panel mode */ 265de2103e4SAlex Deucher struct drm_display_mode native_mode; 266771fe6b9SJerome Glisse }; 267771fe6b9SJerome Glisse 268771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 269771fe6b9SJerome Glisse /* legacy tv dac */ 270771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 271771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 272771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 273771fe6b9SJerome Glisse 2744ce001abSDave Airlie int h_pos; 2754ce001abSDave Airlie int v_pos; 2764ce001abSDave Airlie int h_size; 2774ce001abSDave Airlie int supported_tv_stds; 2784ce001abSDave Airlie bool tv_on; 279771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 2804ce001abSDave Airlie struct radeon_tv_regs tv; 281771fe6b9SJerome Glisse }; 282771fe6b9SJerome Glisse 283771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 284771fe6b9SJerome Glisse /* legacy int tmds */ 285771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 286771fe6b9SJerome Glisse }; 287771fe6b9SJerome Glisse 288fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 289fcec570bSAlex Deucher /* tmds over dvo */ 290fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 291fcec570bSAlex Deucher uint8_t slave_addr; 292fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 293fcec570bSAlex Deucher }; 294fcec570bSAlex Deucher 295ebbe1cb9SAlex Deucher /* spread spectrum */ 296ebbe1cb9SAlex Deucher struct radeon_atom_ss { 297ebbe1cb9SAlex Deucher uint16_t percentage; 298ebbe1cb9SAlex Deucher uint8_t type; 299ebbe1cb9SAlex Deucher uint8_t step; 300ebbe1cb9SAlex Deucher uint8_t delay; 301ebbe1cb9SAlex Deucher uint8_t range; 302ebbe1cb9SAlex Deucher uint8_t refdiv; 303ebbe1cb9SAlex Deucher }; 304ebbe1cb9SAlex Deucher 305771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 306771fe6b9SJerome Glisse /* atom dig */ 307771fe6b9SJerome Glisse bool coherent_mode; 308f28cf339SDave Airlie int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ 309771fe6b9SJerome Glisse /* atom lvds */ 310771fe6b9SJerome Glisse uint32_t lvds_misc; 311771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 312ebbe1cb9SAlex Deucher struct radeon_atom_ss *ss; 313771fe6b9SJerome Glisse /* panel mode */ 314de2103e4SAlex Deucher struct drm_display_mode native_mode; 315771fe6b9SJerome Glisse }; 316771fe6b9SJerome Glisse 3174ce001abSDave Airlie struct radeon_encoder_atom_dac { 3184ce001abSDave Airlie enum radeon_tv_std tv_std; 3194ce001abSDave Airlie }; 3204ce001abSDave Airlie 321771fe6b9SJerome Glisse struct radeon_encoder { 322771fe6b9SJerome Glisse struct drm_encoder base; 323771fe6b9SJerome Glisse uint32_t encoder_id; 324771fe6b9SJerome Glisse uint32_t devices; 3254ce001abSDave Airlie uint32_t active_device; 326771fe6b9SJerome Glisse uint32_t flags; 327771fe6b9SJerome Glisse uint32_t pixel_clock; 328771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 329de2103e4SAlex Deucher struct drm_display_mode native_mode; 330771fe6b9SJerome Glisse void *enc_priv; 331dafc3bd5SChristian Koenig int hdmi_offset; 332dafc3bd5SChristian Koenig int hdmi_audio_workaround; 333dafc3bd5SChristian Koenig int hdmi_buffer_status; 334771fe6b9SJerome Glisse }; 335771fe6b9SJerome Glisse 336771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 337771fe6b9SJerome Glisse uint32_t igp_lane_info; 338771fe6b9SJerome Glisse bool linkb; 3394143e919SAlex Deucher /* displayport */ 340746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 3411a66c95aSAlex Deucher u8 dpcd[8]; 3424143e919SAlex Deucher u8 dp_sink_type; 3435801ead6SAlex Deucher int dp_clock; 3445801ead6SAlex Deucher int dp_lane_count; 345771fe6b9SJerome Glisse }; 346771fe6b9SJerome Glisse 347eed45b30SAlex Deucher struct radeon_gpio_rec { 348eed45b30SAlex Deucher bool valid; 349eed45b30SAlex Deucher u8 id; 350eed45b30SAlex Deucher u32 reg; 351eed45b30SAlex Deucher u32 mask; 352eed45b30SAlex Deucher }; 353eed45b30SAlex Deucher 354eed45b30SAlex Deucher enum radeon_hpd_id { 355eed45b30SAlex Deucher RADEON_HPD_NONE = 0, 356eed45b30SAlex Deucher RADEON_HPD_1, 357eed45b30SAlex Deucher RADEON_HPD_2, 358eed45b30SAlex Deucher RADEON_HPD_3, 359eed45b30SAlex Deucher RADEON_HPD_4, 360eed45b30SAlex Deucher RADEON_HPD_5, 361eed45b30SAlex Deucher RADEON_HPD_6, 362eed45b30SAlex Deucher }; 363eed45b30SAlex Deucher 364eed45b30SAlex Deucher struct radeon_hpd { 365eed45b30SAlex Deucher enum radeon_hpd_id hpd; 366eed45b30SAlex Deucher u8 plugged_state; 367eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 368eed45b30SAlex Deucher }; 369eed45b30SAlex Deucher 370771fe6b9SJerome Glisse struct radeon_connector { 371771fe6b9SJerome Glisse struct drm_connector base; 372771fe6b9SJerome Glisse uint32_t connector_id; 373771fe6b9SJerome Glisse uint32_t devices; 374771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 3750294cf4fSAlex Deucher /* some systems have a an hdmi and vga port with a shared ddc line */ 3760294cf4fSAlex Deucher bool shared_ddc; 3774ce001abSDave Airlie bool use_digital; 3784ce001abSDave Airlie /* we need to mind the EDID between detect 3794ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 3804ce001abSDave Airlie struct edid *edid; 381771fe6b9SJerome Glisse void *con_priv; 382445282dbSDave Airlie bool dac_load_detect; 383b75fad06SAlex Deucher uint16_t connector_object_id; 384eed45b30SAlex Deucher struct radeon_hpd hpd; 385771fe6b9SJerome Glisse }; 386771fe6b9SJerome Glisse 387771fe6b9SJerome Glisse struct radeon_framebuffer { 388771fe6b9SJerome Glisse struct drm_framebuffer base; 389771fe6b9SJerome Glisse struct drm_gem_object *obj; 390771fe6b9SJerome Glisse }; 391771fe6b9SJerome Glisse 392d79766faSAlex Deucher extern enum radeon_tv_std 393d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 394d79766faSAlex Deucher extern enum radeon_tv_std 395d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 396d79766faSAlex Deucher 397d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 398d4877cf2SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 3995801ead6SAlex Deucher extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, 4005801ead6SAlex Deucher struct drm_display_mode *mode); 4015801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 4025801ead6SAlex Deucher struct drm_display_mode *mode); 4035801ead6SAlex Deucher extern void dp_link_train(struct drm_encoder *encoder, 4045801ead6SAlex Deucher struct drm_connector *connector); 4054143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 4069fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 4075801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 4085801ead6SAlex Deucher int action, uint8_t lane_num, 4095801ead6SAlex Deucher uint8_t lane_set); 410746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 411746c1aa4SDave Airlie uint8_t write_byte, uint8_t *read_byte); 412746c1aa4SDave Airlie 413746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 4146a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 4156a93cb25SAlex Deucher const char *name); 416771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 417771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 418771fe6b9SJerome Glisse const char *name); 419771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 4205a6f98f5SAlex Deucher extern void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c); 4215a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 422fcec570bSAlex Deucher u8 slave_addr, 423fcec570bSAlex Deucher u8 addr, 424fcec570bSAlex Deucher u8 *val); 4255a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 426fcec570bSAlex Deucher u8 slave_addr, 427fcec570bSAlex Deucher u8 addr, 428fcec570bSAlex Deucher u8 val); 429771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 430771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 431771fe6b9SJerome Glisse 432771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 433771fe6b9SJerome Glisse 434771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 435771fe6b9SJerome Glisse uint64_t freq, 436771fe6b9SJerome Glisse uint32_t *dot_clock_p, 437771fe6b9SJerome Glisse uint32_t *fb_div_p, 438771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 439771fe6b9SJerome Glisse uint32_t *ref_div_p, 440fc10332bSAlex Deucher uint32_t *post_div_p); 441771fe6b9SJerome Glisse 442b27b6375SAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 443b27b6375SAlex Deucher uint64_t freq, 444b27b6375SAlex Deucher uint32_t *dot_clock_p, 445b27b6375SAlex Deucher uint32_t *fb_div_p, 446b27b6375SAlex Deucher uint32_t *frac_fb_div_p, 447b27b6375SAlex Deucher uint32_t *ref_div_p, 448fc10332bSAlex Deucher uint32_t *post_div_p); 449b27b6375SAlex Deucher 4501f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 4511f3b6a45SDave Airlie 452771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 453771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 454771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 455771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 456771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 457771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 45832f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 459771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 4604ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 461771fe6b9SJerome Glisse 462771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 463771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 464771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 465771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 466771fe6b9SJerome Glisse struct drm_display_mode *mode, 467771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 468771fe6b9SJerome Glisse int x, int y, 469771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 470771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 471771fe6b9SJerome Glisse 472771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 473771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 474771fe6b9SJerome Glisse 475771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 476771fe6b9SJerome Glisse struct drm_file *file_priv, 477771fe6b9SJerome Glisse uint32_t handle, 478771fe6b9SJerome Glisse uint32_t width, 479771fe6b9SJerome Glisse uint32_t height); 480771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 481771fe6b9SJerome Glisse int x, int y); 482771fe6b9SJerome Glisse 4833c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 4843c537889SAlex Deucher extern struct edid * 4853c537889SAlex Deucher radeon_combios_get_hardcoded_edid(struct radeon_device *rdev); 486771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 487771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 488771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 489771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 490fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 491445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 492fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 493445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 494fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 495445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 496fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 497fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 498fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 499fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 5006fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 5016fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 5026fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 5036fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 504771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 505771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 506771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 507771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 508771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 509771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 510771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 511fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 512fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 513771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 514771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 515771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 516771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 517f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 518f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 519771fe6b9SJerome Glisse extern void 520771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 521771fe6b9SJerome Glisse extern void 522771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 523771fe6b9SJerome Glisse extern void 524771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 525771fe6b9SJerome Glisse extern void 526771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 527771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 528771fe6b9SJerome Glisse u16 blue, int regno); 529b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 530b8c00ac5SDave Airlie u16 *blue, int regno); 531771fe6b9SJerome Glisse struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, 532771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 533771fe6b9SJerome Glisse struct drm_gem_object *obj); 534771fe6b9SJerome Glisse 535771fe6b9SJerome Glisse int radeonfb_probe(struct drm_device *dev); 536771fe6b9SJerome Glisse 537771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 538771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 539771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 540771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 541771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 542771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 543771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 544771fe6b9SJerome Glisse 545771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 546771fe6b9SJerome Glisse 547771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 548771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 549771fe6b9SJerome Glisse 550771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 551771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 552771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 553771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev); 554c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 555c93bb85bSJerome Glisse struct drm_display_mode *mode, 556c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 5574ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 558771fe6b9SJerome Glisse 5594ce001abSDave Airlie /* legacy tv */ 5604ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 5614ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 5624ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 5634ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 5644ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 5654ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 5664ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 5674ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 5684ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 5694ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 5704ce001abSDave Airlie struct drm_display_mode *mode, 5714ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 572771fe6b9SJerome Glisse #endif 573