1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33760285e7SDavid Howells #include <drm/drm_crtc.h> 34760285e7SDavid Howells #include <drm/drm_edid.h> 35760285e7SDavid Howells #include <drm/drm_dp_helper.h> 369843ead0SDave Airlie #include <drm/drm_dp_mst_helper.h> 37760285e7SDavid Howells #include <drm/drm_fixed.h> 38760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 39771fe6b9SJerome Glisse #include <linux/i2c.h> 40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 41c93bb85bSJerome Glisse 4238651674SDave Airlie struct radeon_bo; 43c93bb85bSJerome Glisse struct radeon_device; 44771fe6b9SJerome Glisse 45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49771fe6b9SJerome Glisse 5088f39063SStefan Brüns #define RADEON_MAX_HPD_PINS 7 5188f39063SStefan Brüns #define RADEON_MAX_CRTCS 6 5288f39063SStefan Brüns #define RADEON_MAX_AFMT_BLOCKS 7 5388f39063SStefan Brüns 54771fe6b9SJerome Glisse enum radeon_rmx_type { 55771fe6b9SJerome Glisse RMX_OFF, 56771fe6b9SJerome Glisse RMX_FULL, 57771fe6b9SJerome Glisse RMX_CENTER, 58771fe6b9SJerome Glisse RMX_ASPECT 59771fe6b9SJerome Glisse }; 60771fe6b9SJerome Glisse 61771fe6b9SJerome Glisse enum radeon_tv_std { 62771fe6b9SJerome Glisse TV_STD_NTSC, 63771fe6b9SJerome Glisse TV_STD_PAL, 64771fe6b9SJerome Glisse TV_STD_PAL_M, 65771fe6b9SJerome Glisse TV_STD_PAL_60, 66771fe6b9SJerome Glisse TV_STD_NTSC_J, 67771fe6b9SJerome Glisse TV_STD_SCART_PAL, 68771fe6b9SJerome Glisse TV_STD_SECAM, 69771fe6b9SJerome Glisse TV_STD_PAL_CN, 70d79766faSAlex Deucher TV_STD_PAL_N, 71771fe6b9SJerome Glisse }; 72771fe6b9SJerome Glisse 735b1714d3SAlex Deucher enum radeon_underscan_type { 745b1714d3SAlex Deucher UNDERSCAN_OFF, 755b1714d3SAlex Deucher UNDERSCAN_ON, 765b1714d3SAlex Deucher UNDERSCAN_AUTO, 775b1714d3SAlex Deucher }; 785b1714d3SAlex Deucher 798e36ed00SAlex Deucher enum radeon_hpd_id { 808e36ed00SAlex Deucher RADEON_HPD_1 = 0, 818e36ed00SAlex Deucher RADEON_HPD_2, 828e36ed00SAlex Deucher RADEON_HPD_3, 838e36ed00SAlex Deucher RADEON_HPD_4, 848e36ed00SAlex Deucher RADEON_HPD_5, 858e36ed00SAlex Deucher RADEON_HPD_6, 868e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 878e36ed00SAlex Deucher }; 888e36ed00SAlex Deucher 8967ba31d3SAlex Deucher enum radeon_output_csc { 9067ba31d3SAlex Deucher RADEON_OUTPUT_CSC_BYPASS = 0, 9167ba31d3SAlex Deucher RADEON_OUTPUT_CSC_TVRGB = 1, 9267ba31d3SAlex Deucher RADEON_OUTPUT_CSC_YCBCR601 = 2, 9367ba31d3SAlex Deucher RADEON_OUTPUT_CSC_YCBCR709 = 3, 9467ba31d3SAlex Deucher }; 9567ba31d3SAlex Deucher 96f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 97f376b94fSAlex Deucher 989b9fe724SAlex Deucher /* radeon gpio-based i2c 999b9fe724SAlex Deucher * 1. "mask" reg and bits 1009b9fe724SAlex Deucher * grabs the gpio pins for software use 1019b9fe724SAlex Deucher * 0=not held 1=held 1029b9fe724SAlex Deucher * 2. "a" reg and bits 1039b9fe724SAlex Deucher * output pin value 1049b9fe724SAlex Deucher * 0=low 1=high 1059b9fe724SAlex Deucher * 3. "en" reg and bits 1069b9fe724SAlex Deucher * sets the pin direction 1079b9fe724SAlex Deucher * 0=input 1=output 1089b9fe724SAlex Deucher * 4. "y" reg and bits 1099b9fe724SAlex Deucher * input pin value 1109b9fe724SAlex Deucher * 0=low 1=high 1119b9fe724SAlex Deucher */ 112771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 113771fe6b9SJerome Glisse bool valid; 1146a93cb25SAlex Deucher /* id used by atom */ 1156a93cb25SAlex Deucher uint8_t i2c_id; 116bcc1c2a1SAlex Deucher /* id used by atom */ 1178e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1186a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1196a93cb25SAlex Deucher bool hw_capable; 1206a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1216a93cb25SAlex Deucher bool mm_i2c; 1226a93cb25SAlex Deucher /* regs and bits */ 123771fe6b9SJerome Glisse uint32_t mask_clk_reg; 124771fe6b9SJerome Glisse uint32_t mask_data_reg; 125771fe6b9SJerome Glisse uint32_t a_clk_reg; 126771fe6b9SJerome Glisse uint32_t a_data_reg; 1279b9fe724SAlex Deucher uint32_t en_clk_reg; 1289b9fe724SAlex Deucher uint32_t en_data_reg; 1299b9fe724SAlex Deucher uint32_t y_clk_reg; 1309b9fe724SAlex Deucher uint32_t y_data_reg; 131771fe6b9SJerome Glisse uint32_t mask_clk_mask; 132771fe6b9SJerome Glisse uint32_t mask_data_mask; 133771fe6b9SJerome Glisse uint32_t a_clk_mask; 134771fe6b9SJerome Glisse uint32_t a_data_mask; 1359b9fe724SAlex Deucher uint32_t en_clk_mask; 1369b9fe724SAlex Deucher uint32_t en_data_mask; 1379b9fe724SAlex Deucher uint32_t y_clk_mask; 1389b9fe724SAlex Deucher uint32_t y_data_mask; 139771fe6b9SJerome Glisse }; 140771fe6b9SJerome Glisse 141771fe6b9SJerome Glisse struct radeon_tmds_pll { 142771fe6b9SJerome Glisse uint32_t freq; 143771fe6b9SJerome Glisse uint32_t value; 144771fe6b9SJerome Glisse }; 145771fe6b9SJerome Glisse 146771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 147771fe6b9SJerome Glisse 1487c27f87dSAlex Deucher /* pll flags */ 149771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 150771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 151771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 152771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 153771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 154771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 155771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 156771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 157771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 158771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 159771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 160d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 161fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 16286cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 163f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 164771fe6b9SJerome Glisse 165771fe6b9SJerome Glisse struct radeon_pll { 166fc10332bSAlex Deucher /* reference frequency */ 167fc10332bSAlex Deucher uint32_t reference_freq; 168fc10332bSAlex Deucher 169fc10332bSAlex Deucher /* fixed dividers */ 170fc10332bSAlex Deucher uint32_t reference_div; 171fc10332bSAlex Deucher uint32_t post_div; 172fc10332bSAlex Deucher 173fc10332bSAlex Deucher /* pll in/out limits */ 174771fe6b9SJerome Glisse uint32_t pll_in_min; 175771fe6b9SJerome Glisse uint32_t pll_in_max; 176771fe6b9SJerome Glisse uint32_t pll_out_min; 177771fe6b9SJerome Glisse uint32_t pll_out_max; 17886cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 17986cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 180fc10332bSAlex Deucher uint32_t best_vco; 181771fe6b9SJerome Glisse 182fc10332bSAlex Deucher /* divider limits */ 183771fe6b9SJerome Glisse uint32_t min_ref_div; 184771fe6b9SJerome Glisse uint32_t max_ref_div; 185771fe6b9SJerome Glisse uint32_t min_post_div; 186771fe6b9SJerome Glisse uint32_t max_post_div; 187771fe6b9SJerome Glisse uint32_t min_feedback_div; 188771fe6b9SJerome Glisse uint32_t max_feedback_div; 189771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 190771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 191fc10332bSAlex Deucher 192fc10332bSAlex Deucher /* flags for the current clock */ 193fc10332bSAlex Deucher uint32_t flags; 194fc10332bSAlex Deucher 195fc10332bSAlex Deucher /* pll id */ 196fc10332bSAlex Deucher uint32_t id; 197771fe6b9SJerome Glisse }; 198771fe6b9SJerome Glisse 199771fe6b9SJerome Glisse struct radeon_i2c_chan { 200771fe6b9SJerome Glisse struct i2c_adapter adapter; 201746c1aa4SDave Airlie struct drm_device *dev; 202ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 203771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 204496263bfSAlex Deucher struct drm_dp_aux aux; 205379dfc25SAlex Deucher bool has_aux; 206831719d6SAlex Deucher struct mutex mutex; 207771fe6b9SJerome Glisse }; 208771fe6b9SJerome Glisse 209771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 210771fe6b9SJerome Glisse enum radeon_connector_table { 211aa74fbb4SAlex Deucher CT_NONE = 0, 212771fe6b9SJerome Glisse CT_GENERIC, 213771fe6b9SJerome Glisse CT_IBOOK, 214771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 215771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 216771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 217771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 218771fe6b9SJerome Glisse CT_MINI_INTERNAL, 219771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 220771fe6b9SJerome Glisse CT_EMAC, 22176a7142aSDave Airlie CT_RN50_POWER, 222aa74fbb4SAlex Deucher CT_MAC_X800, 2239fad321aSAlex Deucher CT_MAC_G5_9600, 224cafa59b9SAlex Deucher CT_SAM440EP, 225cafa59b9SAlex Deucher CT_MAC_G4_SILVER 226771fe6b9SJerome Glisse }; 227771fe6b9SJerome Glisse 228fcec570bSAlex Deucher enum radeon_dvo_chip { 229fcec570bSAlex Deucher DVO_SIL164, 230fcec570bSAlex Deucher DVO_SIL1178, 231fcec570bSAlex Deucher }; 232fcec570bSAlex Deucher 2338be48d92SDave Airlie struct radeon_fbdev; 23438651674SDave Airlie 2350783986aSAlex Deucher struct radeon_afmt { 2360783986aSAlex Deucher bool enabled; 2370783986aSAlex Deucher int offset; 2380783986aSAlex Deucher bool last_buffer_filled_status; 2390783986aSAlex Deucher int id; 2400783986aSAlex Deucher }; 2410783986aSAlex Deucher 242771fe6b9SJerome Glisse struct radeon_mode_info { 243771fe6b9SJerome Glisse struct atom_context *atom_context; 24461c4b24bSMathias Fröhlich struct card_info *atom_card_info; 245771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 246771fe6b9SJerome Glisse bool mode_config_initialized; 24788f39063SStefan Brüns struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 24888f39063SStefan Brüns struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 249445282dbSDave Airlie /* DVI-I properties */ 250445282dbSDave Airlie struct drm_property *coherent_mode_property; 251445282dbSDave Airlie /* DAC enable load detect */ 252445282dbSDave Airlie struct drm_property *load_detect_property; 2535b1714d3SAlex Deucher /* TV standard */ 254445282dbSDave Airlie struct drm_property *tv_std_property; 255445282dbSDave Airlie /* legacy TMDS PLL detect */ 256445282dbSDave Airlie struct drm_property *tmds_pll_property; 2575b1714d3SAlex Deucher /* underscan */ 2585b1714d3SAlex Deucher struct drm_property *underscan_property; 2595bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2605bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2618666c076SAlex Deucher /* audio */ 2628666c076SAlex Deucher struct drm_property *audio_property; 2636214bb74SAlex Deucher /* FMT dithering */ 2646214bb74SAlex Deucher struct drm_property *dither_property; 26567ba31d3SAlex Deucher /* Output CSC */ 26667ba31d3SAlex Deucher struct drm_property *output_csc_property; 2673c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2683c537889SAlex Deucher struct edid *bios_hardcoded_edid; 269fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 27038651674SDave Airlie 27138651674SDave Airlie /* pointer to fbdev info structure */ 2728be48d92SDave Airlie struct radeon_fbdev *rfbdev; 273af7912e5SAlex Deucher /* firmware flags */ 274af7912e5SAlex Deucher u16 firmware_flags; 275bced76f2SAlex Deucher /* pointer to backlight encoder */ 276bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 2778f0fc088SDave Airlie 2788f0fc088SDave Airlie /* bitmask for active encoder frontends */ 2798f0fc088SDave Airlie uint32_t active_encoders; 280c93bb85bSJerome Glisse }; 281c93bb85bSJerome Glisse 28291030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 28391030880SAlex Deucher 284bced76f2SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 285bced76f2SAlex Deucher 28691030880SAlex Deucher struct radeon_backlight_privdata { 28791030880SAlex Deucher struct radeon_encoder *encoder; 28891030880SAlex Deucher uint8_t negative; 28991030880SAlex Deucher }; 29091030880SAlex Deucher 29191030880SAlex Deucher #endif 29291030880SAlex Deucher 2934ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2944ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2954ce001abSDave Airlie 2964ce001abSDave Airlie /* need to store these as reading 2974ce001abSDave Airlie back code tables is excessive */ 2984ce001abSDave Airlie struct radeon_tv_regs { 2994ce001abSDave Airlie uint32_t tv_uv_adr; 3004ce001abSDave Airlie uint32_t timing_cntl; 3014ce001abSDave Airlie uint32_t hrestart; 3024ce001abSDave Airlie uint32_t vrestart; 3034ce001abSDave Airlie uint32_t frestart; 3044ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 3054ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 3064ce001abSDave Airlie }; 3074ce001abSDave Airlie 30819eca43eSAlex Deucher struct radeon_atom_ss { 30919eca43eSAlex Deucher uint16_t percentage; 31018f8f52bSAlex Deucher uint16_t percentage_divider; 31119eca43eSAlex Deucher uint8_t type; 31219eca43eSAlex Deucher uint16_t step; 31319eca43eSAlex Deucher uint8_t delay; 31419eca43eSAlex Deucher uint8_t range; 31519eca43eSAlex Deucher uint8_t refdiv; 31619eca43eSAlex Deucher /* asic_ss */ 31719eca43eSAlex Deucher uint16_t rate; 31819eca43eSAlex Deucher uint16_t amount; 31919eca43eSAlex Deucher }; 32019eca43eSAlex Deucher 321a2b6d3b3SMichel Dänzer enum radeon_flip_status { 322a2b6d3b3SMichel Dänzer RADEON_FLIP_NONE, 323a2b6d3b3SMichel Dänzer RADEON_FLIP_PENDING, 324a2b6d3b3SMichel Dänzer RADEON_FLIP_SUBMITTED 325a2b6d3b3SMichel Dänzer }; 326a2b6d3b3SMichel Dänzer 327771fe6b9SJerome Glisse struct radeon_crtc { 328771fe6b9SJerome Glisse struct drm_crtc base; 329771fe6b9SJerome Glisse int crtc_id; 330771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 331771fe6b9SJerome Glisse bool enabled; 332771fe6b9SJerome Glisse bool can_tile; 333771fe6b9SJerome Glisse uint32_t crtc_offset; 334771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 335771fe6b9SJerome Glisse uint64_t cursor_addr; 33678b1a601SMichel Dänzer int cursor_x; 33778b1a601SMichel Dänzer int cursor_y; 33878b1a601SMichel Dänzer int cursor_hot_x; 33978b1a601SMichel Dänzer int cursor_hot_y; 340771fe6b9SJerome Glisse int cursor_width; 341771fe6b9SJerome Glisse int cursor_height; 3429e05fa1dSAlex Deucher int max_cursor_width; 3439e05fa1dSAlex Deucher int max_cursor_height; 3444162338aSDave Airlie uint32_t legacy_display_base_addr; 345c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3465b1714d3SAlex Deucher u8 h_border; 3475b1714d3SAlex Deucher u8 v_border; 348c93bb85bSJerome Glisse fixed20_12 vsc; 349c93bb85bSJerome Glisse fixed20_12 hsc; 350de2103e4SAlex Deucher struct drm_display_mode native_mode; 351bcc1c2a1SAlex Deucher int pll_id; 3526f34be50SAlex Deucher /* page flipping */ 353fa7f517cSChristian König struct workqueue_struct *flip_queue; 354fa7f517cSChristian König struct radeon_flip_work *flip_work; 355a2b6d3b3SMichel Dänzer enum radeon_flip_status flip_status; 35619eca43eSAlex Deucher /* pll sharing */ 35719eca43eSAlex Deucher struct radeon_atom_ss ss; 35819eca43eSAlex Deucher bool ss_enabled; 35919eca43eSAlex Deucher u32 adjusted_clock; 36019eca43eSAlex Deucher int bpc; 36119eca43eSAlex Deucher u32 pll_reference_div; 36219eca43eSAlex Deucher u32 pll_post_div; 36319eca43eSAlex Deucher u32 pll_flags; 3645df3196bSAlex Deucher struct drm_encoder *encoder; 36557b35e29SAlex Deucher struct drm_connector *connector; 3667178d2a6SAlex Deucher /* for dpm */ 3677178d2a6SAlex Deucher u32 line_time; 3687178d2a6SAlex Deucher u32 wm_low; 3697178d2a6SAlex Deucher u32 wm_high; 37066edc1c9SAlex Deucher struct drm_display_mode hw_mode; 371643b1f56SAlex Deucher enum radeon_output_csc output_csc; 372771fe6b9SJerome Glisse }; 373771fe6b9SJerome Glisse 374771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 375771fe6b9SJerome Glisse /* legacy primary dac */ 376771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 377771fe6b9SJerome Glisse }; 378771fe6b9SJerome Glisse 379771fe6b9SJerome Glisse struct radeon_encoder_lvds { 380771fe6b9SJerome Glisse /* legacy lvds */ 381771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 382771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 383771fe6b9SJerome Glisse uint8_t panel_digon_delay; 384771fe6b9SJerome Glisse uint8_t panel_blon_delay; 385771fe6b9SJerome Glisse uint16_t panel_ref_divider; 386771fe6b9SJerome Glisse uint8_t panel_post_divider; 387771fe6b9SJerome Glisse uint16_t panel_fb_divider; 388771fe6b9SJerome Glisse bool use_bios_dividers; 389771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 390771fe6b9SJerome Glisse /* panel mode */ 391de2103e4SAlex Deucher struct drm_display_mode native_mode; 39263ec0119SMichel Dänzer struct backlight_device *bl_dev; 39363ec0119SMichel Dänzer int dpms_mode; 39463ec0119SMichel Dänzer uint8_t backlight_level; 395771fe6b9SJerome Glisse }; 396771fe6b9SJerome Glisse 397771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 398771fe6b9SJerome Glisse /* legacy tv dac */ 399771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 400771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 401771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 402771fe6b9SJerome Glisse 4034ce001abSDave Airlie int h_pos; 4044ce001abSDave Airlie int v_pos; 4054ce001abSDave Airlie int h_size; 4064ce001abSDave Airlie int supported_tv_stds; 4074ce001abSDave Airlie bool tv_on; 408771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 4094ce001abSDave Airlie struct radeon_tv_regs tv; 410771fe6b9SJerome Glisse }; 411771fe6b9SJerome Glisse 412771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 413771fe6b9SJerome Glisse /* legacy int tmds */ 414771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 415771fe6b9SJerome Glisse }; 416771fe6b9SJerome Glisse 417fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 418fcec570bSAlex Deucher /* tmds over dvo */ 419fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 420fcec570bSAlex Deucher uint8_t slave_addr; 421fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 422fcec570bSAlex Deucher }; 423fcec570bSAlex Deucher 424ebbe1cb9SAlex Deucher /* spread spectrum */ 425771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 4265137ee94SAlex Deucher bool linkb; 427771fe6b9SJerome Glisse /* atom dig */ 428771fe6b9SJerome Glisse bool coherent_mode; 429ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 430ba032a58SAlex Deucher /* atom lvds/edp */ 431ba032a58SAlex Deucher uint32_t lcd_misc; 432771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 433ba032a58SAlex Deucher uint32_t lcd_ss_id; 434771fe6b9SJerome Glisse /* panel mode */ 435de2103e4SAlex Deucher struct drm_display_mode native_mode; 43663ec0119SMichel Dänzer struct backlight_device *bl_dev; 43763ec0119SMichel Dänzer int dpms_mode; 43863ec0119SMichel Dänzer uint8_t backlight_level; 439386d4d75SAlex Deucher int panel_mode; 4400783986aSAlex Deucher struct radeon_afmt *afmt; 441d0ea397eSAlex Deucher struct r600_audio_pin *pin; 4429843ead0SDave Airlie int active_mst_links; 443771fe6b9SJerome Glisse }; 444771fe6b9SJerome Glisse 4454ce001abSDave Airlie struct radeon_encoder_atom_dac { 4464ce001abSDave Airlie enum radeon_tv_std tv_std; 4474ce001abSDave Airlie }; 4484ce001abSDave Airlie 4499843ead0SDave Airlie struct radeon_encoder_mst { 4509843ead0SDave Airlie int crtc; 4519843ead0SDave Airlie struct radeon_encoder *primary; 4529843ead0SDave Airlie struct radeon_connector *connector; 4539843ead0SDave Airlie struct drm_dp_mst_port *port; 4549843ead0SDave Airlie int pbn; 4559843ead0SDave Airlie int fe; 4569843ead0SDave Airlie bool fe_from_be; 4579843ead0SDave Airlie bool enc_active; 4589843ead0SDave Airlie }; 4599843ead0SDave Airlie 460771fe6b9SJerome Glisse struct radeon_encoder { 461771fe6b9SJerome Glisse struct drm_encoder base; 4625137ee94SAlex Deucher uint32_t encoder_enum; 463771fe6b9SJerome Glisse uint32_t encoder_id; 464771fe6b9SJerome Glisse uint32_t devices; 4654ce001abSDave Airlie uint32_t active_device; 466771fe6b9SJerome Glisse uint32_t flags; 467771fe6b9SJerome Glisse uint32_t pixel_clock; 468771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4695b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4705bccf5e3SMarius Gröger uint32_t underscan_hborder; 4715bccf5e3SMarius Gröger uint32_t underscan_vborder; 472de2103e4SAlex Deucher struct drm_display_mode native_mode; 473771fe6b9SJerome Glisse void *enc_priv; 47458bd0863SChristian König int audio_polling_active; 4753e4b9982SAlex Deucher bool is_ext_encoder; 47636868bdaSAlex Deucher u16 caps; 4771a626b68SSlava Grigorev struct radeon_audio_funcs *audio; 478643b1f56SAlex Deucher enum radeon_output_csc output_csc; 4799843ead0SDave Airlie bool can_mst; 4809843ead0SDave Airlie uint32_t offset; 4819843ead0SDave Airlie bool is_mst_encoder; 4829843ead0SDave Airlie /* front end for this mst encoder */ 483771fe6b9SJerome Glisse }; 484771fe6b9SJerome Glisse 485771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 486771fe6b9SJerome Glisse uint32_t igp_lane_info; 4874143e919SAlex Deucher /* displayport */ 4881a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4894143e919SAlex Deucher u8 dp_sink_type; 4905801ead6SAlex Deucher int dp_clock; 4915801ead6SAlex Deucher int dp_lane_count; 4928b834852SAlex Deucher bool edp_on; 4939843ead0SDave Airlie bool is_mst; 494771fe6b9SJerome Glisse }; 495771fe6b9SJerome Glisse 496eed45b30SAlex Deucher struct radeon_gpio_rec { 497eed45b30SAlex Deucher bool valid; 498eed45b30SAlex Deucher u8 id; 499eed45b30SAlex Deucher u32 reg; 500eed45b30SAlex Deucher u32 mask; 501727b3d25SAlex Deucher u32 shift; 502eed45b30SAlex Deucher }; 503eed45b30SAlex Deucher 504eed45b30SAlex Deucher struct radeon_hpd { 505eed45b30SAlex Deucher enum radeon_hpd_id hpd; 506eed45b30SAlex Deucher u8 plugged_state; 507eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 508eed45b30SAlex Deucher }; 509eed45b30SAlex Deucher 51026b5bc98SAlex Deucher struct radeon_router { 51126b5bc98SAlex Deucher u32 router_id; 51226b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 51326b5bc98SAlex Deucher u8 i2c_addr; 514fb939dfcSAlex Deucher /* i2c mux */ 515fb939dfcSAlex Deucher bool ddc_valid; 516fb939dfcSAlex Deucher u8 ddc_mux_type; 517fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 518fb939dfcSAlex Deucher u8 ddc_mux_state; 519fb939dfcSAlex Deucher /* clock/data mux */ 520fb939dfcSAlex Deucher bool cd_valid; 521fb939dfcSAlex Deucher u8 cd_mux_type; 522fb939dfcSAlex Deucher u8 cd_mux_control_pin; 523fb939dfcSAlex Deucher u8 cd_mux_state; 52426b5bc98SAlex Deucher }; 52526b5bc98SAlex Deucher 5268666c076SAlex Deucher enum radeon_connector_audio { 5278666c076SAlex Deucher RADEON_AUDIO_DISABLE = 0, 5288666c076SAlex Deucher RADEON_AUDIO_ENABLE = 1, 5298666c076SAlex Deucher RADEON_AUDIO_AUTO = 2 5308666c076SAlex Deucher }; 5318666c076SAlex Deucher 5326214bb74SAlex Deucher enum radeon_connector_dither { 5336214bb74SAlex Deucher RADEON_FMT_DITHER_DISABLE = 0, 5346214bb74SAlex Deucher RADEON_FMT_DITHER_ENABLE = 1, 5356214bb74SAlex Deucher }; 5366214bb74SAlex Deucher 5379843ead0SDave Airlie struct stream_attribs { 5389843ead0SDave Airlie uint16_t fe; 5399843ead0SDave Airlie uint16_t slots; 5409843ead0SDave Airlie }; 5419843ead0SDave Airlie 542771fe6b9SJerome Glisse struct radeon_connector { 543771fe6b9SJerome Glisse struct drm_connector base; 544771fe6b9SJerome Glisse uint32_t connector_id; 545771fe6b9SJerome Glisse uint32_t devices; 546771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 5475b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 5480294cf4fSAlex Deucher bool shared_ddc; 5494ce001abSDave Airlie bool use_digital; 5504ce001abSDave Airlie /* we need to mind the EDID between detect 5514ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 5524ce001abSDave Airlie struct edid *edid; 553771fe6b9SJerome Glisse void *con_priv; 554445282dbSDave Airlie bool dac_load_detect; 555d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 556b75fad06SAlex Deucher uint16_t connector_object_id; 557eed45b30SAlex Deucher struct radeon_hpd hpd; 55826b5bc98SAlex Deucher struct radeon_router router; 55926b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 5608666c076SAlex Deucher enum radeon_connector_audio audio; 5616214bb74SAlex Deucher enum radeon_connector_dither dither; 562ea292861SMario Kleiner int pixelclock_for_modeset; 5639843ead0SDave Airlie bool is_mst_connector; 5649843ead0SDave Airlie struct radeon_connector *mst_port; 5659843ead0SDave Airlie struct drm_dp_mst_port *port; 5669843ead0SDave Airlie struct drm_dp_mst_topology_mgr mst_mgr; 5679843ead0SDave Airlie 5689843ead0SDave Airlie struct radeon_encoder *mst_encoder; 5699843ead0SDave Airlie struct stream_attribs cur_stream_attribs[6]; 5709843ead0SDave Airlie int enabled_attribs; 571771fe6b9SJerome Glisse }; 572771fe6b9SJerome Glisse 573771fe6b9SJerome Glisse struct radeon_framebuffer { 574771fe6b9SJerome Glisse struct drm_framebuffer base; 575771fe6b9SJerome Glisse struct drm_gem_object *obj; 576771fe6b9SJerome Glisse }; 577771fe6b9SJerome Glisse 578996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 579996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 5806383cf7dSMario Kleiner 5817062ab67SChristian König struct atom_clock_dividers { 5827062ab67SChristian König u32 post_div; 5837062ab67SChristian König union { 5847062ab67SChristian König struct { 5857062ab67SChristian König #ifdef __BIG_ENDIAN 5867062ab67SChristian König u32 reserved : 6; 5877062ab67SChristian König u32 whole_fb_div : 12; 5887062ab67SChristian König u32 frac_fb_div : 14; 5897062ab67SChristian König #else 5907062ab67SChristian König u32 frac_fb_div : 14; 5917062ab67SChristian König u32 whole_fb_div : 12; 5927062ab67SChristian König u32 reserved : 6; 5937062ab67SChristian König #endif 5947062ab67SChristian König }; 5957062ab67SChristian König u32 fb_div; 5967062ab67SChristian König }; 5977062ab67SChristian König u32 ref_div; 5987062ab67SChristian König bool enable_post_div; 5997062ab67SChristian König bool enable_dithen; 6007062ab67SChristian König u32 vco_mode; 6017062ab67SChristian König u32 real_clock; 6029219ed65SAlex Deucher /* added for CI */ 6039219ed65SAlex Deucher u32 post_divider; 6049219ed65SAlex Deucher u32 flags; 6057062ab67SChristian König }; 6067062ab67SChristian König 607eaa778afSAlex Deucher struct atom_mpll_param { 608eaa778afSAlex Deucher union { 609eaa778afSAlex Deucher struct { 610eaa778afSAlex Deucher #ifdef __BIG_ENDIAN 611eaa778afSAlex Deucher u32 reserved : 8; 612eaa778afSAlex Deucher u32 clkfrac : 12; 613eaa778afSAlex Deucher u32 clkf : 12; 614eaa778afSAlex Deucher #else 615eaa778afSAlex Deucher u32 clkf : 12; 616eaa778afSAlex Deucher u32 clkfrac : 12; 617eaa778afSAlex Deucher u32 reserved : 8; 618eaa778afSAlex Deucher #endif 619eaa778afSAlex Deucher }; 620eaa778afSAlex Deucher u32 fb_div; 621eaa778afSAlex Deucher }; 622eaa778afSAlex Deucher u32 post_div; 623eaa778afSAlex Deucher u32 bwcntl; 624eaa778afSAlex Deucher u32 dll_speed; 625eaa778afSAlex Deucher u32 vco_mode; 626eaa778afSAlex Deucher u32 yclk_sel; 627eaa778afSAlex Deucher u32 qdr; 628eaa778afSAlex Deucher u32 half_rate; 629eaa778afSAlex Deucher }; 630eaa778afSAlex Deucher 631ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR5 0x50 632ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR4 0x40 633ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR3 0x30 634ae5b0abbSAlex Deucher #define MEM_TYPE_DDR2 0x20 635ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR1 0x10 636ae5b0abbSAlex Deucher #define MEM_TYPE_DDR3 0xb0 637ae5b0abbSAlex Deucher #define MEM_TYPE_MASK 0xf0 638ae5b0abbSAlex Deucher 639ae5b0abbSAlex Deucher struct atom_memory_info { 640ae5b0abbSAlex Deucher u8 mem_vendor; 641ae5b0abbSAlex Deucher u8 mem_type; 642ae5b0abbSAlex Deucher }; 643ae5b0abbSAlex Deucher 644ae5b0abbSAlex Deucher #define MAX_AC_TIMING_ENTRIES 16 645ae5b0abbSAlex Deucher 646ae5b0abbSAlex Deucher struct atom_memory_clock_range_table 647ae5b0abbSAlex Deucher { 648ae5b0abbSAlex Deucher u8 num_entries; 649ae5b0abbSAlex Deucher u8 rsv[3]; 650ae5b0abbSAlex Deucher u32 mclk[MAX_AC_TIMING_ENTRIES]; 651ae5b0abbSAlex Deucher }; 652ae5b0abbSAlex Deucher 653ae5b0abbSAlex Deucher #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 654ae5b0abbSAlex Deucher #define VBIOS_MAX_AC_TIMING_ENTRIES 20 655ae5b0abbSAlex Deucher 656ae5b0abbSAlex Deucher struct atom_mc_reg_entry { 657ae5b0abbSAlex Deucher u32 mclk_max; 658ae5b0abbSAlex Deucher u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 659ae5b0abbSAlex Deucher }; 660ae5b0abbSAlex Deucher 661ae5b0abbSAlex Deucher struct atom_mc_register_address { 662ae5b0abbSAlex Deucher u16 s1; 663ae5b0abbSAlex Deucher u8 pre_reg_data; 664ae5b0abbSAlex Deucher }; 665ae5b0abbSAlex Deucher 666ae5b0abbSAlex Deucher struct atom_mc_reg_table { 667ae5b0abbSAlex Deucher u8 last; 668ae5b0abbSAlex Deucher u8 num_entries; 669ae5b0abbSAlex Deucher struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 670ae5b0abbSAlex Deucher struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 671ae5b0abbSAlex Deucher }; 672ae5b0abbSAlex Deucher 673ae5b0abbSAlex Deucher #define MAX_VOLTAGE_ENTRIES 32 674ae5b0abbSAlex Deucher 675ae5b0abbSAlex Deucher struct atom_voltage_table_entry 676ae5b0abbSAlex Deucher { 677ae5b0abbSAlex Deucher u16 value; 678ae5b0abbSAlex Deucher u32 smio_low; 679ae5b0abbSAlex Deucher }; 680ae5b0abbSAlex Deucher 681ae5b0abbSAlex Deucher struct atom_voltage_table 682ae5b0abbSAlex Deucher { 683ae5b0abbSAlex Deucher u32 count; 684ae5b0abbSAlex Deucher u32 mask_low; 68565171944SAlex Deucher u32 phase_delay; 686ae5b0abbSAlex Deucher struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 687ae5b0abbSAlex Deucher }; 688ae5b0abbSAlex Deucher 689a38eab52SRashika Kheria 690a38eab52SRashika Kheria extern void 691a38eab52SRashika Kheria radeon_add_atom_connector(struct drm_device *dev, 692a38eab52SRashika Kheria uint32_t connector_id, 693a38eab52SRashika Kheria uint32_t supported_device, 694a38eab52SRashika Kheria int connector_type, 695a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 696a38eab52SRashika Kheria uint32_t igp_lane_info, 697a38eab52SRashika Kheria uint16_t connector_object_id, 698a38eab52SRashika Kheria struct radeon_hpd *hpd, 699a38eab52SRashika Kheria struct radeon_router *router); 700a38eab52SRashika Kheria extern void 701a38eab52SRashika Kheria radeon_add_legacy_connector(struct drm_device *dev, 702a38eab52SRashika Kheria uint32_t connector_id, 703a38eab52SRashika Kheria uint32_t supported_device, 704a38eab52SRashika Kheria int connector_type, 705a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 706a38eab52SRashika Kheria uint16_t connector_object_id, 707a38eab52SRashika Kheria struct radeon_hpd *hpd); 7080091fc13SRashika Kheria extern uint32_t 7090091fc13SRashika Kheria radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 7100091fc13SRashika Kheria uint8_t dac); 7110091fc13SRashika Kheria extern void radeon_link_encoder_connector(struct drm_device *dev); 712a38eab52SRashika Kheria 713d79766faSAlex Deucher extern enum radeon_tv_std 714d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 715d79766faSAlex Deucher extern enum radeon_tv_std 716d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 7174a6369e9SAlex Deucher extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 7182abba66eSAlex Deucher u16 *vddc, u16 *vddci, u16 *mvdd); 719d79766faSAlex Deucher 72084ac68e0SAlex Deucher extern void 72184ac68e0SAlex Deucher radeon_combios_connected_scratch_regs(struct drm_connector *connector, 72284ac68e0SAlex Deucher struct drm_encoder *encoder, 72384ac68e0SAlex Deucher bool connected); 72484ac68e0SAlex Deucher extern void 72584ac68e0SAlex Deucher radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 72684ac68e0SAlex Deucher struct drm_encoder *encoder, 72784ac68e0SAlex Deucher bool connected); 72884ac68e0SAlex Deucher 7295b1714d3SAlex Deucher extern struct drm_connector * 7305b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 7319aa59993SAlex Deucher extern struct drm_connector * 7329aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 7339aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 7349aa59993SAlex Deucher u32 pixel_clock); 7355b1714d3SAlex Deucher 7361d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 7371d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 738d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 739eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 740d7fa8bb3SAlex Deucher 741377bd8a9SAlex Deucher extern struct edid *radeon_connector_edid(struct drm_connector *connector); 742377bd8a9SAlex Deucher 743d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 744224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 7455801ead6SAlex Deucher struct drm_display_mode *mode); 7465801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 747e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 748224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 7495801ead6SAlex Deucher struct drm_connector *connector); 750d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 7514143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 7529fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 753386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 754386d4d75SAlex Deucher struct drm_connector *connector); 7552be123d7SDave Airlie int radeon_dp_get_max_link_rate(struct drm_connector *connector, 7560c3a8840SAlex Deucher const u8 *dpcd); 7572953da15SAlex Deucher extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 7582953da15SAlex Deucher u8 power_state); 759496263bfSAlex Deucher extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 760875711f0SDave Airlie extern ssize_t 761875711f0SDave Airlie radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 762875711f0SDave Airlie 763558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 764bf071900SDave Airlie extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 765ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 766f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 7675801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 7685801ead6SAlex Deucher int action, uint8_t lane_num, 7695801ead6SAlex Deucher uint8_t lane_set); 770bf071900SDave Airlie extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 771bf071900SDave Airlie int action, uint8_t lane_num, 772bf071900SDave Airlie uint8_t lane_set, int fe); 7739843ead0SDave Airlie extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, 7749843ead0SDave Airlie int fe); 775591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 7763f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 7774cf3b494SRashika Kheria void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 778746c1aa4SDave Airlie 779f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 780f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 781f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 782f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 783f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 784f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 785f376b94fSAlex Deucher const char *name); 786f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 787f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 788771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 789771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 790771fe6b9SJerome Glisse const char *name); 791771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 7925a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 793fcec570bSAlex Deucher u8 slave_addr, 794fcec570bSAlex Deucher u8 addr, 795fcec570bSAlex Deucher u8 *val); 7965a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 797fcec570bSAlex Deucher u8 slave_addr, 798fcec570bSAlex Deucher u8 addr, 799fcec570bSAlex Deucher u8 val); 800fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 801fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 8020a9069d3SNiels Ole Salscheider extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 803771fe6b9SJerome Glisse 804ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 805ba032a58SAlex Deucher struct radeon_atom_ss *ss, 806ba032a58SAlex Deucher int id); 807ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 808ba032a58SAlex Deucher struct radeon_atom_ss *ss, 809ba032a58SAlex Deucher int id, u32 clock); 81009e619c0SAlex Deucher extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 81109e619c0SAlex Deucher u8 id); 812ba032a58SAlex Deucher 813f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 814771fe6b9SJerome Glisse uint64_t freq, 815771fe6b9SJerome Glisse uint32_t *dot_clock_p, 816771fe6b9SJerome Glisse uint32_t *fb_div_p, 817771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 818771fe6b9SJerome Glisse uint32_t *ref_div_p, 819fc10332bSAlex Deucher uint32_t *post_div_p); 820771fe6b9SJerome Glisse 821f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 822f523f74eSAlex Deucher u32 freq, 823f523f74eSAlex Deucher u32 *dot_clock_p, 824f523f74eSAlex Deucher u32 *fb_div_p, 825f523f74eSAlex Deucher u32 *frac_fb_div_p, 826f523f74eSAlex Deucher u32 *ref_div_p, 827f523f74eSAlex Deucher u32 *post_div_p); 828f523f74eSAlex Deucher 8291f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 8301f3b6a45SDave Airlie 831771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 832771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 833771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 834771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 835771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 83699999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 83732f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 838771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 8392dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 8404ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 841d740a933SAlex Deucher extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 842771fe6b9SJerome Glisse 843771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 844771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 845771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8464dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 8474dd19b0dSChris Ball struct drm_framebuffer *fb, 84821c74a8eSJason Wessel int x, int y, 84921c74a8eSJason Wessel enum mode_set_atomic state); 850771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 851771fe6b9SJerome Glisse struct drm_display_mode *mode, 852771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 853771fe6b9SJerome Glisse int x, int y, 854771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 855771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 856771fe6b9SJerome Glisse 857771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 858771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8594dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 8604dd19b0dSChris Ball struct drm_framebuffer *fb, 86121c74a8eSJason Wessel int x, int y, 86221c74a8eSJason Wessel enum mode_set_atomic state); 8634dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 8644dd19b0dSChris Ball struct drm_framebuffer *fb, 8654dd19b0dSChris Ball int x, int y, int atomic); 86678b1a601SMichel Dänzer extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 867771fe6b9SJerome Glisse struct drm_file *file_priv, 868771fe6b9SJerome Glisse uint32_t handle, 869771fe6b9SJerome Glisse uint32_t width, 87078b1a601SMichel Dänzer uint32_t height, 87178b1a601SMichel Dänzer int32_t hot_x, 87278b1a601SMichel Dänzer int32_t hot_y); 873771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 874771fe6b9SJerome Glisse int x, int y); 8756d3759faSMichel Dänzer extern void radeon_cursor_reset(struct drm_crtc *crtc); 876771fe6b9SJerome Glisse 877f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 878abca9e45SVille Syrjälä unsigned int flags, 8793bb403bfSVille Syrjälä int *vpos, int *hpos, 8803bb403bfSVille Syrjälä ktime_t *stime, ktime_t *etime, 8813bb403bfSVille Syrjälä const struct drm_display_mode *mode); 8826383cf7dSMario Kleiner 8833c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 8843c537889SAlex Deucher extern struct edid * 885c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 886771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 887771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 888771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 889771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 890fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 891445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 892fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 893445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 894fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 895445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 896fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 897fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 898fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 899fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 9006fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 9016fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 9026fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 9036fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 904771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 905771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 906771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 907771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 908771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 909771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 910771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 911fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 912fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 913771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 914771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 915771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 916771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 917f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 918f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 919771fe6b9SJerome Glisse extern void 920771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 921771fe6b9SJerome Glisse extern void 922771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 923771fe6b9SJerome Glisse extern void 924771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 925771fe6b9SJerome Glisse extern void 926771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 927771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 928771fe6b9SJerome Glisse u16 blue, int regno); 929b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 930b8c00ac5SDave Airlie u16 *blue, int regno); 931aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 93238651674SDave Airlie struct radeon_framebuffer *rfb, 933308e5bcbSJesse Barnes struct drm_mode_fb_cmd2 *mode_cmd, 934771fe6b9SJerome Glisse struct drm_gem_object *obj); 935771fe6b9SJerome Glisse 936771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 937771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 938771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 939771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 940771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 941771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 942771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 943771fe6b9SJerome Glisse 944771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 945771fe6b9SJerome Glisse 946771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 947771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 948771fe6b9SJerome Glisse 949771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 950771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 951771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 952c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 953e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 954c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 9553515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 9563515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 9574ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 958771fe6b9SJerome Glisse 9594ce001abSDave Airlie /* legacy tv */ 9604ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 9614ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 9624ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 9634ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 9644ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 9654ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 9664ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 9674ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 9684ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 9694ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 9704ce001abSDave Airlie struct drm_display_mode *mode, 9714ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 97238651674SDave Airlie 973134b480fSAlex Deucher /* fmt blocks */ 974134b480fSAlex Deucher void avivo_program_fmt(struct drm_encoder *encoder); 975134b480fSAlex Deucher void dce3_program_fmt(struct drm_encoder *encoder); 976134b480fSAlex Deucher void dce4_program_fmt(struct drm_encoder *encoder); 977134b480fSAlex Deucher void dce8_program_fmt(struct drm_encoder *encoder); 978134b480fSAlex Deucher 97938651674SDave Airlie /* fbdev layer */ 98038651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 98138651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 98238651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 98338651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 984eb1f8e4fSDave Airlie 985eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 9866f34be50SAlex Deucher 9871a0e7918SChristian König void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 988bb26270eSDave Airlie 989bb26270eSDave Airlie void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); 990bb26270eSDave Airlie void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); 991bb26270eSDave Airlie 9926f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 9936f34be50SAlex Deucher 994ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 9958f0fc088SDave Airlie 9969843ead0SDave Airlie /* mst */ 9979843ead0SDave Airlie int radeon_dp_mst_init(struct radeon_connector *radeon_connector); 9989843ead0SDave Airlie int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); 9999843ead0SDave Airlie int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); 10009843ead0SDave Airlie int radeon_mst_debugfs_init(struct radeon_device *rdev); 10019843ead0SDave Airlie void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); 10029843ead0SDave Airlie 10039843ead0SDave Airlie void radeon_setup_mst_connector(struct drm_device *dev); 10049843ead0SDave Airlie 10058f0fc088SDave Airlie int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 10068f0fc088SDave Airlie void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 1007771fe6b9SJerome Glisse #endif 1008