1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36771fe6b9SJerome Glisse #include <linux/i2c.h> 37771fe6b9SJerome Glisse #include <linux/i2c-id.h> 38771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 39c93bb85bSJerome Glisse #include "radeon_fixed.h" 40c93bb85bSJerome Glisse 41c93bb85bSJerome Glisse struct radeon_device; 42771fe6b9SJerome Glisse 43771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 44771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 45771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 46771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 47771fe6b9SJerome Glisse 48771fe6b9SJerome Glisse enum radeon_connector_type { 49771fe6b9SJerome Glisse CONNECTOR_NONE, 50771fe6b9SJerome Glisse CONNECTOR_VGA, 51771fe6b9SJerome Glisse CONNECTOR_DVI_I, 52771fe6b9SJerome Glisse CONNECTOR_DVI_D, 53771fe6b9SJerome Glisse CONNECTOR_DVI_A, 54771fe6b9SJerome Glisse CONNECTOR_STV, 55771fe6b9SJerome Glisse CONNECTOR_CTV, 56771fe6b9SJerome Glisse CONNECTOR_LVDS, 57771fe6b9SJerome Glisse CONNECTOR_DIGITAL, 58771fe6b9SJerome Glisse CONNECTOR_SCART, 59771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_A, 60771fe6b9SJerome Glisse CONNECTOR_HDMI_TYPE_B, 61771fe6b9SJerome Glisse CONNECTOR_0XC, 62771fe6b9SJerome Glisse CONNECTOR_0XD, 63771fe6b9SJerome Glisse CONNECTOR_DIN, 64771fe6b9SJerome Glisse CONNECTOR_DISPLAY_PORT, 65771fe6b9SJerome Glisse CONNECTOR_UNSUPPORTED 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 68771fe6b9SJerome Glisse enum radeon_dvi_type { 69771fe6b9SJerome Glisse DVI_AUTO, 70771fe6b9SJerome Glisse DVI_DIGITAL, 71771fe6b9SJerome Glisse DVI_ANALOG 72771fe6b9SJerome Glisse }; 73771fe6b9SJerome Glisse 74771fe6b9SJerome Glisse enum radeon_rmx_type { 75771fe6b9SJerome Glisse RMX_OFF, 76771fe6b9SJerome Glisse RMX_FULL, 77771fe6b9SJerome Glisse RMX_CENTER, 78771fe6b9SJerome Glisse RMX_ASPECT 79771fe6b9SJerome Glisse }; 80771fe6b9SJerome Glisse 81771fe6b9SJerome Glisse enum radeon_tv_std { 82771fe6b9SJerome Glisse TV_STD_NTSC, 83771fe6b9SJerome Glisse TV_STD_PAL, 84771fe6b9SJerome Glisse TV_STD_PAL_M, 85771fe6b9SJerome Glisse TV_STD_PAL_60, 86771fe6b9SJerome Glisse TV_STD_NTSC_J, 87771fe6b9SJerome Glisse TV_STD_SCART_PAL, 88771fe6b9SJerome Glisse TV_STD_SECAM, 89771fe6b9SJerome Glisse TV_STD_PAL_CN, 90771fe6b9SJerome Glisse }; 91771fe6b9SJerome Glisse 929b9fe724SAlex Deucher /* radeon gpio-based i2c 939b9fe724SAlex Deucher * 1. "mask" reg and bits 949b9fe724SAlex Deucher * grabs the gpio pins for software use 959b9fe724SAlex Deucher * 0=not held 1=held 969b9fe724SAlex Deucher * 2. "a" reg and bits 979b9fe724SAlex Deucher * output pin value 989b9fe724SAlex Deucher * 0=low 1=high 999b9fe724SAlex Deucher * 3. "en" reg and bits 1009b9fe724SAlex Deucher * sets the pin direction 1019b9fe724SAlex Deucher * 0=input 1=output 1029b9fe724SAlex Deucher * 4. "y" reg and bits 1039b9fe724SAlex Deucher * input pin value 1049b9fe724SAlex Deucher * 0=low 1=high 1059b9fe724SAlex Deucher */ 106771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 107771fe6b9SJerome Glisse bool valid; 108771fe6b9SJerome Glisse uint32_t mask_clk_reg; 109771fe6b9SJerome Glisse uint32_t mask_data_reg; 110771fe6b9SJerome Glisse uint32_t a_clk_reg; 111771fe6b9SJerome Glisse uint32_t a_data_reg; 1129b9fe724SAlex Deucher uint32_t en_clk_reg; 1139b9fe724SAlex Deucher uint32_t en_data_reg; 1149b9fe724SAlex Deucher uint32_t y_clk_reg; 1159b9fe724SAlex Deucher uint32_t y_data_reg; 116771fe6b9SJerome Glisse uint32_t mask_clk_mask; 117771fe6b9SJerome Glisse uint32_t mask_data_mask; 118771fe6b9SJerome Glisse uint32_t a_clk_mask; 119771fe6b9SJerome Glisse uint32_t a_data_mask; 1209b9fe724SAlex Deucher uint32_t en_clk_mask; 1219b9fe724SAlex Deucher uint32_t en_data_mask; 1229b9fe724SAlex Deucher uint32_t y_clk_mask; 1239b9fe724SAlex Deucher uint32_t y_data_mask; 124771fe6b9SJerome Glisse }; 125771fe6b9SJerome Glisse 126771fe6b9SJerome Glisse struct radeon_tmds_pll { 127771fe6b9SJerome Glisse uint32_t freq; 128771fe6b9SJerome Glisse uint32_t value; 129771fe6b9SJerome Glisse }; 130771fe6b9SJerome Glisse 131771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 132771fe6b9SJerome Glisse 133771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 134771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 135771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 136771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 137771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 138771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 139771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 140771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 141771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 143771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 144d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 145771fe6b9SJerome Glisse 146771fe6b9SJerome Glisse struct radeon_pll { 147771fe6b9SJerome Glisse uint16_t reference_freq; 148771fe6b9SJerome Glisse uint16_t reference_div; 149771fe6b9SJerome Glisse uint32_t pll_in_min; 150771fe6b9SJerome Glisse uint32_t pll_in_max; 151771fe6b9SJerome Glisse uint32_t pll_out_min; 152771fe6b9SJerome Glisse uint32_t pll_out_max; 153771fe6b9SJerome Glisse uint16_t xclk; 154771fe6b9SJerome Glisse 155771fe6b9SJerome Glisse uint32_t min_ref_div; 156771fe6b9SJerome Glisse uint32_t max_ref_div; 157771fe6b9SJerome Glisse uint32_t min_post_div; 158771fe6b9SJerome Glisse uint32_t max_post_div; 159771fe6b9SJerome Glisse uint32_t min_feedback_div; 160771fe6b9SJerome Glisse uint32_t max_feedback_div; 161771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 162771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 163771fe6b9SJerome Glisse uint32_t best_vco; 164771fe6b9SJerome Glisse }; 165771fe6b9SJerome Glisse 166771fe6b9SJerome Glisse struct radeon_i2c_chan { 167771fe6b9SJerome Glisse struct drm_device *dev; 168771fe6b9SJerome Glisse struct i2c_adapter adapter; 169771fe6b9SJerome Glisse struct i2c_algo_bit_data algo; 170771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 171771fe6b9SJerome Glisse }; 172771fe6b9SJerome Glisse 173771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 174771fe6b9SJerome Glisse enum radeon_connector_table { 175771fe6b9SJerome Glisse CT_NONE, 176771fe6b9SJerome Glisse CT_GENERIC, 177771fe6b9SJerome Glisse CT_IBOOK, 178771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 179771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 180771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 181771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 182771fe6b9SJerome Glisse CT_MINI_INTERNAL, 183771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 184771fe6b9SJerome Glisse CT_EMAC, 185771fe6b9SJerome Glisse }; 186771fe6b9SJerome Glisse 187fcec570bSAlex Deucher enum radeon_dvo_chip { 188fcec570bSAlex Deucher DVO_SIL164, 189fcec570bSAlex Deucher DVO_SIL1178, 190fcec570bSAlex Deucher }; 191fcec570bSAlex Deucher 192771fe6b9SJerome Glisse struct radeon_mode_info { 193771fe6b9SJerome Glisse struct atom_context *atom_context; 19461c4b24bSMathias Fröhlich struct card_info *atom_card_info; 195771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 196771fe6b9SJerome Glisse bool mode_config_initialized; 197c93bb85bSJerome Glisse struct radeon_crtc *crtcs[2]; 198445282dbSDave Airlie /* DVI-I properties */ 199445282dbSDave Airlie struct drm_property *coherent_mode_property; 200445282dbSDave Airlie /* DAC enable load detect */ 201445282dbSDave Airlie struct drm_property *load_detect_property; 202445282dbSDave Airlie /* TV standard load detect */ 203445282dbSDave Airlie struct drm_property *tv_std_property; 204445282dbSDave Airlie /* legacy TMDS PLL detect */ 205445282dbSDave Airlie struct drm_property *tmds_pll_property; 206445282dbSDave Airlie 207c93bb85bSJerome Glisse }; 208c93bb85bSJerome Glisse 2094ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2104ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2114ce001abSDave Airlie 2124ce001abSDave Airlie /* need to store these as reading 2134ce001abSDave Airlie back code tables is excessive */ 2144ce001abSDave Airlie struct radeon_tv_regs { 2154ce001abSDave Airlie uint32_t tv_uv_adr; 2164ce001abSDave Airlie uint32_t timing_cntl; 2174ce001abSDave Airlie uint32_t hrestart; 2184ce001abSDave Airlie uint32_t vrestart; 2194ce001abSDave Airlie uint32_t frestart; 2204ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2214ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2224ce001abSDave Airlie }; 2234ce001abSDave Airlie 224771fe6b9SJerome Glisse struct radeon_crtc { 225771fe6b9SJerome Glisse struct drm_crtc base; 226771fe6b9SJerome Glisse int crtc_id; 227771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 228771fe6b9SJerome Glisse bool enabled; 229771fe6b9SJerome Glisse bool can_tile; 230771fe6b9SJerome Glisse uint32_t crtc_offset; 231771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 232771fe6b9SJerome Glisse uint64_t cursor_addr; 233771fe6b9SJerome Glisse int cursor_width; 234771fe6b9SJerome Glisse int cursor_height; 2354162338aSDave Airlie uint32_t legacy_display_base_addr; 236c836e862SAlex Deucher uint32_t legacy_cursor_offset; 237c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 238c93bb85bSJerome Glisse fixed20_12 vsc; 239c93bb85bSJerome Glisse fixed20_12 hsc; 240de2103e4SAlex Deucher struct drm_display_mode native_mode; 241771fe6b9SJerome Glisse }; 242771fe6b9SJerome Glisse 243771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 244771fe6b9SJerome Glisse /* legacy primary dac */ 245771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 246771fe6b9SJerome Glisse }; 247771fe6b9SJerome Glisse 248771fe6b9SJerome Glisse struct radeon_encoder_lvds { 249771fe6b9SJerome Glisse /* legacy lvds */ 250771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 251771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 252771fe6b9SJerome Glisse uint8_t panel_digon_delay; 253771fe6b9SJerome Glisse uint8_t panel_blon_delay; 254771fe6b9SJerome Glisse uint16_t panel_ref_divider; 255771fe6b9SJerome Glisse uint8_t panel_post_divider; 256771fe6b9SJerome Glisse uint16_t panel_fb_divider; 257771fe6b9SJerome Glisse bool use_bios_dividers; 258771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 259771fe6b9SJerome Glisse /* panel mode */ 260de2103e4SAlex Deucher struct drm_display_mode native_mode; 261771fe6b9SJerome Glisse }; 262771fe6b9SJerome Glisse 263771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 264771fe6b9SJerome Glisse /* legacy tv dac */ 265771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 266771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 267771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 268771fe6b9SJerome Glisse 2694ce001abSDave Airlie int h_pos; 2704ce001abSDave Airlie int v_pos; 2714ce001abSDave Airlie int h_size; 2724ce001abSDave Airlie int supported_tv_stds; 2734ce001abSDave Airlie bool tv_on; 274771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 2754ce001abSDave Airlie struct radeon_tv_regs tv; 276771fe6b9SJerome Glisse }; 277771fe6b9SJerome Glisse 278771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 279771fe6b9SJerome Glisse /* legacy int tmds */ 280771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 281771fe6b9SJerome Glisse }; 282771fe6b9SJerome Glisse 283fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 284fcec570bSAlex Deucher /* tmds over dvo */ 285fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 286fcec570bSAlex Deucher uint8_t slave_addr; 287fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 288fcec570bSAlex Deucher }; 289fcec570bSAlex Deucher 290ebbe1cb9SAlex Deucher /* spread spectrum */ 291ebbe1cb9SAlex Deucher struct radeon_atom_ss { 292ebbe1cb9SAlex Deucher uint16_t percentage; 293ebbe1cb9SAlex Deucher uint8_t type; 294ebbe1cb9SAlex Deucher uint8_t step; 295ebbe1cb9SAlex Deucher uint8_t delay; 296ebbe1cb9SAlex Deucher uint8_t range; 297ebbe1cb9SAlex Deucher uint8_t refdiv; 298ebbe1cb9SAlex Deucher }; 299ebbe1cb9SAlex Deucher 300771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 301771fe6b9SJerome Glisse /* atom dig */ 302771fe6b9SJerome Glisse bool coherent_mode; 303771fe6b9SJerome Glisse int dig_block; 304771fe6b9SJerome Glisse /* atom lvds */ 305771fe6b9SJerome Glisse uint32_t lvds_misc; 306771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 307ebbe1cb9SAlex Deucher struct radeon_atom_ss *ss; 308771fe6b9SJerome Glisse /* panel mode */ 309de2103e4SAlex Deucher struct drm_display_mode native_mode; 310771fe6b9SJerome Glisse }; 311771fe6b9SJerome Glisse 3124ce001abSDave Airlie struct radeon_encoder_atom_dac { 3134ce001abSDave Airlie enum radeon_tv_std tv_std; 3144ce001abSDave Airlie }; 3154ce001abSDave Airlie 316771fe6b9SJerome Glisse struct radeon_encoder { 317771fe6b9SJerome Glisse struct drm_encoder base; 318771fe6b9SJerome Glisse uint32_t encoder_id; 319771fe6b9SJerome Glisse uint32_t devices; 3204ce001abSDave Airlie uint32_t active_device; 321771fe6b9SJerome Glisse uint32_t flags; 322771fe6b9SJerome Glisse uint32_t pixel_clock; 323771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 324de2103e4SAlex Deucher struct drm_display_mode native_mode; 325771fe6b9SJerome Glisse void *enc_priv; 326771fe6b9SJerome Glisse }; 327771fe6b9SJerome Glisse 328771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 329771fe6b9SJerome Glisse uint32_t igp_lane_info; 330771fe6b9SJerome Glisse bool linkb; 331771fe6b9SJerome Glisse }; 332771fe6b9SJerome Glisse 333771fe6b9SJerome Glisse struct radeon_connector { 334771fe6b9SJerome Glisse struct drm_connector base; 335771fe6b9SJerome Glisse uint32_t connector_id; 336771fe6b9SJerome Glisse uint32_t devices; 337771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 3380294cf4fSAlex Deucher /* some systems have a an hdmi and vga port with a shared ddc line */ 3390294cf4fSAlex Deucher bool shared_ddc; 3404ce001abSDave Airlie bool use_digital; 3414ce001abSDave Airlie /* we need to mind the EDID between detect 3424ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 3434ce001abSDave Airlie struct edid *edid; 344771fe6b9SJerome Glisse void *con_priv; 345445282dbSDave Airlie bool dac_load_detect; 346b75fad06SAlex Deucher uint16_t connector_object_id; 347771fe6b9SJerome Glisse }; 348771fe6b9SJerome Glisse 349771fe6b9SJerome Glisse struct radeon_framebuffer { 350771fe6b9SJerome Glisse struct drm_framebuffer base; 351771fe6b9SJerome Glisse struct drm_gem_object *obj; 352771fe6b9SJerome Glisse }; 353771fe6b9SJerome Glisse 354771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 355771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 356771fe6b9SJerome Glisse const char *name); 357771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 358fcec570bSAlex Deucher extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, 359fcec570bSAlex Deucher u8 slave_addr, 360fcec570bSAlex Deucher u8 addr, 361fcec570bSAlex Deucher u8 *val); 362fcec570bSAlex Deucher extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c, 363fcec570bSAlex Deucher u8 slave_addr, 364fcec570bSAlex Deucher u8 addr, 365fcec570bSAlex Deucher u8 val); 366771fe6b9SJerome Glisse extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 367771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 368771fe6b9SJerome Glisse 369771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 370771fe6b9SJerome Glisse 371771fe6b9SJerome Glisse extern void radeon_compute_pll(struct radeon_pll *pll, 372771fe6b9SJerome Glisse uint64_t freq, 373771fe6b9SJerome Glisse uint32_t *dot_clock_p, 374771fe6b9SJerome Glisse uint32_t *fb_div_p, 375771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 376771fe6b9SJerome Glisse uint32_t *ref_div_p, 377771fe6b9SJerome Glisse uint32_t *post_div_p, 378771fe6b9SJerome Glisse int flags); 379771fe6b9SJerome Glisse 3801f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 3811f3b6a45SDave Airlie 382771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 383771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 384771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 385771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 386771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 387771fe6b9SJerome Glisse extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); 388771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 3894ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 390771fe6b9SJerome Glisse 391771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 392771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 393771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 394771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 395771fe6b9SJerome Glisse struct drm_display_mode *mode, 396771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 397771fe6b9SJerome Glisse int x, int y, 398771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 399771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 400771fe6b9SJerome Glisse 401771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 402771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 403771fe6b9SJerome Glisse extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); 404771fe6b9SJerome Glisse 405771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 406771fe6b9SJerome Glisse struct drm_file *file_priv, 407771fe6b9SJerome Glisse uint32_t handle, 408771fe6b9SJerome Glisse uint32_t width, 409771fe6b9SJerome Glisse uint32_t height); 410771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 411771fe6b9SJerome Glisse int x, int y); 412771fe6b9SJerome Glisse 413771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 414771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 415771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 416771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 417fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 418445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 419fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 420445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 421fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 422445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 423fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 424fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 425fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 426fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 4276fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 4286fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 4296fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 4306fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 431771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 432771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 433771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 434771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 435771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 436771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 437771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 438fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 439fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 440771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 441771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 442771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 443771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 444f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 445f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 446771fe6b9SJerome Glisse extern void 447771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 448771fe6b9SJerome Glisse extern void 449771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 450771fe6b9SJerome Glisse extern void 451771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 452771fe6b9SJerome Glisse extern void 453771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 454771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 455771fe6b9SJerome Glisse u16 blue, int regno); 456b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 457b8c00ac5SDave Airlie u16 *blue, int regno); 458771fe6b9SJerome Glisse struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, 459771fe6b9SJerome Glisse struct drm_mode_fb_cmd *mode_cmd, 460771fe6b9SJerome Glisse struct drm_gem_object *obj); 461771fe6b9SJerome Glisse 462771fe6b9SJerome Glisse int radeonfb_probe(struct drm_device *dev); 463771fe6b9SJerome Glisse 464771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 465771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 466771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 467771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 468771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 469771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 470771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 471ab1e9ea0SAlex Deucher extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state); 472771fe6b9SJerome Glisse 473771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 474771fe6b9SJerome Glisse 475771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 476771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 477771fe6b9SJerome Glisse 478771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 479771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 480771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 481771fe6b9SJerome Glisse extern int radeon_static_clocks_init(struct drm_device *dev); 482c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 483c93bb85bSJerome Glisse struct drm_display_mode *mode, 484c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 4854ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 486771fe6b9SJerome Glisse 4874ce001abSDave Airlie /* legacy tv */ 4884ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 4894ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 4904ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 4914ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 4924ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 4934ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 4944ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 4954ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 4964ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 4974ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 4984ce001abSDave Airlie struct drm_display_mode *mode, 4994ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 500771fe6b9SJerome Glisse #endif 501