1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33760285e7SDavid Howells #include <drm/drm_crtc.h> 34760285e7SDavid Howells #include <drm/drm_edid.h> 35760285e7SDavid Howells #include <drm/drm_dp_helper.h> 36760285e7SDavid Howells #include <drm/drm_fixed.h> 37760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 38771fe6b9SJerome Glisse #include <linux/i2c.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse 4138651674SDave Airlie struct radeon_bo; 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 49771fe6b9SJerome Glisse enum radeon_rmx_type { 50771fe6b9SJerome Glisse RMX_OFF, 51771fe6b9SJerome Glisse RMX_FULL, 52771fe6b9SJerome Glisse RMX_CENTER, 53771fe6b9SJerome Glisse RMX_ASPECT 54771fe6b9SJerome Glisse }; 55771fe6b9SJerome Glisse 56771fe6b9SJerome Glisse enum radeon_tv_std { 57771fe6b9SJerome Glisse TV_STD_NTSC, 58771fe6b9SJerome Glisse TV_STD_PAL, 59771fe6b9SJerome Glisse TV_STD_PAL_M, 60771fe6b9SJerome Glisse TV_STD_PAL_60, 61771fe6b9SJerome Glisse TV_STD_NTSC_J, 62771fe6b9SJerome Glisse TV_STD_SCART_PAL, 63771fe6b9SJerome Glisse TV_STD_SECAM, 64771fe6b9SJerome Glisse TV_STD_PAL_CN, 65d79766faSAlex Deucher TV_STD_PAL_N, 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 685b1714d3SAlex Deucher enum radeon_underscan_type { 695b1714d3SAlex Deucher UNDERSCAN_OFF, 705b1714d3SAlex Deucher UNDERSCAN_ON, 715b1714d3SAlex Deucher UNDERSCAN_AUTO, 725b1714d3SAlex Deucher }; 735b1714d3SAlex Deucher 748e36ed00SAlex Deucher enum radeon_hpd_id { 758e36ed00SAlex Deucher RADEON_HPD_1 = 0, 768e36ed00SAlex Deucher RADEON_HPD_2, 778e36ed00SAlex Deucher RADEON_HPD_3, 788e36ed00SAlex Deucher RADEON_HPD_4, 798e36ed00SAlex Deucher RADEON_HPD_5, 808e36ed00SAlex Deucher RADEON_HPD_6, 818e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 828e36ed00SAlex Deucher }; 838e36ed00SAlex Deucher 84f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 85f376b94fSAlex Deucher 869b9fe724SAlex Deucher /* radeon gpio-based i2c 879b9fe724SAlex Deucher * 1. "mask" reg and bits 889b9fe724SAlex Deucher * grabs the gpio pins for software use 899b9fe724SAlex Deucher * 0=not held 1=held 909b9fe724SAlex Deucher * 2. "a" reg and bits 919b9fe724SAlex Deucher * output pin value 929b9fe724SAlex Deucher * 0=low 1=high 939b9fe724SAlex Deucher * 3. "en" reg and bits 949b9fe724SAlex Deucher * sets the pin direction 959b9fe724SAlex Deucher * 0=input 1=output 969b9fe724SAlex Deucher * 4. "y" reg and bits 979b9fe724SAlex Deucher * input pin value 989b9fe724SAlex Deucher * 0=low 1=high 999b9fe724SAlex Deucher */ 100771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 101771fe6b9SJerome Glisse bool valid; 1026a93cb25SAlex Deucher /* id used by atom */ 1036a93cb25SAlex Deucher uint8_t i2c_id; 104bcc1c2a1SAlex Deucher /* id used by atom */ 1058e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1066a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1076a93cb25SAlex Deucher bool hw_capable; 1086a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1096a93cb25SAlex Deucher bool mm_i2c; 1106a93cb25SAlex Deucher /* regs and bits */ 111771fe6b9SJerome Glisse uint32_t mask_clk_reg; 112771fe6b9SJerome Glisse uint32_t mask_data_reg; 113771fe6b9SJerome Glisse uint32_t a_clk_reg; 114771fe6b9SJerome Glisse uint32_t a_data_reg; 1159b9fe724SAlex Deucher uint32_t en_clk_reg; 1169b9fe724SAlex Deucher uint32_t en_data_reg; 1179b9fe724SAlex Deucher uint32_t y_clk_reg; 1189b9fe724SAlex Deucher uint32_t y_data_reg; 119771fe6b9SJerome Glisse uint32_t mask_clk_mask; 120771fe6b9SJerome Glisse uint32_t mask_data_mask; 121771fe6b9SJerome Glisse uint32_t a_clk_mask; 122771fe6b9SJerome Glisse uint32_t a_data_mask; 1239b9fe724SAlex Deucher uint32_t en_clk_mask; 1249b9fe724SAlex Deucher uint32_t en_data_mask; 1259b9fe724SAlex Deucher uint32_t y_clk_mask; 1269b9fe724SAlex Deucher uint32_t y_data_mask; 127771fe6b9SJerome Glisse }; 128771fe6b9SJerome Glisse 129771fe6b9SJerome Glisse struct radeon_tmds_pll { 130771fe6b9SJerome Glisse uint32_t freq; 131771fe6b9SJerome Glisse uint32_t value; 132771fe6b9SJerome Glisse }; 133771fe6b9SJerome Glisse 134771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 135771fe6b9SJerome Glisse 1367c27f87dSAlex Deucher /* pll flags */ 137771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 140771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 141771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15086cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 151f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152771fe6b9SJerome Glisse 153771fe6b9SJerome Glisse struct radeon_pll { 154fc10332bSAlex Deucher /* reference frequency */ 155fc10332bSAlex Deucher uint32_t reference_freq; 156fc10332bSAlex Deucher 157fc10332bSAlex Deucher /* fixed dividers */ 158fc10332bSAlex Deucher uint32_t reference_div; 159fc10332bSAlex Deucher uint32_t post_div; 160fc10332bSAlex Deucher 161fc10332bSAlex Deucher /* pll in/out limits */ 162771fe6b9SJerome Glisse uint32_t pll_in_min; 163771fe6b9SJerome Glisse uint32_t pll_in_max; 164771fe6b9SJerome Glisse uint32_t pll_out_min; 165771fe6b9SJerome Glisse uint32_t pll_out_max; 16686cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 16786cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 168fc10332bSAlex Deucher uint32_t best_vco; 169771fe6b9SJerome Glisse 170fc10332bSAlex Deucher /* divider limits */ 171771fe6b9SJerome Glisse uint32_t min_ref_div; 172771fe6b9SJerome Glisse uint32_t max_ref_div; 173771fe6b9SJerome Glisse uint32_t min_post_div; 174771fe6b9SJerome Glisse uint32_t max_post_div; 175771fe6b9SJerome Glisse uint32_t min_feedback_div; 176771fe6b9SJerome Glisse uint32_t max_feedback_div; 177771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 178771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 179fc10332bSAlex Deucher 180fc10332bSAlex Deucher /* flags for the current clock */ 181fc10332bSAlex Deucher uint32_t flags; 182fc10332bSAlex Deucher 183fc10332bSAlex Deucher /* pll id */ 184fc10332bSAlex Deucher uint32_t id; 185771fe6b9SJerome Glisse }; 186771fe6b9SJerome Glisse 187771fe6b9SJerome Glisse struct radeon_i2c_chan { 188771fe6b9SJerome Glisse struct i2c_adapter adapter; 189746c1aa4SDave Airlie struct drm_device *dev; 190746c1aa4SDave Airlie union { 191ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 192746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 193746c1aa4SDave Airlie } algo; 194771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 195771fe6b9SJerome Glisse }; 196771fe6b9SJerome Glisse 197771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 198771fe6b9SJerome Glisse enum radeon_connector_table { 199aa74fbb4SAlex Deucher CT_NONE = 0, 200771fe6b9SJerome Glisse CT_GENERIC, 201771fe6b9SJerome Glisse CT_IBOOK, 202771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 203771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 204771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 205771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 206771fe6b9SJerome Glisse CT_MINI_INTERNAL, 207771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 208771fe6b9SJerome Glisse CT_EMAC, 20976a7142aSDave Airlie CT_RN50_POWER, 210aa74fbb4SAlex Deucher CT_MAC_X800, 2119fad321aSAlex Deucher CT_MAC_G5_9600, 2126a556039SAlex Deucher CT_SAM440EP 213771fe6b9SJerome Glisse }; 214771fe6b9SJerome Glisse 215fcec570bSAlex Deucher enum radeon_dvo_chip { 216fcec570bSAlex Deucher DVO_SIL164, 217fcec570bSAlex Deucher DVO_SIL1178, 218fcec570bSAlex Deucher }; 219fcec570bSAlex Deucher 2208be48d92SDave Airlie struct radeon_fbdev; 22138651674SDave Airlie 2220783986aSAlex Deucher struct radeon_afmt { 2230783986aSAlex Deucher bool enabled; 2240783986aSAlex Deucher int offset; 2250783986aSAlex Deucher bool last_buffer_filled_status; 2260783986aSAlex Deucher int id; 2270783986aSAlex Deucher }; 2280783986aSAlex Deucher 229771fe6b9SJerome Glisse struct radeon_mode_info { 230771fe6b9SJerome Glisse struct atom_context *atom_context; 23161c4b24bSMathias Fröhlich struct card_info *atom_card_info; 232771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 233771fe6b9SJerome Glisse bool mode_config_initialized; 234bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 2350783986aSAlex Deucher struct radeon_afmt *afmt[6]; 236445282dbSDave Airlie /* DVI-I properties */ 237445282dbSDave Airlie struct drm_property *coherent_mode_property; 238445282dbSDave Airlie /* DAC enable load detect */ 239445282dbSDave Airlie struct drm_property *load_detect_property; 2405b1714d3SAlex Deucher /* TV standard */ 241445282dbSDave Airlie struct drm_property *tv_std_property; 242445282dbSDave Airlie /* legacy TMDS PLL detect */ 243445282dbSDave Airlie struct drm_property *tmds_pll_property; 2445b1714d3SAlex Deucher /* underscan */ 2455b1714d3SAlex Deucher struct drm_property *underscan_property; 2465bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2475bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2483c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2493c537889SAlex Deucher struct edid *bios_hardcoded_edid; 250fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 25138651674SDave Airlie 25238651674SDave Airlie /* pointer to fbdev info structure */ 2538be48d92SDave Airlie struct radeon_fbdev *rfbdev; 254af7912e5SAlex Deucher /* firmware flags */ 255af7912e5SAlex Deucher u16 firmware_flags; 256bced76f2SAlex Deucher /* pointer to backlight encoder */ 257bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 258c93bb85bSJerome Glisse }; 259c93bb85bSJerome Glisse 26091030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 26191030880SAlex Deucher 262bced76f2SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 263bced76f2SAlex Deucher 26491030880SAlex Deucher struct radeon_backlight_privdata { 26591030880SAlex Deucher struct radeon_encoder *encoder; 26691030880SAlex Deucher uint8_t negative; 26791030880SAlex Deucher }; 26891030880SAlex Deucher 26991030880SAlex Deucher #endif 27091030880SAlex Deucher 2714ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2724ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2734ce001abSDave Airlie 2744ce001abSDave Airlie /* need to store these as reading 2754ce001abSDave Airlie back code tables is excessive */ 2764ce001abSDave Airlie struct radeon_tv_regs { 2774ce001abSDave Airlie uint32_t tv_uv_adr; 2784ce001abSDave Airlie uint32_t timing_cntl; 2794ce001abSDave Airlie uint32_t hrestart; 2804ce001abSDave Airlie uint32_t vrestart; 2814ce001abSDave Airlie uint32_t frestart; 2824ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2834ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2844ce001abSDave Airlie }; 2854ce001abSDave Airlie 28619eca43eSAlex Deucher struct radeon_atom_ss { 28719eca43eSAlex Deucher uint16_t percentage; 28819eca43eSAlex Deucher uint8_t type; 28919eca43eSAlex Deucher uint16_t step; 29019eca43eSAlex Deucher uint8_t delay; 29119eca43eSAlex Deucher uint8_t range; 29219eca43eSAlex Deucher uint8_t refdiv; 29319eca43eSAlex Deucher /* asic_ss */ 29419eca43eSAlex Deucher uint16_t rate; 29519eca43eSAlex Deucher uint16_t amount; 29619eca43eSAlex Deucher }; 29719eca43eSAlex Deucher 298771fe6b9SJerome Glisse struct radeon_crtc { 299771fe6b9SJerome Glisse struct drm_crtc base; 300771fe6b9SJerome Glisse int crtc_id; 301771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 302771fe6b9SJerome Glisse bool enabled; 303771fe6b9SJerome Glisse bool can_tile; 3046c0ae2abSAlex Deucher bool in_mode_set; 305771fe6b9SJerome Glisse uint32_t crtc_offset; 306771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 307771fe6b9SJerome Glisse uint64_t cursor_addr; 308771fe6b9SJerome Glisse int cursor_width; 309771fe6b9SJerome Glisse int cursor_height; 3104162338aSDave Airlie uint32_t legacy_display_base_addr; 311c836e862SAlex Deucher uint32_t legacy_cursor_offset; 312c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3135b1714d3SAlex Deucher u8 h_border; 3145b1714d3SAlex Deucher u8 v_border; 315c93bb85bSJerome Glisse fixed20_12 vsc; 316c93bb85bSJerome Glisse fixed20_12 hsc; 317de2103e4SAlex Deucher struct drm_display_mode native_mode; 318bcc1c2a1SAlex Deucher int pll_id; 3196f34be50SAlex Deucher /* page flipping */ 3206f34be50SAlex Deucher struct radeon_unpin_work *unpin_work; 3216f34be50SAlex Deucher int deferred_flip_completion; 32219eca43eSAlex Deucher /* pll sharing */ 32319eca43eSAlex Deucher struct radeon_atom_ss ss; 32419eca43eSAlex Deucher bool ss_enabled; 32519eca43eSAlex Deucher u32 adjusted_clock; 32619eca43eSAlex Deucher int bpc; 32719eca43eSAlex Deucher u32 pll_reference_div; 32819eca43eSAlex Deucher u32 pll_post_div; 32919eca43eSAlex Deucher u32 pll_flags; 3305df3196bSAlex Deucher struct drm_encoder *encoder; 33157b35e29SAlex Deucher struct drm_connector *connector; 332771fe6b9SJerome Glisse }; 333771fe6b9SJerome Glisse 334771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 335771fe6b9SJerome Glisse /* legacy primary dac */ 336771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 337771fe6b9SJerome Glisse }; 338771fe6b9SJerome Glisse 339771fe6b9SJerome Glisse struct radeon_encoder_lvds { 340771fe6b9SJerome Glisse /* legacy lvds */ 341771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 342771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 343771fe6b9SJerome Glisse uint8_t panel_digon_delay; 344771fe6b9SJerome Glisse uint8_t panel_blon_delay; 345771fe6b9SJerome Glisse uint16_t panel_ref_divider; 346771fe6b9SJerome Glisse uint8_t panel_post_divider; 347771fe6b9SJerome Glisse uint16_t panel_fb_divider; 348771fe6b9SJerome Glisse bool use_bios_dividers; 349771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 350771fe6b9SJerome Glisse /* panel mode */ 351de2103e4SAlex Deucher struct drm_display_mode native_mode; 35263ec0119SMichel Dänzer struct backlight_device *bl_dev; 35363ec0119SMichel Dänzer int dpms_mode; 35463ec0119SMichel Dänzer uint8_t backlight_level; 355771fe6b9SJerome Glisse }; 356771fe6b9SJerome Glisse 357771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 358771fe6b9SJerome Glisse /* legacy tv dac */ 359771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 360771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 361771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 362771fe6b9SJerome Glisse 3634ce001abSDave Airlie int h_pos; 3644ce001abSDave Airlie int v_pos; 3654ce001abSDave Airlie int h_size; 3664ce001abSDave Airlie int supported_tv_stds; 3674ce001abSDave Airlie bool tv_on; 368771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3694ce001abSDave Airlie struct radeon_tv_regs tv; 370771fe6b9SJerome Glisse }; 371771fe6b9SJerome Glisse 372771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 373771fe6b9SJerome Glisse /* legacy int tmds */ 374771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 375771fe6b9SJerome Glisse }; 376771fe6b9SJerome Glisse 377fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 378fcec570bSAlex Deucher /* tmds over dvo */ 379fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 380fcec570bSAlex Deucher uint8_t slave_addr; 381fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 382fcec570bSAlex Deucher }; 383fcec570bSAlex Deucher 384ebbe1cb9SAlex Deucher /* spread spectrum */ 385771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 3865137ee94SAlex Deucher bool linkb; 387771fe6b9SJerome Glisse /* atom dig */ 388771fe6b9SJerome Glisse bool coherent_mode; 389ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 390ba032a58SAlex Deucher /* atom lvds/edp */ 391ba032a58SAlex Deucher uint32_t lcd_misc; 392771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 393ba032a58SAlex Deucher uint32_t lcd_ss_id; 394771fe6b9SJerome Glisse /* panel mode */ 395de2103e4SAlex Deucher struct drm_display_mode native_mode; 39663ec0119SMichel Dänzer struct backlight_device *bl_dev; 39763ec0119SMichel Dänzer int dpms_mode; 39863ec0119SMichel Dänzer uint8_t backlight_level; 399386d4d75SAlex Deucher int panel_mode; 4000783986aSAlex Deucher struct radeon_afmt *afmt; 401771fe6b9SJerome Glisse }; 402771fe6b9SJerome Glisse 4034ce001abSDave Airlie struct radeon_encoder_atom_dac { 4044ce001abSDave Airlie enum radeon_tv_std tv_std; 4054ce001abSDave Airlie }; 4064ce001abSDave Airlie 407771fe6b9SJerome Glisse struct radeon_encoder { 408771fe6b9SJerome Glisse struct drm_encoder base; 4095137ee94SAlex Deucher uint32_t encoder_enum; 410771fe6b9SJerome Glisse uint32_t encoder_id; 411771fe6b9SJerome Glisse uint32_t devices; 4124ce001abSDave Airlie uint32_t active_device; 413771fe6b9SJerome Glisse uint32_t flags; 414771fe6b9SJerome Glisse uint32_t pixel_clock; 415771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4165b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4175bccf5e3SMarius Gröger uint32_t underscan_hborder; 4185bccf5e3SMarius Gröger uint32_t underscan_vborder; 419de2103e4SAlex Deucher struct drm_display_mode native_mode; 420771fe6b9SJerome Glisse void *enc_priv; 42158bd0863SChristian König int audio_polling_active; 4223e4b9982SAlex Deucher bool is_ext_encoder; 42336868bdaSAlex Deucher u16 caps; 424771fe6b9SJerome Glisse }; 425771fe6b9SJerome Glisse 426771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 427771fe6b9SJerome Glisse uint32_t igp_lane_info; 4284143e919SAlex Deucher /* displayport */ 429746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 4301a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4314143e919SAlex Deucher u8 dp_sink_type; 4325801ead6SAlex Deucher int dp_clock; 4335801ead6SAlex Deucher int dp_lane_count; 4348b834852SAlex Deucher bool edp_on; 435771fe6b9SJerome Glisse }; 436771fe6b9SJerome Glisse 437eed45b30SAlex Deucher struct radeon_gpio_rec { 438eed45b30SAlex Deucher bool valid; 439eed45b30SAlex Deucher u8 id; 440eed45b30SAlex Deucher u32 reg; 441eed45b30SAlex Deucher u32 mask; 442eed45b30SAlex Deucher }; 443eed45b30SAlex Deucher 444eed45b30SAlex Deucher struct radeon_hpd { 445eed45b30SAlex Deucher enum radeon_hpd_id hpd; 446eed45b30SAlex Deucher u8 plugged_state; 447eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 448eed45b30SAlex Deucher }; 449eed45b30SAlex Deucher 45026b5bc98SAlex Deucher struct radeon_router { 45126b5bc98SAlex Deucher u32 router_id; 45226b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 45326b5bc98SAlex Deucher u8 i2c_addr; 454fb939dfcSAlex Deucher /* i2c mux */ 455fb939dfcSAlex Deucher bool ddc_valid; 456fb939dfcSAlex Deucher u8 ddc_mux_type; 457fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 458fb939dfcSAlex Deucher u8 ddc_mux_state; 459fb939dfcSAlex Deucher /* clock/data mux */ 460fb939dfcSAlex Deucher bool cd_valid; 461fb939dfcSAlex Deucher u8 cd_mux_type; 462fb939dfcSAlex Deucher u8 cd_mux_control_pin; 463fb939dfcSAlex Deucher u8 cd_mux_state; 46426b5bc98SAlex Deucher }; 46526b5bc98SAlex Deucher 466771fe6b9SJerome Glisse struct radeon_connector { 467771fe6b9SJerome Glisse struct drm_connector base; 468771fe6b9SJerome Glisse uint32_t connector_id; 469771fe6b9SJerome Glisse uint32_t devices; 470771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 4715b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 4720294cf4fSAlex Deucher bool shared_ddc; 4734ce001abSDave Airlie bool use_digital; 4744ce001abSDave Airlie /* we need to mind the EDID between detect 4754ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 4764ce001abSDave Airlie struct edid *edid; 477771fe6b9SJerome Glisse void *con_priv; 478445282dbSDave Airlie bool dac_load_detect; 479d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 480b75fad06SAlex Deucher uint16_t connector_object_id; 481eed45b30SAlex Deucher struct radeon_hpd hpd; 48226b5bc98SAlex Deucher struct radeon_router router; 48326b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 484771fe6b9SJerome Glisse }; 485771fe6b9SJerome Glisse 486771fe6b9SJerome Glisse struct radeon_framebuffer { 487771fe6b9SJerome Glisse struct drm_framebuffer base; 488771fe6b9SJerome Glisse struct drm_gem_object *obj; 489771fe6b9SJerome Glisse }; 490771fe6b9SJerome Glisse 491996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 492996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 4936383cf7dSMario Kleiner 494d79766faSAlex Deucher extern enum radeon_tv_std 495d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 496d79766faSAlex Deucher extern enum radeon_tv_std 497d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 498d79766faSAlex Deucher 4995b1714d3SAlex Deucher extern struct drm_connector * 5005b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 5019aa59993SAlex Deucher extern struct drm_connector * 5029aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 5039aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 5049aa59993SAlex Deucher u32 pixel_clock); 5055b1714d3SAlex Deucher 5061d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 5071d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 508d7fa8bb3SAlex Deucher extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 509d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 510eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 511d7fa8bb3SAlex Deucher 512d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 513224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 5145801ead6SAlex Deucher struct drm_display_mode *mode); 5155801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 516e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 517224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 5185801ead6SAlex Deucher struct drm_connector *connector); 519d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 5204143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 5219fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 522386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 523386d4d75SAlex Deucher struct drm_connector *connector); 524558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 525ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 526f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 5275801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 5285801ead6SAlex Deucher int action, uint8_t lane_num, 5295801ead6SAlex Deucher uint8_t lane_set); 530591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 5313f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 532746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 533834b2904SAlex Deucher u8 write_byte, u8 *read_byte); 534746c1aa4SDave Airlie 535f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 536f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 537f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 538f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 539f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 540f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 541f376b94fSAlex Deucher const char *name); 542f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 543f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 544746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 5456a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 5466a93cb25SAlex Deucher const char *name); 547771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 548771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 549771fe6b9SJerome Glisse const char *name); 550771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 5515a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 552fcec570bSAlex Deucher u8 slave_addr, 553fcec570bSAlex Deucher u8 addr, 554fcec570bSAlex Deucher u8 *val); 5555a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 556fcec570bSAlex Deucher u8 slave_addr, 557fcec570bSAlex Deucher u8 addr, 558fcec570bSAlex Deucher u8 val); 559fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 560fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 561bc1c4dc3SAlex Deucher extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 562771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 563771fe6b9SJerome Glisse 564771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 565771fe6b9SJerome Glisse 566ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 567ba032a58SAlex Deucher struct radeon_atom_ss *ss, 568ba032a58SAlex Deucher int id); 569ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 570ba032a58SAlex Deucher struct radeon_atom_ss *ss, 571ba032a58SAlex Deucher int id, u32 clock); 572ba032a58SAlex Deucher 573f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 574771fe6b9SJerome Glisse uint64_t freq, 575771fe6b9SJerome Glisse uint32_t *dot_clock_p, 576771fe6b9SJerome Glisse uint32_t *fb_div_p, 577771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 578771fe6b9SJerome Glisse uint32_t *ref_div_p, 579fc10332bSAlex Deucher uint32_t *post_div_p); 580771fe6b9SJerome Glisse 581f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 582f523f74eSAlex Deucher u32 freq, 583f523f74eSAlex Deucher u32 *dot_clock_p, 584f523f74eSAlex Deucher u32 *fb_div_p, 585f523f74eSAlex Deucher u32 *frac_fb_div_p, 586f523f74eSAlex Deucher u32 *ref_div_p, 587f523f74eSAlex Deucher u32 *post_div_p); 588f523f74eSAlex Deucher 5891f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 5901f3b6a45SDave Airlie 591771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 592771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 593771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 594771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 595771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 59699999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 59732f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 598771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 5992dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 6004ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 601771fe6b9SJerome Glisse 602771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 603771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 604771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 6054dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 6064dd19b0dSChris Ball struct drm_framebuffer *fb, 60721c74a8eSJason Wessel int x, int y, 60821c74a8eSJason Wessel enum mode_set_atomic state); 609771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 610771fe6b9SJerome Glisse struct drm_display_mode *mode, 611771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 612771fe6b9SJerome Glisse int x, int y, 613771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 614771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 615771fe6b9SJerome Glisse 616771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 617771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 6184dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 6194dd19b0dSChris Ball struct drm_framebuffer *fb, 62021c74a8eSJason Wessel int x, int y, 62121c74a8eSJason Wessel enum mode_set_atomic state); 6224dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 6234dd19b0dSChris Ball struct drm_framebuffer *fb, 6244dd19b0dSChris Ball int x, int y, int atomic); 625771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 626771fe6b9SJerome Glisse struct drm_file *file_priv, 627771fe6b9SJerome Glisse uint32_t handle, 628771fe6b9SJerome Glisse uint32_t width, 629771fe6b9SJerome Glisse uint32_t height); 630771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 631771fe6b9SJerome Glisse int x, int y); 632771fe6b9SJerome Glisse 633f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 634f5a80209SMario Kleiner int *vpos, int *hpos); 6356383cf7dSMario Kleiner 6363c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 6373c537889SAlex Deucher extern struct edid * 638c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 639771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 640771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 641771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 642771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 643fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 644445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 645fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 646445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 647fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 648445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 649fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 650fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 651fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 652fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 6536fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 6546fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 6556fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 6566fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 657771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 658771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 659771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 660771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 661771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 662771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 663771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 664fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 665fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 666771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 667771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 668771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 669771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 670f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 671f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 672771fe6b9SJerome Glisse extern void 673771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 674771fe6b9SJerome Glisse extern void 675771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 676771fe6b9SJerome Glisse extern void 677771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 678771fe6b9SJerome Glisse extern void 679771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 680771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 681771fe6b9SJerome Glisse u16 blue, int regno); 682b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 683b8c00ac5SDave Airlie u16 *blue, int regno); 684aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 68538651674SDave Airlie struct radeon_framebuffer *rfb, 686308e5bcbSJesse Barnes struct drm_mode_fb_cmd2 *mode_cmd, 687771fe6b9SJerome Glisse struct drm_gem_object *obj); 688771fe6b9SJerome Glisse 689771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 690771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 691771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 692771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 693771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 694771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 695771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 696771fe6b9SJerome Glisse 697771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 698771fe6b9SJerome Glisse 699771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 700771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 701771fe6b9SJerome Glisse 702771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 703771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 704771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 705c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 706e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 707c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 7083515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 7093515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 7104ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 711771fe6b9SJerome Glisse 7124ce001abSDave Airlie /* legacy tv */ 7134ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 7144ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 7154ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 7164ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 7174ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 7184ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 7194ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 7204ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 7214ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 7224ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 7234ce001abSDave Airlie struct drm_display_mode *mode, 7244ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 72538651674SDave Airlie 72638651674SDave Airlie /* fbdev layer */ 72738651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 72838651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 72938651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 73038651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev); 73138651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 732eb1f8e4fSDave Airlie 733eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 7346f34be50SAlex Deucher 7356f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 7366f34be50SAlex Deucher 737ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 738771fe6b9SJerome Glisse #endif 739