1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33760285e7SDavid Howells #include <drm/drm_crtc.h> 34760285e7SDavid Howells #include <drm/drm_edid.h> 35760285e7SDavid Howells #include <drm/drm_dp_helper.h> 36760285e7SDavid Howells #include <drm/drm_fixed.h> 37760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 38771fe6b9SJerome Glisse #include <linux/i2c.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse 4138651674SDave Airlie struct radeon_bo; 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 4988f39063SStefan Brüns #define RADEON_MAX_HPD_PINS 7 5088f39063SStefan Brüns #define RADEON_MAX_CRTCS 6 5188f39063SStefan Brüns #define RADEON_MAX_AFMT_BLOCKS 7 5288f39063SStefan Brüns 53771fe6b9SJerome Glisse enum radeon_rmx_type { 54771fe6b9SJerome Glisse RMX_OFF, 55771fe6b9SJerome Glisse RMX_FULL, 56771fe6b9SJerome Glisse RMX_CENTER, 57771fe6b9SJerome Glisse RMX_ASPECT 58771fe6b9SJerome Glisse }; 59771fe6b9SJerome Glisse 60771fe6b9SJerome Glisse enum radeon_tv_std { 61771fe6b9SJerome Glisse TV_STD_NTSC, 62771fe6b9SJerome Glisse TV_STD_PAL, 63771fe6b9SJerome Glisse TV_STD_PAL_M, 64771fe6b9SJerome Glisse TV_STD_PAL_60, 65771fe6b9SJerome Glisse TV_STD_NTSC_J, 66771fe6b9SJerome Glisse TV_STD_SCART_PAL, 67771fe6b9SJerome Glisse TV_STD_SECAM, 68771fe6b9SJerome Glisse TV_STD_PAL_CN, 69d79766faSAlex Deucher TV_STD_PAL_N, 70771fe6b9SJerome Glisse }; 71771fe6b9SJerome Glisse 725b1714d3SAlex Deucher enum radeon_underscan_type { 735b1714d3SAlex Deucher UNDERSCAN_OFF, 745b1714d3SAlex Deucher UNDERSCAN_ON, 755b1714d3SAlex Deucher UNDERSCAN_AUTO, 765b1714d3SAlex Deucher }; 775b1714d3SAlex Deucher 788e36ed00SAlex Deucher enum radeon_hpd_id { 798e36ed00SAlex Deucher RADEON_HPD_1 = 0, 808e36ed00SAlex Deucher RADEON_HPD_2, 818e36ed00SAlex Deucher RADEON_HPD_3, 828e36ed00SAlex Deucher RADEON_HPD_4, 838e36ed00SAlex Deucher RADEON_HPD_5, 848e36ed00SAlex Deucher RADEON_HPD_6, 858e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 868e36ed00SAlex Deucher }; 878e36ed00SAlex Deucher 88f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 89f376b94fSAlex Deucher 909b9fe724SAlex Deucher /* radeon gpio-based i2c 919b9fe724SAlex Deucher * 1. "mask" reg and bits 929b9fe724SAlex Deucher * grabs the gpio pins for software use 939b9fe724SAlex Deucher * 0=not held 1=held 949b9fe724SAlex Deucher * 2. "a" reg and bits 959b9fe724SAlex Deucher * output pin value 969b9fe724SAlex Deucher * 0=low 1=high 979b9fe724SAlex Deucher * 3. "en" reg and bits 989b9fe724SAlex Deucher * sets the pin direction 999b9fe724SAlex Deucher * 0=input 1=output 1009b9fe724SAlex Deucher * 4. "y" reg and bits 1019b9fe724SAlex Deucher * input pin value 1029b9fe724SAlex Deucher * 0=low 1=high 1039b9fe724SAlex Deucher */ 104771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 105771fe6b9SJerome Glisse bool valid; 1066a93cb25SAlex Deucher /* id used by atom */ 1076a93cb25SAlex Deucher uint8_t i2c_id; 108bcc1c2a1SAlex Deucher /* id used by atom */ 1098e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1106a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1116a93cb25SAlex Deucher bool hw_capable; 1126a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1136a93cb25SAlex Deucher bool mm_i2c; 1146a93cb25SAlex Deucher /* regs and bits */ 115771fe6b9SJerome Glisse uint32_t mask_clk_reg; 116771fe6b9SJerome Glisse uint32_t mask_data_reg; 117771fe6b9SJerome Glisse uint32_t a_clk_reg; 118771fe6b9SJerome Glisse uint32_t a_data_reg; 1199b9fe724SAlex Deucher uint32_t en_clk_reg; 1209b9fe724SAlex Deucher uint32_t en_data_reg; 1219b9fe724SAlex Deucher uint32_t y_clk_reg; 1229b9fe724SAlex Deucher uint32_t y_data_reg; 123771fe6b9SJerome Glisse uint32_t mask_clk_mask; 124771fe6b9SJerome Glisse uint32_t mask_data_mask; 125771fe6b9SJerome Glisse uint32_t a_clk_mask; 126771fe6b9SJerome Glisse uint32_t a_data_mask; 1279b9fe724SAlex Deucher uint32_t en_clk_mask; 1289b9fe724SAlex Deucher uint32_t en_data_mask; 1299b9fe724SAlex Deucher uint32_t y_clk_mask; 1309b9fe724SAlex Deucher uint32_t y_data_mask; 131771fe6b9SJerome Glisse }; 132771fe6b9SJerome Glisse 133771fe6b9SJerome Glisse struct radeon_tmds_pll { 134771fe6b9SJerome Glisse uint32_t freq; 135771fe6b9SJerome Glisse uint32_t value; 136771fe6b9SJerome Glisse }; 137771fe6b9SJerome Glisse 138771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 139771fe6b9SJerome Glisse 1407c27f87dSAlex Deucher /* pll flags */ 141771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 142771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 143771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 144771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 147771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 148771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 149771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 150771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 151771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 152d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 153fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15486cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 155f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 156771fe6b9SJerome Glisse 157771fe6b9SJerome Glisse struct radeon_pll { 158fc10332bSAlex Deucher /* reference frequency */ 159fc10332bSAlex Deucher uint32_t reference_freq; 160fc10332bSAlex Deucher 161fc10332bSAlex Deucher /* fixed dividers */ 162fc10332bSAlex Deucher uint32_t reference_div; 163fc10332bSAlex Deucher uint32_t post_div; 164fc10332bSAlex Deucher 165fc10332bSAlex Deucher /* pll in/out limits */ 166771fe6b9SJerome Glisse uint32_t pll_in_min; 167771fe6b9SJerome Glisse uint32_t pll_in_max; 168771fe6b9SJerome Glisse uint32_t pll_out_min; 169771fe6b9SJerome Glisse uint32_t pll_out_max; 17086cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 17186cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 172fc10332bSAlex Deucher uint32_t best_vco; 173771fe6b9SJerome Glisse 174fc10332bSAlex Deucher /* divider limits */ 175771fe6b9SJerome Glisse uint32_t min_ref_div; 176771fe6b9SJerome Glisse uint32_t max_ref_div; 177771fe6b9SJerome Glisse uint32_t min_post_div; 178771fe6b9SJerome Glisse uint32_t max_post_div; 179771fe6b9SJerome Glisse uint32_t min_feedback_div; 180771fe6b9SJerome Glisse uint32_t max_feedback_div; 181771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 182771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 183fc10332bSAlex Deucher 184fc10332bSAlex Deucher /* flags for the current clock */ 185fc10332bSAlex Deucher uint32_t flags; 186fc10332bSAlex Deucher 187fc10332bSAlex Deucher /* pll id */ 188fc10332bSAlex Deucher uint32_t id; 189771fe6b9SJerome Glisse }; 190771fe6b9SJerome Glisse 191771fe6b9SJerome Glisse struct radeon_i2c_chan { 192771fe6b9SJerome Glisse struct i2c_adapter adapter; 193746c1aa4SDave Airlie struct drm_device *dev; 194ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 195771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 196496263bfSAlex Deucher struct drm_dp_aux aux; 197379dfc25SAlex Deucher bool has_aux; 198831719d6SAlex Deucher struct mutex mutex; 199771fe6b9SJerome Glisse }; 200771fe6b9SJerome Glisse 201771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 202771fe6b9SJerome Glisse enum radeon_connector_table { 203aa74fbb4SAlex Deucher CT_NONE = 0, 204771fe6b9SJerome Glisse CT_GENERIC, 205771fe6b9SJerome Glisse CT_IBOOK, 206771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 207771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 208771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 209771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 210771fe6b9SJerome Glisse CT_MINI_INTERNAL, 211771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 212771fe6b9SJerome Glisse CT_EMAC, 21376a7142aSDave Airlie CT_RN50_POWER, 214aa74fbb4SAlex Deucher CT_MAC_X800, 2159fad321aSAlex Deucher CT_MAC_G5_9600, 216cafa59b9SAlex Deucher CT_SAM440EP, 217cafa59b9SAlex Deucher CT_MAC_G4_SILVER 218771fe6b9SJerome Glisse }; 219771fe6b9SJerome Glisse 220fcec570bSAlex Deucher enum radeon_dvo_chip { 221fcec570bSAlex Deucher DVO_SIL164, 222fcec570bSAlex Deucher DVO_SIL1178, 223fcec570bSAlex Deucher }; 224fcec570bSAlex Deucher 2258be48d92SDave Airlie struct radeon_fbdev; 22638651674SDave Airlie 2270783986aSAlex Deucher struct radeon_afmt { 2280783986aSAlex Deucher bool enabled; 2290783986aSAlex Deucher int offset; 2300783986aSAlex Deucher bool last_buffer_filled_status; 2310783986aSAlex Deucher int id; 232b530602fSAlex Deucher struct r600_audio_pin *pin; 2330783986aSAlex Deucher }; 2340783986aSAlex Deucher 235771fe6b9SJerome Glisse struct radeon_mode_info { 236771fe6b9SJerome Glisse struct atom_context *atom_context; 23761c4b24bSMathias Fröhlich struct card_info *atom_card_info; 238771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 239771fe6b9SJerome Glisse bool mode_config_initialized; 24088f39063SStefan Brüns struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 24188f39063SStefan Brüns struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 242445282dbSDave Airlie /* DVI-I properties */ 243445282dbSDave Airlie struct drm_property *coherent_mode_property; 244445282dbSDave Airlie /* DAC enable load detect */ 245445282dbSDave Airlie struct drm_property *load_detect_property; 2465b1714d3SAlex Deucher /* TV standard */ 247445282dbSDave Airlie struct drm_property *tv_std_property; 248445282dbSDave Airlie /* legacy TMDS PLL detect */ 249445282dbSDave Airlie struct drm_property *tmds_pll_property; 2505b1714d3SAlex Deucher /* underscan */ 2515b1714d3SAlex Deucher struct drm_property *underscan_property; 2525bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2535bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2548666c076SAlex Deucher /* audio */ 2558666c076SAlex Deucher struct drm_property *audio_property; 2566214bb74SAlex Deucher /* FMT dithering */ 2576214bb74SAlex Deucher struct drm_property *dither_property; 2583c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2593c537889SAlex Deucher struct edid *bios_hardcoded_edid; 260fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 26138651674SDave Airlie 26238651674SDave Airlie /* pointer to fbdev info structure */ 2638be48d92SDave Airlie struct radeon_fbdev *rfbdev; 264af7912e5SAlex Deucher /* firmware flags */ 265af7912e5SAlex Deucher u16 firmware_flags; 266bced76f2SAlex Deucher /* pointer to backlight encoder */ 267bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 268c93bb85bSJerome Glisse }; 269c93bb85bSJerome Glisse 27091030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 27191030880SAlex Deucher 272bced76f2SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 273bced76f2SAlex Deucher 27491030880SAlex Deucher struct radeon_backlight_privdata { 27591030880SAlex Deucher struct radeon_encoder *encoder; 27691030880SAlex Deucher uint8_t negative; 27791030880SAlex Deucher }; 27891030880SAlex Deucher 27991030880SAlex Deucher #endif 28091030880SAlex Deucher 2814ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2824ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2834ce001abSDave Airlie 2844ce001abSDave Airlie /* need to store these as reading 2854ce001abSDave Airlie back code tables is excessive */ 2864ce001abSDave Airlie struct radeon_tv_regs { 2874ce001abSDave Airlie uint32_t tv_uv_adr; 2884ce001abSDave Airlie uint32_t timing_cntl; 2894ce001abSDave Airlie uint32_t hrestart; 2904ce001abSDave Airlie uint32_t vrestart; 2914ce001abSDave Airlie uint32_t frestart; 2924ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2934ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2944ce001abSDave Airlie }; 2954ce001abSDave Airlie 29619eca43eSAlex Deucher struct radeon_atom_ss { 29719eca43eSAlex Deucher uint16_t percentage; 29818f8f52bSAlex Deucher uint16_t percentage_divider; 29919eca43eSAlex Deucher uint8_t type; 30019eca43eSAlex Deucher uint16_t step; 30119eca43eSAlex Deucher uint8_t delay; 30219eca43eSAlex Deucher uint8_t range; 30319eca43eSAlex Deucher uint8_t refdiv; 30419eca43eSAlex Deucher /* asic_ss */ 30519eca43eSAlex Deucher uint16_t rate; 30619eca43eSAlex Deucher uint16_t amount; 30719eca43eSAlex Deucher }; 30819eca43eSAlex Deucher 309a2b6d3b3SMichel Dänzer enum radeon_flip_status { 310a2b6d3b3SMichel Dänzer RADEON_FLIP_NONE, 311a2b6d3b3SMichel Dänzer RADEON_FLIP_PENDING, 312a2b6d3b3SMichel Dänzer RADEON_FLIP_SUBMITTED 313a2b6d3b3SMichel Dänzer }; 314a2b6d3b3SMichel Dänzer 315771fe6b9SJerome Glisse struct radeon_crtc { 316771fe6b9SJerome Glisse struct drm_crtc base; 317771fe6b9SJerome Glisse int crtc_id; 318771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 319771fe6b9SJerome Glisse bool enabled; 320771fe6b9SJerome Glisse bool can_tile; 321771fe6b9SJerome Glisse uint32_t crtc_offset; 322771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 323771fe6b9SJerome Glisse uint64_t cursor_addr; 32478b1a601SMichel Dänzer int cursor_x; 32578b1a601SMichel Dänzer int cursor_y; 32678b1a601SMichel Dänzer int cursor_hot_x; 32778b1a601SMichel Dänzer int cursor_hot_y; 328771fe6b9SJerome Glisse int cursor_width; 329771fe6b9SJerome Glisse int cursor_height; 3309e05fa1dSAlex Deucher int max_cursor_width; 3319e05fa1dSAlex Deucher int max_cursor_height; 3324162338aSDave Airlie uint32_t legacy_display_base_addr; 333c836e862SAlex Deucher uint32_t legacy_cursor_offset; 334c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3355b1714d3SAlex Deucher u8 h_border; 3365b1714d3SAlex Deucher u8 v_border; 337c93bb85bSJerome Glisse fixed20_12 vsc; 338c93bb85bSJerome Glisse fixed20_12 hsc; 339de2103e4SAlex Deucher struct drm_display_mode native_mode; 340bcc1c2a1SAlex Deucher int pll_id; 3416f34be50SAlex Deucher /* page flipping */ 342fa7f517cSChristian König struct workqueue_struct *flip_queue; 343fa7f517cSChristian König struct radeon_flip_work *flip_work; 344a2b6d3b3SMichel Dänzer enum radeon_flip_status flip_status; 34519eca43eSAlex Deucher /* pll sharing */ 34619eca43eSAlex Deucher struct radeon_atom_ss ss; 34719eca43eSAlex Deucher bool ss_enabled; 34819eca43eSAlex Deucher u32 adjusted_clock; 34919eca43eSAlex Deucher int bpc; 35019eca43eSAlex Deucher u32 pll_reference_div; 35119eca43eSAlex Deucher u32 pll_post_div; 35219eca43eSAlex Deucher u32 pll_flags; 3535df3196bSAlex Deucher struct drm_encoder *encoder; 35457b35e29SAlex Deucher struct drm_connector *connector; 3557178d2a6SAlex Deucher /* for dpm */ 3567178d2a6SAlex Deucher u32 line_time; 3577178d2a6SAlex Deucher u32 wm_low; 3587178d2a6SAlex Deucher u32 wm_high; 35966edc1c9SAlex Deucher struct drm_display_mode hw_mode; 360771fe6b9SJerome Glisse }; 361771fe6b9SJerome Glisse 362771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 363771fe6b9SJerome Glisse /* legacy primary dac */ 364771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 365771fe6b9SJerome Glisse }; 366771fe6b9SJerome Glisse 367771fe6b9SJerome Glisse struct radeon_encoder_lvds { 368771fe6b9SJerome Glisse /* legacy lvds */ 369771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 370771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 371771fe6b9SJerome Glisse uint8_t panel_digon_delay; 372771fe6b9SJerome Glisse uint8_t panel_blon_delay; 373771fe6b9SJerome Glisse uint16_t panel_ref_divider; 374771fe6b9SJerome Glisse uint8_t panel_post_divider; 375771fe6b9SJerome Glisse uint16_t panel_fb_divider; 376771fe6b9SJerome Glisse bool use_bios_dividers; 377771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 378771fe6b9SJerome Glisse /* panel mode */ 379de2103e4SAlex Deucher struct drm_display_mode native_mode; 38063ec0119SMichel Dänzer struct backlight_device *bl_dev; 38163ec0119SMichel Dänzer int dpms_mode; 38263ec0119SMichel Dänzer uint8_t backlight_level; 383771fe6b9SJerome Glisse }; 384771fe6b9SJerome Glisse 385771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 386771fe6b9SJerome Glisse /* legacy tv dac */ 387771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 388771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 389771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 390771fe6b9SJerome Glisse 3914ce001abSDave Airlie int h_pos; 3924ce001abSDave Airlie int v_pos; 3934ce001abSDave Airlie int h_size; 3944ce001abSDave Airlie int supported_tv_stds; 3954ce001abSDave Airlie bool tv_on; 396771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3974ce001abSDave Airlie struct radeon_tv_regs tv; 398771fe6b9SJerome Glisse }; 399771fe6b9SJerome Glisse 400771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 401771fe6b9SJerome Glisse /* legacy int tmds */ 402771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 403771fe6b9SJerome Glisse }; 404771fe6b9SJerome Glisse 405fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 406fcec570bSAlex Deucher /* tmds over dvo */ 407fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 408fcec570bSAlex Deucher uint8_t slave_addr; 409fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 410fcec570bSAlex Deucher }; 411fcec570bSAlex Deucher 412ebbe1cb9SAlex Deucher /* spread spectrum */ 413771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 4145137ee94SAlex Deucher bool linkb; 415771fe6b9SJerome Glisse /* atom dig */ 416771fe6b9SJerome Glisse bool coherent_mode; 417ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 418ba032a58SAlex Deucher /* atom lvds/edp */ 419ba032a58SAlex Deucher uint32_t lcd_misc; 420771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 421ba032a58SAlex Deucher uint32_t lcd_ss_id; 422771fe6b9SJerome Glisse /* panel mode */ 423de2103e4SAlex Deucher struct drm_display_mode native_mode; 42463ec0119SMichel Dänzer struct backlight_device *bl_dev; 42563ec0119SMichel Dänzer int dpms_mode; 42663ec0119SMichel Dänzer uint8_t backlight_level; 427386d4d75SAlex Deucher int panel_mode; 4280783986aSAlex Deucher struct radeon_afmt *afmt; 429771fe6b9SJerome Glisse }; 430771fe6b9SJerome Glisse 4314ce001abSDave Airlie struct radeon_encoder_atom_dac { 4324ce001abSDave Airlie enum radeon_tv_std tv_std; 4334ce001abSDave Airlie }; 4344ce001abSDave Airlie 435771fe6b9SJerome Glisse struct radeon_encoder { 436771fe6b9SJerome Glisse struct drm_encoder base; 4375137ee94SAlex Deucher uint32_t encoder_enum; 438771fe6b9SJerome Glisse uint32_t encoder_id; 439771fe6b9SJerome Glisse uint32_t devices; 4404ce001abSDave Airlie uint32_t active_device; 441771fe6b9SJerome Glisse uint32_t flags; 442771fe6b9SJerome Glisse uint32_t pixel_clock; 443771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4445b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4455bccf5e3SMarius Gröger uint32_t underscan_hborder; 4465bccf5e3SMarius Gröger uint32_t underscan_vborder; 447de2103e4SAlex Deucher struct drm_display_mode native_mode; 448771fe6b9SJerome Glisse void *enc_priv; 44958bd0863SChristian König int audio_polling_active; 4503e4b9982SAlex Deucher bool is_ext_encoder; 45136868bdaSAlex Deucher u16 caps; 4521a626b68SSlava Grigorev struct radeon_audio_funcs *audio; 453771fe6b9SJerome Glisse }; 454771fe6b9SJerome Glisse 455771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 456771fe6b9SJerome Glisse uint32_t igp_lane_info; 4574143e919SAlex Deucher /* displayport */ 4581a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4594143e919SAlex Deucher u8 dp_sink_type; 4605801ead6SAlex Deucher int dp_clock; 4615801ead6SAlex Deucher int dp_lane_count; 4628b834852SAlex Deucher bool edp_on; 463771fe6b9SJerome Glisse }; 464771fe6b9SJerome Glisse 465eed45b30SAlex Deucher struct radeon_gpio_rec { 466eed45b30SAlex Deucher bool valid; 467eed45b30SAlex Deucher u8 id; 468eed45b30SAlex Deucher u32 reg; 469eed45b30SAlex Deucher u32 mask; 470727b3d25SAlex Deucher u32 shift; 471eed45b30SAlex Deucher }; 472eed45b30SAlex Deucher 473eed45b30SAlex Deucher struct radeon_hpd { 474eed45b30SAlex Deucher enum radeon_hpd_id hpd; 475eed45b30SAlex Deucher u8 plugged_state; 476eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 477eed45b30SAlex Deucher }; 478eed45b30SAlex Deucher 47926b5bc98SAlex Deucher struct radeon_router { 48026b5bc98SAlex Deucher u32 router_id; 48126b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 48226b5bc98SAlex Deucher u8 i2c_addr; 483fb939dfcSAlex Deucher /* i2c mux */ 484fb939dfcSAlex Deucher bool ddc_valid; 485fb939dfcSAlex Deucher u8 ddc_mux_type; 486fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 487fb939dfcSAlex Deucher u8 ddc_mux_state; 488fb939dfcSAlex Deucher /* clock/data mux */ 489fb939dfcSAlex Deucher bool cd_valid; 490fb939dfcSAlex Deucher u8 cd_mux_type; 491fb939dfcSAlex Deucher u8 cd_mux_control_pin; 492fb939dfcSAlex Deucher u8 cd_mux_state; 49326b5bc98SAlex Deucher }; 49426b5bc98SAlex Deucher 4958666c076SAlex Deucher enum radeon_connector_audio { 4968666c076SAlex Deucher RADEON_AUDIO_DISABLE = 0, 4978666c076SAlex Deucher RADEON_AUDIO_ENABLE = 1, 4988666c076SAlex Deucher RADEON_AUDIO_AUTO = 2 4998666c076SAlex Deucher }; 5008666c076SAlex Deucher 5016214bb74SAlex Deucher enum radeon_connector_dither { 5026214bb74SAlex Deucher RADEON_FMT_DITHER_DISABLE = 0, 5036214bb74SAlex Deucher RADEON_FMT_DITHER_ENABLE = 1, 5046214bb74SAlex Deucher }; 5056214bb74SAlex Deucher 506771fe6b9SJerome Glisse struct radeon_connector { 507771fe6b9SJerome Glisse struct drm_connector base; 508771fe6b9SJerome Glisse uint32_t connector_id; 509771fe6b9SJerome Glisse uint32_t devices; 510771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 5115b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 5120294cf4fSAlex Deucher bool shared_ddc; 5134ce001abSDave Airlie bool use_digital; 5144ce001abSDave Airlie /* we need to mind the EDID between detect 5154ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 5164ce001abSDave Airlie struct edid *edid; 517771fe6b9SJerome Glisse void *con_priv; 518445282dbSDave Airlie bool dac_load_detect; 519d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 520b75fad06SAlex Deucher uint16_t connector_object_id; 521eed45b30SAlex Deucher struct radeon_hpd hpd; 52226b5bc98SAlex Deucher struct radeon_router router; 52326b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 5248666c076SAlex Deucher enum radeon_connector_audio audio; 5256214bb74SAlex Deucher enum radeon_connector_dither dither; 526ea292861SMario Kleiner int pixelclock_for_modeset; 527771fe6b9SJerome Glisse }; 528771fe6b9SJerome Glisse 529771fe6b9SJerome Glisse struct radeon_framebuffer { 530771fe6b9SJerome Glisse struct drm_framebuffer base; 531771fe6b9SJerome Glisse struct drm_gem_object *obj; 532771fe6b9SJerome Glisse }; 533771fe6b9SJerome Glisse 534996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 535996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 5366383cf7dSMario Kleiner 5377062ab67SChristian König struct atom_clock_dividers { 5387062ab67SChristian König u32 post_div; 5397062ab67SChristian König union { 5407062ab67SChristian König struct { 5417062ab67SChristian König #ifdef __BIG_ENDIAN 5427062ab67SChristian König u32 reserved : 6; 5437062ab67SChristian König u32 whole_fb_div : 12; 5447062ab67SChristian König u32 frac_fb_div : 14; 5457062ab67SChristian König #else 5467062ab67SChristian König u32 frac_fb_div : 14; 5477062ab67SChristian König u32 whole_fb_div : 12; 5487062ab67SChristian König u32 reserved : 6; 5497062ab67SChristian König #endif 5507062ab67SChristian König }; 5517062ab67SChristian König u32 fb_div; 5527062ab67SChristian König }; 5537062ab67SChristian König u32 ref_div; 5547062ab67SChristian König bool enable_post_div; 5557062ab67SChristian König bool enable_dithen; 5567062ab67SChristian König u32 vco_mode; 5577062ab67SChristian König u32 real_clock; 5589219ed65SAlex Deucher /* added for CI */ 5599219ed65SAlex Deucher u32 post_divider; 5609219ed65SAlex Deucher u32 flags; 5617062ab67SChristian König }; 5627062ab67SChristian König 563eaa778afSAlex Deucher struct atom_mpll_param { 564eaa778afSAlex Deucher union { 565eaa778afSAlex Deucher struct { 566eaa778afSAlex Deucher #ifdef __BIG_ENDIAN 567eaa778afSAlex Deucher u32 reserved : 8; 568eaa778afSAlex Deucher u32 clkfrac : 12; 569eaa778afSAlex Deucher u32 clkf : 12; 570eaa778afSAlex Deucher #else 571eaa778afSAlex Deucher u32 clkf : 12; 572eaa778afSAlex Deucher u32 clkfrac : 12; 573eaa778afSAlex Deucher u32 reserved : 8; 574eaa778afSAlex Deucher #endif 575eaa778afSAlex Deucher }; 576eaa778afSAlex Deucher u32 fb_div; 577eaa778afSAlex Deucher }; 578eaa778afSAlex Deucher u32 post_div; 579eaa778afSAlex Deucher u32 bwcntl; 580eaa778afSAlex Deucher u32 dll_speed; 581eaa778afSAlex Deucher u32 vco_mode; 582eaa778afSAlex Deucher u32 yclk_sel; 583eaa778afSAlex Deucher u32 qdr; 584eaa778afSAlex Deucher u32 half_rate; 585eaa778afSAlex Deucher }; 586eaa778afSAlex Deucher 587ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR5 0x50 588ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR4 0x40 589ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR3 0x30 590ae5b0abbSAlex Deucher #define MEM_TYPE_DDR2 0x20 591ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR1 0x10 592ae5b0abbSAlex Deucher #define MEM_TYPE_DDR3 0xb0 593ae5b0abbSAlex Deucher #define MEM_TYPE_MASK 0xf0 594ae5b0abbSAlex Deucher 595ae5b0abbSAlex Deucher struct atom_memory_info { 596ae5b0abbSAlex Deucher u8 mem_vendor; 597ae5b0abbSAlex Deucher u8 mem_type; 598ae5b0abbSAlex Deucher }; 599ae5b0abbSAlex Deucher 600ae5b0abbSAlex Deucher #define MAX_AC_TIMING_ENTRIES 16 601ae5b0abbSAlex Deucher 602ae5b0abbSAlex Deucher struct atom_memory_clock_range_table 603ae5b0abbSAlex Deucher { 604ae5b0abbSAlex Deucher u8 num_entries; 605ae5b0abbSAlex Deucher u8 rsv[3]; 606ae5b0abbSAlex Deucher u32 mclk[MAX_AC_TIMING_ENTRIES]; 607ae5b0abbSAlex Deucher }; 608ae5b0abbSAlex Deucher 609ae5b0abbSAlex Deucher #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 610ae5b0abbSAlex Deucher #define VBIOS_MAX_AC_TIMING_ENTRIES 20 611ae5b0abbSAlex Deucher 612ae5b0abbSAlex Deucher struct atom_mc_reg_entry { 613ae5b0abbSAlex Deucher u32 mclk_max; 614ae5b0abbSAlex Deucher u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 615ae5b0abbSAlex Deucher }; 616ae5b0abbSAlex Deucher 617ae5b0abbSAlex Deucher struct atom_mc_register_address { 618ae5b0abbSAlex Deucher u16 s1; 619ae5b0abbSAlex Deucher u8 pre_reg_data; 620ae5b0abbSAlex Deucher }; 621ae5b0abbSAlex Deucher 622ae5b0abbSAlex Deucher struct atom_mc_reg_table { 623ae5b0abbSAlex Deucher u8 last; 624ae5b0abbSAlex Deucher u8 num_entries; 625ae5b0abbSAlex Deucher struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 626ae5b0abbSAlex Deucher struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 627ae5b0abbSAlex Deucher }; 628ae5b0abbSAlex Deucher 629ae5b0abbSAlex Deucher #define MAX_VOLTAGE_ENTRIES 32 630ae5b0abbSAlex Deucher 631ae5b0abbSAlex Deucher struct atom_voltage_table_entry 632ae5b0abbSAlex Deucher { 633ae5b0abbSAlex Deucher u16 value; 634ae5b0abbSAlex Deucher u32 smio_low; 635ae5b0abbSAlex Deucher }; 636ae5b0abbSAlex Deucher 637ae5b0abbSAlex Deucher struct atom_voltage_table 638ae5b0abbSAlex Deucher { 639ae5b0abbSAlex Deucher u32 count; 640ae5b0abbSAlex Deucher u32 mask_low; 64165171944SAlex Deucher u32 phase_delay; 642ae5b0abbSAlex Deucher struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 643ae5b0abbSAlex Deucher }; 644ae5b0abbSAlex Deucher 645a38eab52SRashika Kheria 646a38eab52SRashika Kheria extern void 647a38eab52SRashika Kheria radeon_add_atom_connector(struct drm_device *dev, 648a38eab52SRashika Kheria uint32_t connector_id, 649a38eab52SRashika Kheria uint32_t supported_device, 650a38eab52SRashika Kheria int connector_type, 651a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 652a38eab52SRashika Kheria uint32_t igp_lane_info, 653a38eab52SRashika Kheria uint16_t connector_object_id, 654a38eab52SRashika Kheria struct radeon_hpd *hpd, 655a38eab52SRashika Kheria struct radeon_router *router); 656a38eab52SRashika Kheria extern void 657a38eab52SRashika Kheria radeon_add_legacy_connector(struct drm_device *dev, 658a38eab52SRashika Kheria uint32_t connector_id, 659a38eab52SRashika Kheria uint32_t supported_device, 660a38eab52SRashika Kheria int connector_type, 661a38eab52SRashika Kheria struct radeon_i2c_bus_rec *i2c_bus, 662a38eab52SRashika Kheria uint16_t connector_object_id, 663a38eab52SRashika Kheria struct radeon_hpd *hpd); 6640091fc13SRashika Kheria extern uint32_t 6650091fc13SRashika Kheria radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 6660091fc13SRashika Kheria uint8_t dac); 6670091fc13SRashika Kheria extern void radeon_link_encoder_connector(struct drm_device *dev); 668a38eab52SRashika Kheria 669d79766faSAlex Deucher extern enum radeon_tv_std 670d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 671d79766faSAlex Deucher extern enum radeon_tv_std 672d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 6734a6369e9SAlex Deucher extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 6742abba66eSAlex Deucher u16 *vddc, u16 *vddci, u16 *mvdd); 675d79766faSAlex Deucher 67684ac68e0SAlex Deucher extern void 67784ac68e0SAlex Deucher radeon_combios_connected_scratch_regs(struct drm_connector *connector, 67884ac68e0SAlex Deucher struct drm_encoder *encoder, 67984ac68e0SAlex Deucher bool connected); 68084ac68e0SAlex Deucher extern void 68184ac68e0SAlex Deucher radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 68284ac68e0SAlex Deucher struct drm_encoder *encoder, 68384ac68e0SAlex Deucher bool connected); 68484ac68e0SAlex Deucher 6855b1714d3SAlex Deucher extern struct drm_connector * 6865b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 6879aa59993SAlex Deucher extern struct drm_connector * 6889aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 6899aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 6909aa59993SAlex Deucher u32 pixel_clock); 6915b1714d3SAlex Deucher 6921d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 6931d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 694d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 695eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 696d7fa8bb3SAlex Deucher 697377bd8a9SAlex Deucher extern struct edid *radeon_connector_edid(struct drm_connector *connector); 698377bd8a9SAlex Deucher 699d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 700224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 7015801ead6SAlex Deucher struct drm_display_mode *mode); 7025801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 703e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 704224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 7055801ead6SAlex Deucher struct drm_connector *connector); 706d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 7074143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 7089fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 709386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 710386d4d75SAlex Deucher struct drm_connector *connector); 7112953da15SAlex Deucher extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 7122953da15SAlex Deucher u8 power_state); 713496263bfSAlex Deucher extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 714558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 715ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 716f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 7175801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 7185801ead6SAlex Deucher int action, uint8_t lane_num, 7195801ead6SAlex Deucher uint8_t lane_set); 720591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 7213f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 7224cf3b494SRashika Kheria void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 723746c1aa4SDave Airlie 724f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 725f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 726f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 727f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 728f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 729f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 730f376b94fSAlex Deucher const char *name); 731f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 732f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 733771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 734771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 735771fe6b9SJerome Glisse const char *name); 736771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 7375a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 738fcec570bSAlex Deucher u8 slave_addr, 739fcec570bSAlex Deucher u8 addr, 740fcec570bSAlex Deucher u8 *val); 7415a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 742fcec570bSAlex Deucher u8 slave_addr, 743fcec570bSAlex Deucher u8 addr, 744fcec570bSAlex Deucher u8 val); 745fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 746fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 7470a9069d3SNiels Ole Salscheider extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 748771fe6b9SJerome Glisse 749ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 750ba032a58SAlex Deucher struct radeon_atom_ss *ss, 751ba032a58SAlex Deucher int id); 752ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 753ba032a58SAlex Deucher struct radeon_atom_ss *ss, 754ba032a58SAlex Deucher int id, u32 clock); 75509e619c0SAlex Deucher extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 75609e619c0SAlex Deucher u8 id); 757ba032a58SAlex Deucher 758f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 759771fe6b9SJerome Glisse uint64_t freq, 760771fe6b9SJerome Glisse uint32_t *dot_clock_p, 761771fe6b9SJerome Glisse uint32_t *fb_div_p, 762771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 763771fe6b9SJerome Glisse uint32_t *ref_div_p, 764fc10332bSAlex Deucher uint32_t *post_div_p); 765771fe6b9SJerome Glisse 766f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 767f523f74eSAlex Deucher u32 freq, 768f523f74eSAlex Deucher u32 *dot_clock_p, 769f523f74eSAlex Deucher u32 *fb_div_p, 770f523f74eSAlex Deucher u32 *frac_fb_div_p, 771f523f74eSAlex Deucher u32 *ref_div_p, 772f523f74eSAlex Deucher u32 *post_div_p); 773f523f74eSAlex Deucher 7741f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 7751f3b6a45SDave Airlie 776771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 777771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 778771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 779771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 780771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 78199999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 78232f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 783771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 7842dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 7854ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 786d740a933SAlex Deucher extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 787771fe6b9SJerome Glisse 788771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 789771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 790771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 7914dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 7924dd19b0dSChris Ball struct drm_framebuffer *fb, 79321c74a8eSJason Wessel int x, int y, 79421c74a8eSJason Wessel enum mode_set_atomic state); 795771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 796771fe6b9SJerome Glisse struct drm_display_mode *mode, 797771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 798771fe6b9SJerome Glisse int x, int y, 799771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 800771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 801771fe6b9SJerome Glisse 802771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 803771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 8044dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 8054dd19b0dSChris Ball struct drm_framebuffer *fb, 80621c74a8eSJason Wessel int x, int y, 80721c74a8eSJason Wessel enum mode_set_atomic state); 8084dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 8094dd19b0dSChris Ball struct drm_framebuffer *fb, 8104dd19b0dSChris Ball int x, int y, int atomic); 81178b1a601SMichel Dänzer extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 812771fe6b9SJerome Glisse struct drm_file *file_priv, 813771fe6b9SJerome Glisse uint32_t handle, 814771fe6b9SJerome Glisse uint32_t width, 81578b1a601SMichel Dänzer uint32_t height, 81678b1a601SMichel Dänzer int32_t hot_x, 81778b1a601SMichel Dänzer int32_t hot_y); 818771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 819771fe6b9SJerome Glisse int x, int y); 8206d3759faSMichel Dänzer extern void radeon_cursor_reset(struct drm_crtc *crtc); 821771fe6b9SJerome Glisse 822f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 823abca9e45SVille Syrjälä unsigned int flags, 824d47abc58SMario Kleiner int *vpos, int *hpos, ktime_t *stime, 825d47abc58SMario Kleiner ktime_t *etime); 8266383cf7dSMario Kleiner 8273c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 8283c537889SAlex Deucher extern struct edid * 829c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 830771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 831771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 832771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 833771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 834fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 835445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 836fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 837445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 838fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 839445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 840fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 841fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 842fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 843fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 8446fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 8456fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 8466fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 8476fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 848771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 849771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 850771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 851771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 852771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 853771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 854771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 855fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 856fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 857771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 858771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 859771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 860771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 861f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 862f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 863771fe6b9SJerome Glisse extern void 864771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 865771fe6b9SJerome Glisse extern void 866771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 867771fe6b9SJerome Glisse extern void 868771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 869771fe6b9SJerome Glisse extern void 870771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 871771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 872771fe6b9SJerome Glisse u16 blue, int regno); 873b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 874b8c00ac5SDave Airlie u16 *blue, int regno); 875aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 87638651674SDave Airlie struct radeon_framebuffer *rfb, 877308e5bcbSJesse Barnes struct drm_mode_fb_cmd2 *mode_cmd, 878771fe6b9SJerome Glisse struct drm_gem_object *obj); 879771fe6b9SJerome Glisse 880771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 881771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 882771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 883771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 884771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 885771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 886771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 887771fe6b9SJerome Glisse 888771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 889771fe6b9SJerome Glisse 890771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 891771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 892771fe6b9SJerome Glisse 893771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 894771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 895771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 896c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 897e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 898c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 8993515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 9003515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 9014ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 902771fe6b9SJerome Glisse 9034ce001abSDave Airlie /* legacy tv */ 9044ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 9054ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 9064ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 9074ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 9084ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 9094ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 9104ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 9114ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 9124ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 9134ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 9144ce001abSDave Airlie struct drm_display_mode *mode, 9154ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 91638651674SDave Airlie 917134b480fSAlex Deucher /* fmt blocks */ 918134b480fSAlex Deucher void avivo_program_fmt(struct drm_encoder *encoder); 919134b480fSAlex Deucher void dce3_program_fmt(struct drm_encoder *encoder); 920134b480fSAlex Deucher void dce4_program_fmt(struct drm_encoder *encoder); 921134b480fSAlex Deucher void dce8_program_fmt(struct drm_encoder *encoder); 922134b480fSAlex Deucher 92338651674SDave Airlie /* fbdev layer */ 92438651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 92538651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 92638651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 92738651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 928eb1f8e4fSDave Airlie 929eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 9306f34be50SAlex Deucher 9311a0e7918SChristian König void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 9326f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 9336f34be50SAlex Deucher 934ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 935771fe6b9SJerome Glisse #endif 936