1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33771fe6b9SJerome Glisse #include <drm_crtc.h> 34771fe6b9SJerome Glisse #include <drm_mode.h> 35771fe6b9SJerome Glisse #include <drm_edid.h> 36746c1aa4SDave Airlie #include <drm_dp_helper.h> 3768adac5eSBen Skeggs #include <drm_fixed.h> 3821c74a8eSJason Wessel #include <drm_crtc_helper.h> 39771fe6b9SJerome Glisse #include <linux/i2c.h> 40771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 41c93bb85bSJerome Glisse 4238651674SDave Airlie struct radeon_bo; 43c93bb85bSJerome Glisse struct radeon_device; 44771fe6b9SJerome Glisse 45771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49771fe6b9SJerome Glisse 50771fe6b9SJerome Glisse enum radeon_rmx_type { 51771fe6b9SJerome Glisse RMX_OFF, 52771fe6b9SJerome Glisse RMX_FULL, 53771fe6b9SJerome Glisse RMX_CENTER, 54771fe6b9SJerome Glisse RMX_ASPECT 55771fe6b9SJerome Glisse }; 56771fe6b9SJerome Glisse 57771fe6b9SJerome Glisse enum radeon_tv_std { 58771fe6b9SJerome Glisse TV_STD_NTSC, 59771fe6b9SJerome Glisse TV_STD_PAL, 60771fe6b9SJerome Glisse TV_STD_PAL_M, 61771fe6b9SJerome Glisse TV_STD_PAL_60, 62771fe6b9SJerome Glisse TV_STD_NTSC_J, 63771fe6b9SJerome Glisse TV_STD_SCART_PAL, 64771fe6b9SJerome Glisse TV_STD_SECAM, 65771fe6b9SJerome Glisse TV_STD_PAL_CN, 66d79766faSAlex Deucher TV_STD_PAL_N, 67771fe6b9SJerome Glisse }; 68771fe6b9SJerome Glisse 695b1714d3SAlex Deucher enum radeon_underscan_type { 705b1714d3SAlex Deucher UNDERSCAN_OFF, 715b1714d3SAlex Deucher UNDERSCAN_ON, 725b1714d3SAlex Deucher UNDERSCAN_AUTO, 735b1714d3SAlex Deucher }; 745b1714d3SAlex Deucher 758e36ed00SAlex Deucher enum radeon_hpd_id { 768e36ed00SAlex Deucher RADEON_HPD_1 = 0, 778e36ed00SAlex Deucher RADEON_HPD_2, 788e36ed00SAlex Deucher RADEON_HPD_3, 798e36ed00SAlex Deucher RADEON_HPD_4, 808e36ed00SAlex Deucher RADEON_HPD_5, 818e36ed00SAlex Deucher RADEON_HPD_6, 828e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 838e36ed00SAlex Deucher }; 848e36ed00SAlex Deucher 85f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 86f376b94fSAlex Deucher 879b9fe724SAlex Deucher /* radeon gpio-based i2c 889b9fe724SAlex Deucher * 1. "mask" reg and bits 899b9fe724SAlex Deucher * grabs the gpio pins for software use 909b9fe724SAlex Deucher * 0=not held 1=held 919b9fe724SAlex Deucher * 2. "a" reg and bits 929b9fe724SAlex Deucher * output pin value 939b9fe724SAlex Deucher * 0=low 1=high 949b9fe724SAlex Deucher * 3. "en" reg and bits 959b9fe724SAlex Deucher * sets the pin direction 969b9fe724SAlex Deucher * 0=input 1=output 979b9fe724SAlex Deucher * 4. "y" reg and bits 989b9fe724SAlex Deucher * input pin value 999b9fe724SAlex Deucher * 0=low 1=high 1009b9fe724SAlex Deucher */ 101771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 102771fe6b9SJerome Glisse bool valid; 1036a93cb25SAlex Deucher /* id used by atom */ 1046a93cb25SAlex Deucher uint8_t i2c_id; 105bcc1c2a1SAlex Deucher /* id used by atom */ 1068e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1076a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1086a93cb25SAlex Deucher bool hw_capable; 1096a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1106a93cb25SAlex Deucher bool mm_i2c; 1116a93cb25SAlex Deucher /* regs and bits */ 112771fe6b9SJerome Glisse uint32_t mask_clk_reg; 113771fe6b9SJerome Glisse uint32_t mask_data_reg; 114771fe6b9SJerome Glisse uint32_t a_clk_reg; 115771fe6b9SJerome Glisse uint32_t a_data_reg; 1169b9fe724SAlex Deucher uint32_t en_clk_reg; 1179b9fe724SAlex Deucher uint32_t en_data_reg; 1189b9fe724SAlex Deucher uint32_t y_clk_reg; 1199b9fe724SAlex Deucher uint32_t y_data_reg; 120771fe6b9SJerome Glisse uint32_t mask_clk_mask; 121771fe6b9SJerome Glisse uint32_t mask_data_mask; 122771fe6b9SJerome Glisse uint32_t a_clk_mask; 123771fe6b9SJerome Glisse uint32_t a_data_mask; 1249b9fe724SAlex Deucher uint32_t en_clk_mask; 1259b9fe724SAlex Deucher uint32_t en_data_mask; 1269b9fe724SAlex Deucher uint32_t y_clk_mask; 1279b9fe724SAlex Deucher uint32_t y_data_mask; 128771fe6b9SJerome Glisse }; 129771fe6b9SJerome Glisse 130771fe6b9SJerome Glisse struct radeon_tmds_pll { 131771fe6b9SJerome Glisse uint32_t freq; 132771fe6b9SJerome Glisse uint32_t value; 133771fe6b9SJerome Glisse }; 134771fe6b9SJerome Glisse 135771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 136771fe6b9SJerome Glisse 1377c27f87dSAlex Deucher /* pll flags */ 138771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 139771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 140771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 141771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 143771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 144771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 147771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 148771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 149d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 150fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15186cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 152f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 153771fe6b9SJerome Glisse 154771fe6b9SJerome Glisse struct radeon_pll { 155fc10332bSAlex Deucher /* reference frequency */ 156fc10332bSAlex Deucher uint32_t reference_freq; 157fc10332bSAlex Deucher 158fc10332bSAlex Deucher /* fixed dividers */ 159fc10332bSAlex Deucher uint32_t reference_div; 160fc10332bSAlex Deucher uint32_t post_div; 161fc10332bSAlex Deucher 162fc10332bSAlex Deucher /* pll in/out limits */ 163771fe6b9SJerome Glisse uint32_t pll_in_min; 164771fe6b9SJerome Glisse uint32_t pll_in_max; 165771fe6b9SJerome Glisse uint32_t pll_out_min; 166771fe6b9SJerome Glisse uint32_t pll_out_max; 16786cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 16886cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 169fc10332bSAlex Deucher uint32_t best_vco; 170771fe6b9SJerome Glisse 171fc10332bSAlex Deucher /* divider limits */ 172771fe6b9SJerome Glisse uint32_t min_ref_div; 173771fe6b9SJerome Glisse uint32_t max_ref_div; 174771fe6b9SJerome Glisse uint32_t min_post_div; 175771fe6b9SJerome Glisse uint32_t max_post_div; 176771fe6b9SJerome Glisse uint32_t min_feedback_div; 177771fe6b9SJerome Glisse uint32_t max_feedback_div; 178771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 179771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 180fc10332bSAlex Deucher 181fc10332bSAlex Deucher /* flags for the current clock */ 182fc10332bSAlex Deucher uint32_t flags; 183fc10332bSAlex Deucher 184fc10332bSAlex Deucher /* pll id */ 185fc10332bSAlex Deucher uint32_t id; 186771fe6b9SJerome Glisse }; 187771fe6b9SJerome Glisse 188771fe6b9SJerome Glisse struct radeon_i2c_chan { 189771fe6b9SJerome Glisse struct i2c_adapter adapter; 190746c1aa4SDave Airlie struct drm_device *dev; 191746c1aa4SDave Airlie union { 192ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 193746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 194746c1aa4SDave Airlie } algo; 195771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 196771fe6b9SJerome Glisse }; 197771fe6b9SJerome Glisse 198771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 199771fe6b9SJerome Glisse enum radeon_connector_table { 200aa74fbb4SAlex Deucher CT_NONE = 0, 201771fe6b9SJerome Glisse CT_GENERIC, 202771fe6b9SJerome Glisse CT_IBOOK, 203771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 204771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 205771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 206771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 207771fe6b9SJerome Glisse CT_MINI_INTERNAL, 208771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 209771fe6b9SJerome Glisse CT_EMAC, 21076a7142aSDave Airlie CT_RN50_POWER, 211aa74fbb4SAlex Deucher CT_MAC_X800, 2129fad321aSAlex Deucher CT_MAC_G5_9600, 2136a556039SAlex Deucher CT_SAM440EP 214771fe6b9SJerome Glisse }; 215771fe6b9SJerome Glisse 216fcec570bSAlex Deucher enum radeon_dvo_chip { 217fcec570bSAlex Deucher DVO_SIL164, 218fcec570bSAlex Deucher DVO_SIL1178, 219fcec570bSAlex Deucher }; 220fcec570bSAlex Deucher 2218be48d92SDave Airlie struct radeon_fbdev; 22238651674SDave Airlie 2230783986aSAlex Deucher struct radeon_afmt { 2240783986aSAlex Deucher bool enabled; 2250783986aSAlex Deucher int offset; 2260783986aSAlex Deucher bool last_buffer_filled_status; 2270783986aSAlex Deucher int id; 2280783986aSAlex Deucher }; 2290783986aSAlex Deucher 230771fe6b9SJerome Glisse struct radeon_mode_info { 231771fe6b9SJerome Glisse struct atom_context *atom_context; 23261c4b24bSMathias Fröhlich struct card_info *atom_card_info; 233771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 234771fe6b9SJerome Glisse bool mode_config_initialized; 235bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 2360783986aSAlex Deucher struct radeon_afmt *afmt[6]; 237445282dbSDave Airlie /* DVI-I properties */ 238445282dbSDave Airlie struct drm_property *coherent_mode_property; 239445282dbSDave Airlie /* DAC enable load detect */ 240445282dbSDave Airlie struct drm_property *load_detect_property; 2415b1714d3SAlex Deucher /* TV standard */ 242445282dbSDave Airlie struct drm_property *tv_std_property; 243445282dbSDave Airlie /* legacy TMDS PLL detect */ 244445282dbSDave Airlie struct drm_property *tmds_pll_property; 2455b1714d3SAlex Deucher /* underscan */ 2465b1714d3SAlex Deucher struct drm_property *underscan_property; 2475bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2485bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2493c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2503c537889SAlex Deucher struct edid *bios_hardcoded_edid; 251fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 25238651674SDave Airlie 25338651674SDave Airlie /* pointer to fbdev info structure */ 2548be48d92SDave Airlie struct radeon_fbdev *rfbdev; 255af7912e5SAlex Deucher /* firmware flags */ 256af7912e5SAlex Deucher u16 firmware_flags; 257c93bb85bSJerome Glisse }; 258c93bb85bSJerome Glisse 25991030880SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 26091030880SAlex Deucher 26191030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 26291030880SAlex Deucher 26391030880SAlex Deucher struct radeon_backlight_privdata { 26491030880SAlex Deucher struct radeon_encoder *encoder; 26591030880SAlex Deucher uint8_t negative; 26691030880SAlex Deucher }; 26791030880SAlex Deucher 26891030880SAlex Deucher #endif 26991030880SAlex Deucher 2704ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2714ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2724ce001abSDave Airlie 2734ce001abSDave Airlie /* need to store these as reading 2744ce001abSDave Airlie back code tables is excessive */ 2754ce001abSDave Airlie struct radeon_tv_regs { 2764ce001abSDave Airlie uint32_t tv_uv_adr; 2774ce001abSDave Airlie uint32_t timing_cntl; 2784ce001abSDave Airlie uint32_t hrestart; 2794ce001abSDave Airlie uint32_t vrestart; 2804ce001abSDave Airlie uint32_t frestart; 2814ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2824ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2834ce001abSDave Airlie }; 2844ce001abSDave Airlie 28519eca43eSAlex Deucher struct radeon_atom_ss { 28619eca43eSAlex Deucher uint16_t percentage; 28719eca43eSAlex Deucher uint8_t type; 28819eca43eSAlex Deucher uint16_t step; 28919eca43eSAlex Deucher uint8_t delay; 29019eca43eSAlex Deucher uint8_t range; 29119eca43eSAlex Deucher uint8_t refdiv; 29219eca43eSAlex Deucher /* asic_ss */ 29319eca43eSAlex Deucher uint16_t rate; 29419eca43eSAlex Deucher uint16_t amount; 29519eca43eSAlex Deucher }; 29619eca43eSAlex Deucher 297771fe6b9SJerome Glisse struct radeon_crtc { 298771fe6b9SJerome Glisse struct drm_crtc base; 299771fe6b9SJerome Glisse int crtc_id; 300771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 301771fe6b9SJerome Glisse bool enabled; 302771fe6b9SJerome Glisse bool can_tile; 3036c0ae2abSAlex Deucher bool in_mode_set; 304771fe6b9SJerome Glisse uint32_t crtc_offset; 305771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 306771fe6b9SJerome Glisse uint64_t cursor_addr; 307771fe6b9SJerome Glisse int cursor_width; 308771fe6b9SJerome Glisse int cursor_height; 3094162338aSDave Airlie uint32_t legacy_display_base_addr; 310c836e862SAlex Deucher uint32_t legacy_cursor_offset; 311c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3125b1714d3SAlex Deucher u8 h_border; 3135b1714d3SAlex Deucher u8 v_border; 314c93bb85bSJerome Glisse fixed20_12 vsc; 315c93bb85bSJerome Glisse fixed20_12 hsc; 316de2103e4SAlex Deucher struct drm_display_mode native_mode; 317bcc1c2a1SAlex Deucher int pll_id; 3186f34be50SAlex Deucher /* page flipping */ 3196f34be50SAlex Deucher struct radeon_unpin_work *unpin_work; 3206f34be50SAlex Deucher int deferred_flip_completion; 32119eca43eSAlex Deucher /* pll sharing */ 32219eca43eSAlex Deucher struct radeon_atom_ss ss; 32319eca43eSAlex Deucher bool ss_enabled; 32419eca43eSAlex Deucher u32 adjusted_clock; 32519eca43eSAlex Deucher int bpc; 32619eca43eSAlex Deucher u32 pll_reference_div; 32719eca43eSAlex Deucher u32 pll_post_div; 32819eca43eSAlex Deucher u32 pll_flags; 329771fe6b9SJerome Glisse }; 330771fe6b9SJerome Glisse 331771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 332771fe6b9SJerome Glisse /* legacy primary dac */ 333771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 334771fe6b9SJerome Glisse }; 335771fe6b9SJerome Glisse 336771fe6b9SJerome Glisse struct radeon_encoder_lvds { 337771fe6b9SJerome Glisse /* legacy lvds */ 338771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 339771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 340771fe6b9SJerome Glisse uint8_t panel_digon_delay; 341771fe6b9SJerome Glisse uint8_t panel_blon_delay; 342771fe6b9SJerome Glisse uint16_t panel_ref_divider; 343771fe6b9SJerome Glisse uint8_t panel_post_divider; 344771fe6b9SJerome Glisse uint16_t panel_fb_divider; 345771fe6b9SJerome Glisse bool use_bios_dividers; 346771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 347771fe6b9SJerome Glisse /* panel mode */ 348de2103e4SAlex Deucher struct drm_display_mode native_mode; 34963ec0119SMichel Dänzer struct backlight_device *bl_dev; 35063ec0119SMichel Dänzer int dpms_mode; 35163ec0119SMichel Dänzer uint8_t backlight_level; 352771fe6b9SJerome Glisse }; 353771fe6b9SJerome Glisse 354771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 355771fe6b9SJerome Glisse /* legacy tv dac */ 356771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 357771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 358771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 359771fe6b9SJerome Glisse 3604ce001abSDave Airlie int h_pos; 3614ce001abSDave Airlie int v_pos; 3624ce001abSDave Airlie int h_size; 3634ce001abSDave Airlie int supported_tv_stds; 3644ce001abSDave Airlie bool tv_on; 365771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3664ce001abSDave Airlie struct radeon_tv_regs tv; 367771fe6b9SJerome Glisse }; 368771fe6b9SJerome Glisse 369771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 370771fe6b9SJerome Glisse /* legacy int tmds */ 371771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 372771fe6b9SJerome Glisse }; 373771fe6b9SJerome Glisse 374fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 375fcec570bSAlex Deucher /* tmds over dvo */ 376fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 377fcec570bSAlex Deucher uint8_t slave_addr; 378fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 379fcec570bSAlex Deucher }; 380fcec570bSAlex Deucher 381ebbe1cb9SAlex Deucher /* spread spectrum */ 382771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 3835137ee94SAlex Deucher bool linkb; 384771fe6b9SJerome Glisse /* atom dig */ 385771fe6b9SJerome Glisse bool coherent_mode; 386ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 387ba032a58SAlex Deucher /* atom lvds/edp */ 388ba032a58SAlex Deucher uint32_t lcd_misc; 389771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 390ba032a58SAlex Deucher uint32_t lcd_ss_id; 391771fe6b9SJerome Glisse /* panel mode */ 392de2103e4SAlex Deucher struct drm_display_mode native_mode; 39363ec0119SMichel Dänzer struct backlight_device *bl_dev; 39463ec0119SMichel Dänzer int dpms_mode; 39563ec0119SMichel Dänzer uint8_t backlight_level; 396386d4d75SAlex Deucher int panel_mode; 3970783986aSAlex Deucher struct radeon_afmt *afmt; 398771fe6b9SJerome Glisse }; 399771fe6b9SJerome Glisse 4004ce001abSDave Airlie struct radeon_encoder_atom_dac { 4014ce001abSDave Airlie enum radeon_tv_std tv_std; 4024ce001abSDave Airlie }; 4034ce001abSDave Airlie 404771fe6b9SJerome Glisse struct radeon_encoder { 405771fe6b9SJerome Glisse struct drm_encoder base; 4065137ee94SAlex Deucher uint32_t encoder_enum; 407771fe6b9SJerome Glisse uint32_t encoder_id; 408771fe6b9SJerome Glisse uint32_t devices; 4094ce001abSDave Airlie uint32_t active_device; 410771fe6b9SJerome Glisse uint32_t flags; 411771fe6b9SJerome Glisse uint32_t pixel_clock; 412771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4135b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4145bccf5e3SMarius Gröger uint32_t underscan_hborder; 4155bccf5e3SMarius Gröger uint32_t underscan_vborder; 416de2103e4SAlex Deucher struct drm_display_mode native_mode; 417771fe6b9SJerome Glisse void *enc_priv; 41858bd0863SChristian König int audio_polling_active; 4193e4b9982SAlex Deucher bool is_ext_encoder; 42036868bdaSAlex Deucher u16 caps; 421771fe6b9SJerome Glisse }; 422771fe6b9SJerome Glisse 423771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 424771fe6b9SJerome Glisse uint32_t igp_lane_info; 4254143e919SAlex Deucher /* displayport */ 426746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 4271a66c95aSAlex Deucher u8 dpcd[8]; 4284143e919SAlex Deucher u8 dp_sink_type; 4295801ead6SAlex Deucher int dp_clock; 4305801ead6SAlex Deucher int dp_lane_count; 4318b834852SAlex Deucher bool edp_on; 432771fe6b9SJerome Glisse }; 433771fe6b9SJerome Glisse 434eed45b30SAlex Deucher struct radeon_gpio_rec { 435eed45b30SAlex Deucher bool valid; 436eed45b30SAlex Deucher u8 id; 437eed45b30SAlex Deucher u32 reg; 438eed45b30SAlex Deucher u32 mask; 439eed45b30SAlex Deucher }; 440eed45b30SAlex Deucher 441eed45b30SAlex Deucher struct radeon_hpd { 442eed45b30SAlex Deucher enum radeon_hpd_id hpd; 443eed45b30SAlex Deucher u8 plugged_state; 444eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 445eed45b30SAlex Deucher }; 446eed45b30SAlex Deucher 44726b5bc98SAlex Deucher struct radeon_router { 44826b5bc98SAlex Deucher u32 router_id; 44926b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 45026b5bc98SAlex Deucher u8 i2c_addr; 451fb939dfcSAlex Deucher /* i2c mux */ 452fb939dfcSAlex Deucher bool ddc_valid; 453fb939dfcSAlex Deucher u8 ddc_mux_type; 454fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 455fb939dfcSAlex Deucher u8 ddc_mux_state; 456fb939dfcSAlex Deucher /* clock/data mux */ 457fb939dfcSAlex Deucher bool cd_valid; 458fb939dfcSAlex Deucher u8 cd_mux_type; 459fb939dfcSAlex Deucher u8 cd_mux_control_pin; 460fb939dfcSAlex Deucher u8 cd_mux_state; 46126b5bc98SAlex Deucher }; 46226b5bc98SAlex Deucher 463771fe6b9SJerome Glisse struct radeon_connector { 464771fe6b9SJerome Glisse struct drm_connector base; 465771fe6b9SJerome Glisse uint32_t connector_id; 466771fe6b9SJerome Glisse uint32_t devices; 467771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 4685b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 4690294cf4fSAlex Deucher bool shared_ddc; 4704ce001abSDave Airlie bool use_digital; 4714ce001abSDave Airlie /* we need to mind the EDID between detect 4724ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 4734ce001abSDave Airlie struct edid *edid; 474771fe6b9SJerome Glisse void *con_priv; 475445282dbSDave Airlie bool dac_load_detect; 476d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 477b75fad06SAlex Deucher uint16_t connector_object_id; 478eed45b30SAlex Deucher struct radeon_hpd hpd; 47926b5bc98SAlex Deucher struct radeon_router router; 48026b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 481771fe6b9SJerome Glisse }; 482771fe6b9SJerome Glisse 483771fe6b9SJerome Glisse struct radeon_framebuffer { 484771fe6b9SJerome Glisse struct drm_framebuffer base; 485771fe6b9SJerome Glisse struct drm_gem_object *obj; 486771fe6b9SJerome Glisse }; 487771fe6b9SJerome Glisse 488996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 489996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 4906383cf7dSMario Kleiner 491d79766faSAlex Deucher extern enum radeon_tv_std 492d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 493d79766faSAlex Deucher extern enum radeon_tv_std 494d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 495d79766faSAlex Deucher 4965b1714d3SAlex Deucher extern struct drm_connector * 4975b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 4989aa59993SAlex Deucher extern struct drm_connector * 4999aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 5009aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 5019aa59993SAlex Deucher u32 pixel_clock); 5025b1714d3SAlex Deucher 5031d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 5041d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 505d7fa8bb3SAlex Deucher extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 506d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 507eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 508d7fa8bb3SAlex Deucher 509d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 510224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 5115801ead6SAlex Deucher struct drm_display_mode *mode); 5125801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 513e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 514224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 5155801ead6SAlex Deucher struct drm_connector *connector); 516d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 5174143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 5189fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 519386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 520386d4d75SAlex Deucher struct drm_connector *connector); 521558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 522ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 523f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 5245801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 5255801ead6SAlex Deucher int action, uint8_t lane_num, 5265801ead6SAlex Deucher uint8_t lane_set); 527591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 5283f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 529746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 530834b2904SAlex Deucher u8 write_byte, u8 *read_byte); 531746c1aa4SDave Airlie 532f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 533f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 534f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 535f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 536f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 537f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 538f376b94fSAlex Deucher const char *name); 539f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 540f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 541746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 5426a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 5436a93cb25SAlex Deucher const char *name); 544771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 545771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 546771fe6b9SJerome Glisse const char *name); 547771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 5485a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 549fcec570bSAlex Deucher u8 slave_addr, 550fcec570bSAlex Deucher u8 addr, 551fcec570bSAlex Deucher u8 *val); 5525a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 553fcec570bSAlex Deucher u8 slave_addr, 554fcec570bSAlex Deucher u8 addr, 555fcec570bSAlex Deucher u8 val); 556fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 557fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 558bc1c4dc3SAlex Deucher extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 559771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 560771fe6b9SJerome Glisse 561771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 562771fe6b9SJerome Glisse 563ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 564ba032a58SAlex Deucher struct radeon_atom_ss *ss, 565ba032a58SAlex Deucher int id); 566ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 567ba032a58SAlex Deucher struct radeon_atom_ss *ss, 568ba032a58SAlex Deucher int id, u32 clock); 569ba032a58SAlex Deucher 570f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 571771fe6b9SJerome Glisse uint64_t freq, 572771fe6b9SJerome Glisse uint32_t *dot_clock_p, 573771fe6b9SJerome Glisse uint32_t *fb_div_p, 574771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 575771fe6b9SJerome Glisse uint32_t *ref_div_p, 576fc10332bSAlex Deucher uint32_t *post_div_p); 577771fe6b9SJerome Glisse 578f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 579f523f74eSAlex Deucher u32 freq, 580f523f74eSAlex Deucher u32 *dot_clock_p, 581f523f74eSAlex Deucher u32 *fb_div_p, 582f523f74eSAlex Deucher u32 *frac_fb_div_p, 583f523f74eSAlex Deucher u32 *ref_div_p, 584f523f74eSAlex Deucher u32 *post_div_p); 585f523f74eSAlex Deucher 5861f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 5871f3b6a45SDave Airlie 588771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 589771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 590771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 591771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 592771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 59399999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 59432f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 595771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 5962dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 5974ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 598771fe6b9SJerome Glisse 599771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 600771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 601771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 6024dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 6034dd19b0dSChris Ball struct drm_framebuffer *fb, 60421c74a8eSJason Wessel int x, int y, 60521c74a8eSJason Wessel enum mode_set_atomic state); 606771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 607771fe6b9SJerome Glisse struct drm_display_mode *mode, 608771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 609771fe6b9SJerome Glisse int x, int y, 610771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 611771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 612771fe6b9SJerome Glisse 613771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 614771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 6154dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 6164dd19b0dSChris Ball struct drm_framebuffer *fb, 61721c74a8eSJason Wessel int x, int y, 61821c74a8eSJason Wessel enum mode_set_atomic state); 6194dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 6204dd19b0dSChris Ball struct drm_framebuffer *fb, 6214dd19b0dSChris Ball int x, int y, int atomic); 622771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 623771fe6b9SJerome Glisse struct drm_file *file_priv, 624771fe6b9SJerome Glisse uint32_t handle, 625771fe6b9SJerome Glisse uint32_t width, 626771fe6b9SJerome Glisse uint32_t height); 627771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 628771fe6b9SJerome Glisse int x, int y); 629771fe6b9SJerome Glisse 630f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 631f5a80209SMario Kleiner int *vpos, int *hpos); 6326383cf7dSMario Kleiner 6333c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 6343c537889SAlex Deucher extern struct edid * 635c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 636771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 637771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 638771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 639771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 640fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 641445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 642fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 643445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 644fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 645445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 646fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 647fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 648fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 649fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 6506fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 6516fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 6526fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 6536fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 654771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 655771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 656771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 657771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 658771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 659771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 660771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 661fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 662fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 663771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 664771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 665771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 666771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 667f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 668f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 669771fe6b9SJerome Glisse extern void 670771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 671771fe6b9SJerome Glisse extern void 672771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 673771fe6b9SJerome Glisse extern void 674771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 675771fe6b9SJerome Glisse extern void 676771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 677771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 678771fe6b9SJerome Glisse u16 blue, int regno); 679b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 680b8c00ac5SDave Airlie u16 *blue, int regno); 681aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 68238651674SDave Airlie struct radeon_framebuffer *rfb, 683308e5bcbSJesse Barnes struct drm_mode_fb_cmd2 *mode_cmd, 684771fe6b9SJerome Glisse struct drm_gem_object *obj); 685771fe6b9SJerome Glisse 686771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 687771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 688771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 689771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 690771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 691771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 692771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 693771fe6b9SJerome Glisse 694771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 695771fe6b9SJerome Glisse 696771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 697771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 698771fe6b9SJerome Glisse 699771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 700771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 701771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 702c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 703e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 704c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 7053515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 7063515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 7074ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 708771fe6b9SJerome Glisse 7094ce001abSDave Airlie /* legacy tv */ 7104ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 7114ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 7124ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 7134ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 7144ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 7154ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 7164ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 7174ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 7184ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 7194ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 7204ce001abSDave Airlie struct drm_display_mode *mode, 7214ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 72238651674SDave Airlie 72338651674SDave Airlie /* fbdev layer */ 72438651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 72538651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 72638651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 72738651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev); 72838651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 729eb1f8e4fSDave Airlie 730eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 7316f34be50SAlex Deucher 7326f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 7336f34be50SAlex Deucher 734ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 735771fe6b9SJerome Glisse #endif 736