1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3771fe6b9SJerome Glisse * VA Linux Systems Inc., Fremont, California. 4771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 5771fe6b9SJerome Glisse * 6771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b9SJerome Glisse * 13771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 15771fe6b9SJerome Glisse * 16771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b9SJerome Glisse * 24771fe6b9SJerome Glisse * Original Authors: 25771fe6b9SJerome Glisse * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26771fe6b9SJerome Glisse * 27771fe6b9SJerome Glisse * Kernel port Author: Dave Airlie 28771fe6b9SJerome Glisse */ 29771fe6b9SJerome Glisse 30771fe6b9SJerome Glisse #ifndef RADEON_MODE_H 31771fe6b9SJerome Glisse #define RADEON_MODE_H 32771fe6b9SJerome Glisse 33760285e7SDavid Howells #include <drm/drm_crtc.h> 34760285e7SDavid Howells #include <drm/drm_edid.h> 35760285e7SDavid Howells #include <drm/drm_dp_helper.h> 36760285e7SDavid Howells #include <drm/drm_fixed.h> 37760285e7SDavid Howells #include <drm/drm_crtc_helper.h> 38771fe6b9SJerome Glisse #include <linux/i2c.h> 39771fe6b9SJerome Glisse #include <linux/i2c-algo-bit.h> 40c93bb85bSJerome Glisse 4138651674SDave Airlie struct radeon_bo; 42c93bb85bSJerome Glisse struct radeon_device; 43771fe6b9SJerome Glisse 44771fe6b9SJerome Glisse #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45771fe6b9SJerome Glisse #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46771fe6b9SJerome Glisse #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47771fe6b9SJerome Glisse #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48771fe6b9SJerome Glisse 49771fe6b9SJerome Glisse enum radeon_rmx_type { 50771fe6b9SJerome Glisse RMX_OFF, 51771fe6b9SJerome Glisse RMX_FULL, 52771fe6b9SJerome Glisse RMX_CENTER, 53771fe6b9SJerome Glisse RMX_ASPECT 54771fe6b9SJerome Glisse }; 55771fe6b9SJerome Glisse 56771fe6b9SJerome Glisse enum radeon_tv_std { 57771fe6b9SJerome Glisse TV_STD_NTSC, 58771fe6b9SJerome Glisse TV_STD_PAL, 59771fe6b9SJerome Glisse TV_STD_PAL_M, 60771fe6b9SJerome Glisse TV_STD_PAL_60, 61771fe6b9SJerome Glisse TV_STD_NTSC_J, 62771fe6b9SJerome Glisse TV_STD_SCART_PAL, 63771fe6b9SJerome Glisse TV_STD_SECAM, 64771fe6b9SJerome Glisse TV_STD_PAL_CN, 65d79766faSAlex Deucher TV_STD_PAL_N, 66771fe6b9SJerome Glisse }; 67771fe6b9SJerome Glisse 685b1714d3SAlex Deucher enum radeon_underscan_type { 695b1714d3SAlex Deucher UNDERSCAN_OFF, 705b1714d3SAlex Deucher UNDERSCAN_ON, 715b1714d3SAlex Deucher UNDERSCAN_AUTO, 725b1714d3SAlex Deucher }; 735b1714d3SAlex Deucher 748e36ed00SAlex Deucher enum radeon_hpd_id { 758e36ed00SAlex Deucher RADEON_HPD_1 = 0, 768e36ed00SAlex Deucher RADEON_HPD_2, 778e36ed00SAlex Deucher RADEON_HPD_3, 788e36ed00SAlex Deucher RADEON_HPD_4, 798e36ed00SAlex Deucher RADEON_HPD_5, 808e36ed00SAlex Deucher RADEON_HPD_6, 818e36ed00SAlex Deucher RADEON_HPD_NONE = 0xff, 828e36ed00SAlex Deucher }; 838e36ed00SAlex Deucher 84f376b94fSAlex Deucher #define RADEON_MAX_I2C_BUS 16 85f376b94fSAlex Deucher 869b9fe724SAlex Deucher /* radeon gpio-based i2c 879b9fe724SAlex Deucher * 1. "mask" reg and bits 889b9fe724SAlex Deucher * grabs the gpio pins for software use 899b9fe724SAlex Deucher * 0=not held 1=held 909b9fe724SAlex Deucher * 2. "a" reg and bits 919b9fe724SAlex Deucher * output pin value 929b9fe724SAlex Deucher * 0=low 1=high 939b9fe724SAlex Deucher * 3. "en" reg and bits 949b9fe724SAlex Deucher * sets the pin direction 959b9fe724SAlex Deucher * 0=input 1=output 969b9fe724SAlex Deucher * 4. "y" reg and bits 979b9fe724SAlex Deucher * input pin value 989b9fe724SAlex Deucher * 0=low 1=high 999b9fe724SAlex Deucher */ 100771fe6b9SJerome Glisse struct radeon_i2c_bus_rec { 101771fe6b9SJerome Glisse bool valid; 1026a93cb25SAlex Deucher /* id used by atom */ 1036a93cb25SAlex Deucher uint8_t i2c_id; 104bcc1c2a1SAlex Deucher /* id used by atom */ 1058e36ed00SAlex Deucher enum radeon_hpd_id hpd; 1066a93cb25SAlex Deucher /* can be used with hw i2c engine */ 1076a93cb25SAlex Deucher bool hw_capable; 1086a93cb25SAlex Deucher /* uses multi-media i2c engine */ 1096a93cb25SAlex Deucher bool mm_i2c; 1106a93cb25SAlex Deucher /* regs and bits */ 111771fe6b9SJerome Glisse uint32_t mask_clk_reg; 112771fe6b9SJerome Glisse uint32_t mask_data_reg; 113771fe6b9SJerome Glisse uint32_t a_clk_reg; 114771fe6b9SJerome Glisse uint32_t a_data_reg; 1159b9fe724SAlex Deucher uint32_t en_clk_reg; 1169b9fe724SAlex Deucher uint32_t en_data_reg; 1179b9fe724SAlex Deucher uint32_t y_clk_reg; 1189b9fe724SAlex Deucher uint32_t y_data_reg; 119771fe6b9SJerome Glisse uint32_t mask_clk_mask; 120771fe6b9SJerome Glisse uint32_t mask_data_mask; 121771fe6b9SJerome Glisse uint32_t a_clk_mask; 122771fe6b9SJerome Glisse uint32_t a_data_mask; 1239b9fe724SAlex Deucher uint32_t en_clk_mask; 1249b9fe724SAlex Deucher uint32_t en_data_mask; 1259b9fe724SAlex Deucher uint32_t y_clk_mask; 1269b9fe724SAlex Deucher uint32_t y_data_mask; 127771fe6b9SJerome Glisse }; 128771fe6b9SJerome Glisse 129771fe6b9SJerome Glisse struct radeon_tmds_pll { 130771fe6b9SJerome Glisse uint32_t freq; 131771fe6b9SJerome Glisse uint32_t value; 132771fe6b9SJerome Glisse }; 133771fe6b9SJerome Glisse 134771fe6b9SJerome Glisse #define RADEON_MAX_BIOS_CONNECTOR 16 135771fe6b9SJerome Glisse 1367c27f87dSAlex Deucher /* pll flags */ 137771fe6b9SJerome Glisse #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138771fe6b9SJerome Glisse #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139771fe6b9SJerome Glisse #define RADEON_PLL_USE_REF_DIV (1 << 2) 140771fe6b9SJerome Glisse #define RADEON_PLL_LEGACY (1 << 3) 141771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146771fe6b9SJerome Glisse #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147771fe6b9SJerome Glisse #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148d0e275a9SAlex Deucher #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149fc10332bSAlex Deucher #define RADEON_PLL_USE_POST_DIV (1 << 12) 15086cb2bbfSAlex Deucher #define RADEON_PLL_IS_LCD (1 << 13) 151f523f74eSAlex Deucher #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152771fe6b9SJerome Glisse 153771fe6b9SJerome Glisse struct radeon_pll { 154fc10332bSAlex Deucher /* reference frequency */ 155fc10332bSAlex Deucher uint32_t reference_freq; 156fc10332bSAlex Deucher 157fc10332bSAlex Deucher /* fixed dividers */ 158fc10332bSAlex Deucher uint32_t reference_div; 159fc10332bSAlex Deucher uint32_t post_div; 160fc10332bSAlex Deucher 161fc10332bSAlex Deucher /* pll in/out limits */ 162771fe6b9SJerome Glisse uint32_t pll_in_min; 163771fe6b9SJerome Glisse uint32_t pll_in_max; 164771fe6b9SJerome Glisse uint32_t pll_out_min; 165771fe6b9SJerome Glisse uint32_t pll_out_max; 16686cb2bbfSAlex Deucher uint32_t lcd_pll_out_min; 16786cb2bbfSAlex Deucher uint32_t lcd_pll_out_max; 168fc10332bSAlex Deucher uint32_t best_vco; 169771fe6b9SJerome Glisse 170fc10332bSAlex Deucher /* divider limits */ 171771fe6b9SJerome Glisse uint32_t min_ref_div; 172771fe6b9SJerome Glisse uint32_t max_ref_div; 173771fe6b9SJerome Glisse uint32_t min_post_div; 174771fe6b9SJerome Glisse uint32_t max_post_div; 175771fe6b9SJerome Glisse uint32_t min_feedback_div; 176771fe6b9SJerome Glisse uint32_t max_feedback_div; 177771fe6b9SJerome Glisse uint32_t min_frac_feedback_div; 178771fe6b9SJerome Glisse uint32_t max_frac_feedback_div; 179fc10332bSAlex Deucher 180fc10332bSAlex Deucher /* flags for the current clock */ 181fc10332bSAlex Deucher uint32_t flags; 182fc10332bSAlex Deucher 183fc10332bSAlex Deucher /* pll id */ 184fc10332bSAlex Deucher uint32_t id; 185771fe6b9SJerome Glisse }; 186771fe6b9SJerome Glisse 187771fe6b9SJerome Glisse struct radeon_i2c_chan { 188771fe6b9SJerome Glisse struct i2c_adapter adapter; 189746c1aa4SDave Airlie struct drm_device *dev; 190746c1aa4SDave Airlie union { 191ac1aade6SAlex Deucher struct i2c_algo_bit_data bit; 192746c1aa4SDave Airlie struct i2c_algo_dp_aux_data dp; 193746c1aa4SDave Airlie } algo; 194771fe6b9SJerome Glisse struct radeon_i2c_bus_rec rec; 195771fe6b9SJerome Glisse }; 196771fe6b9SJerome Glisse 197771fe6b9SJerome Glisse /* mostly for macs, but really any system without connector tables */ 198771fe6b9SJerome Glisse enum radeon_connector_table { 199aa74fbb4SAlex Deucher CT_NONE = 0, 200771fe6b9SJerome Glisse CT_GENERIC, 201771fe6b9SJerome Glisse CT_IBOOK, 202771fe6b9SJerome Glisse CT_POWERBOOK_EXTERNAL, 203771fe6b9SJerome Glisse CT_POWERBOOK_INTERNAL, 204771fe6b9SJerome Glisse CT_POWERBOOK_VGA, 205771fe6b9SJerome Glisse CT_MINI_EXTERNAL, 206771fe6b9SJerome Glisse CT_MINI_INTERNAL, 207771fe6b9SJerome Glisse CT_IMAC_G5_ISIGHT, 208771fe6b9SJerome Glisse CT_EMAC, 20976a7142aSDave Airlie CT_RN50_POWER, 210aa74fbb4SAlex Deucher CT_MAC_X800, 2119fad321aSAlex Deucher CT_MAC_G5_9600, 212cafa59b9SAlex Deucher CT_SAM440EP, 213cafa59b9SAlex Deucher CT_MAC_G4_SILVER 214771fe6b9SJerome Glisse }; 215771fe6b9SJerome Glisse 216fcec570bSAlex Deucher enum radeon_dvo_chip { 217fcec570bSAlex Deucher DVO_SIL164, 218fcec570bSAlex Deucher DVO_SIL1178, 219fcec570bSAlex Deucher }; 220fcec570bSAlex Deucher 2218be48d92SDave Airlie struct radeon_fbdev; 22238651674SDave Airlie 2230783986aSAlex Deucher struct radeon_afmt { 2240783986aSAlex Deucher bool enabled; 2250783986aSAlex Deucher int offset; 2260783986aSAlex Deucher bool last_buffer_filled_status; 2270783986aSAlex Deucher int id; 228b530602fSAlex Deucher struct r600_audio_pin *pin; 2290783986aSAlex Deucher }; 2300783986aSAlex Deucher 231771fe6b9SJerome Glisse struct radeon_mode_info { 232771fe6b9SJerome Glisse struct atom_context *atom_context; 23361c4b24bSMathias Fröhlich struct card_info *atom_card_info; 234771fe6b9SJerome Glisse enum radeon_connector_table connector_table; 235771fe6b9SJerome Glisse bool mode_config_initialized; 236bcc1c2a1SAlex Deucher struct radeon_crtc *crtcs[6]; 237b530602fSAlex Deucher struct radeon_afmt *afmt[7]; 238445282dbSDave Airlie /* DVI-I properties */ 239445282dbSDave Airlie struct drm_property *coherent_mode_property; 240445282dbSDave Airlie /* DAC enable load detect */ 241445282dbSDave Airlie struct drm_property *load_detect_property; 2425b1714d3SAlex Deucher /* TV standard */ 243445282dbSDave Airlie struct drm_property *tv_std_property; 244445282dbSDave Airlie /* legacy TMDS PLL detect */ 245445282dbSDave Airlie struct drm_property *tmds_pll_property; 2465b1714d3SAlex Deucher /* underscan */ 2475b1714d3SAlex Deucher struct drm_property *underscan_property; 2485bccf5e3SMarius Gröger struct drm_property *underscan_hborder_property; 2495bccf5e3SMarius Gröger struct drm_property *underscan_vborder_property; 2508666c076SAlex Deucher /* audio */ 2518666c076SAlex Deucher struct drm_property *audio_property; 2523c537889SAlex Deucher /* hardcoded DFP edid from BIOS */ 2533c537889SAlex Deucher struct edid *bios_hardcoded_edid; 254fafcf94eSAlex Deucher int bios_hardcoded_edid_size; 25538651674SDave Airlie 25638651674SDave Airlie /* pointer to fbdev info structure */ 2578be48d92SDave Airlie struct radeon_fbdev *rfbdev; 258af7912e5SAlex Deucher /* firmware flags */ 259af7912e5SAlex Deucher u16 firmware_flags; 260bced76f2SAlex Deucher /* pointer to backlight encoder */ 261bced76f2SAlex Deucher struct radeon_encoder *bl_encoder; 262c93bb85bSJerome Glisse }; 263c93bb85bSJerome Glisse 26491030880SAlex Deucher #define RADEON_MAX_BL_LEVEL 0xFF 26591030880SAlex Deucher 266bced76f2SAlex Deucher #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 267bced76f2SAlex Deucher 26891030880SAlex Deucher struct radeon_backlight_privdata { 26991030880SAlex Deucher struct radeon_encoder *encoder; 27091030880SAlex Deucher uint8_t negative; 27191030880SAlex Deucher }; 27291030880SAlex Deucher 27391030880SAlex Deucher #endif 27491030880SAlex Deucher 2754ce001abSDave Airlie #define MAX_H_CODE_TIMING_LEN 32 2764ce001abSDave Airlie #define MAX_V_CODE_TIMING_LEN 32 2774ce001abSDave Airlie 2784ce001abSDave Airlie /* need to store these as reading 2794ce001abSDave Airlie back code tables is excessive */ 2804ce001abSDave Airlie struct radeon_tv_regs { 2814ce001abSDave Airlie uint32_t tv_uv_adr; 2824ce001abSDave Airlie uint32_t timing_cntl; 2834ce001abSDave Airlie uint32_t hrestart; 2844ce001abSDave Airlie uint32_t vrestart; 2854ce001abSDave Airlie uint32_t frestart; 2864ce001abSDave Airlie uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 2874ce001abSDave Airlie uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 2884ce001abSDave Airlie }; 2894ce001abSDave Airlie 29019eca43eSAlex Deucher struct radeon_atom_ss { 29119eca43eSAlex Deucher uint16_t percentage; 29219eca43eSAlex Deucher uint8_t type; 29319eca43eSAlex Deucher uint16_t step; 29419eca43eSAlex Deucher uint8_t delay; 29519eca43eSAlex Deucher uint8_t range; 29619eca43eSAlex Deucher uint8_t refdiv; 29719eca43eSAlex Deucher /* asic_ss */ 29819eca43eSAlex Deucher uint16_t rate; 29919eca43eSAlex Deucher uint16_t amount; 30019eca43eSAlex Deucher }; 30119eca43eSAlex Deucher 302771fe6b9SJerome Glisse struct radeon_crtc { 303771fe6b9SJerome Glisse struct drm_crtc base; 304771fe6b9SJerome Glisse int crtc_id; 305771fe6b9SJerome Glisse u16 lut_r[256], lut_g[256], lut_b[256]; 306771fe6b9SJerome Glisse bool enabled; 307771fe6b9SJerome Glisse bool can_tile; 308771fe6b9SJerome Glisse uint32_t crtc_offset; 309771fe6b9SJerome Glisse struct drm_gem_object *cursor_bo; 310771fe6b9SJerome Glisse uint64_t cursor_addr; 311771fe6b9SJerome Glisse int cursor_width; 312771fe6b9SJerome Glisse int cursor_height; 3139e05fa1dSAlex Deucher int max_cursor_width; 3149e05fa1dSAlex Deucher int max_cursor_height; 3154162338aSDave Airlie uint32_t legacy_display_base_addr; 316c836e862SAlex Deucher uint32_t legacy_cursor_offset; 317c93bb85bSJerome Glisse enum radeon_rmx_type rmx_type; 3185b1714d3SAlex Deucher u8 h_border; 3195b1714d3SAlex Deucher u8 v_border; 320c93bb85bSJerome Glisse fixed20_12 vsc; 321c93bb85bSJerome Glisse fixed20_12 hsc; 322de2103e4SAlex Deucher struct drm_display_mode native_mode; 323bcc1c2a1SAlex Deucher int pll_id; 3246f34be50SAlex Deucher /* page flipping */ 3256f34be50SAlex Deucher struct radeon_unpin_work *unpin_work; 3266f34be50SAlex Deucher int deferred_flip_completion; 32719eca43eSAlex Deucher /* pll sharing */ 32819eca43eSAlex Deucher struct radeon_atom_ss ss; 32919eca43eSAlex Deucher bool ss_enabled; 33019eca43eSAlex Deucher u32 adjusted_clock; 33119eca43eSAlex Deucher int bpc; 33219eca43eSAlex Deucher u32 pll_reference_div; 33319eca43eSAlex Deucher u32 pll_post_div; 33419eca43eSAlex Deucher u32 pll_flags; 3355df3196bSAlex Deucher struct drm_encoder *encoder; 33657b35e29SAlex Deucher struct drm_connector *connector; 3377178d2a6SAlex Deucher /* for dpm */ 3387178d2a6SAlex Deucher u32 line_time; 3397178d2a6SAlex Deucher u32 wm_low; 3407178d2a6SAlex Deucher u32 wm_high; 34166edc1c9SAlex Deucher struct drm_display_mode hw_mode; 342771fe6b9SJerome Glisse }; 343771fe6b9SJerome Glisse 344771fe6b9SJerome Glisse struct radeon_encoder_primary_dac { 345771fe6b9SJerome Glisse /* legacy primary dac */ 346771fe6b9SJerome Glisse uint32_t ps2_pdac_adj; 347771fe6b9SJerome Glisse }; 348771fe6b9SJerome Glisse 349771fe6b9SJerome Glisse struct radeon_encoder_lvds { 350771fe6b9SJerome Glisse /* legacy lvds */ 351771fe6b9SJerome Glisse uint16_t panel_vcc_delay; 352771fe6b9SJerome Glisse uint8_t panel_pwr_delay; 353771fe6b9SJerome Glisse uint8_t panel_digon_delay; 354771fe6b9SJerome Glisse uint8_t panel_blon_delay; 355771fe6b9SJerome Glisse uint16_t panel_ref_divider; 356771fe6b9SJerome Glisse uint8_t panel_post_divider; 357771fe6b9SJerome Glisse uint16_t panel_fb_divider; 358771fe6b9SJerome Glisse bool use_bios_dividers; 359771fe6b9SJerome Glisse uint32_t lvds_gen_cntl; 360771fe6b9SJerome Glisse /* panel mode */ 361de2103e4SAlex Deucher struct drm_display_mode native_mode; 36263ec0119SMichel Dänzer struct backlight_device *bl_dev; 36363ec0119SMichel Dänzer int dpms_mode; 36463ec0119SMichel Dänzer uint8_t backlight_level; 365771fe6b9SJerome Glisse }; 366771fe6b9SJerome Glisse 367771fe6b9SJerome Glisse struct radeon_encoder_tv_dac { 368771fe6b9SJerome Glisse /* legacy tv dac */ 369771fe6b9SJerome Glisse uint32_t ps2_tvdac_adj; 370771fe6b9SJerome Glisse uint32_t ntsc_tvdac_adj; 371771fe6b9SJerome Glisse uint32_t pal_tvdac_adj; 372771fe6b9SJerome Glisse 3734ce001abSDave Airlie int h_pos; 3744ce001abSDave Airlie int v_pos; 3754ce001abSDave Airlie int h_size; 3764ce001abSDave Airlie int supported_tv_stds; 3774ce001abSDave Airlie bool tv_on; 378771fe6b9SJerome Glisse enum radeon_tv_std tv_std; 3794ce001abSDave Airlie struct radeon_tv_regs tv; 380771fe6b9SJerome Glisse }; 381771fe6b9SJerome Glisse 382771fe6b9SJerome Glisse struct radeon_encoder_int_tmds { 383771fe6b9SJerome Glisse /* legacy int tmds */ 384771fe6b9SJerome Glisse struct radeon_tmds_pll tmds_pll[4]; 385771fe6b9SJerome Glisse }; 386771fe6b9SJerome Glisse 387fcec570bSAlex Deucher struct radeon_encoder_ext_tmds { 388fcec570bSAlex Deucher /* tmds over dvo */ 389fcec570bSAlex Deucher struct radeon_i2c_chan *i2c_bus; 390fcec570bSAlex Deucher uint8_t slave_addr; 391fcec570bSAlex Deucher enum radeon_dvo_chip dvo_chip; 392fcec570bSAlex Deucher }; 393fcec570bSAlex Deucher 394ebbe1cb9SAlex Deucher /* spread spectrum */ 395771fe6b9SJerome Glisse struct radeon_encoder_atom_dig { 3965137ee94SAlex Deucher bool linkb; 397771fe6b9SJerome Glisse /* atom dig */ 398771fe6b9SJerome Glisse bool coherent_mode; 399ba032a58SAlex Deucher int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 400ba032a58SAlex Deucher /* atom lvds/edp */ 401ba032a58SAlex Deucher uint32_t lcd_misc; 402771fe6b9SJerome Glisse uint16_t panel_pwr_delay; 403ba032a58SAlex Deucher uint32_t lcd_ss_id; 404771fe6b9SJerome Glisse /* panel mode */ 405de2103e4SAlex Deucher struct drm_display_mode native_mode; 40663ec0119SMichel Dänzer struct backlight_device *bl_dev; 40763ec0119SMichel Dänzer int dpms_mode; 40863ec0119SMichel Dänzer uint8_t backlight_level; 409386d4d75SAlex Deucher int panel_mode; 4100783986aSAlex Deucher struct radeon_afmt *afmt; 411771fe6b9SJerome Glisse }; 412771fe6b9SJerome Glisse 4134ce001abSDave Airlie struct radeon_encoder_atom_dac { 4144ce001abSDave Airlie enum radeon_tv_std tv_std; 4154ce001abSDave Airlie }; 4164ce001abSDave Airlie 417771fe6b9SJerome Glisse struct radeon_encoder { 418771fe6b9SJerome Glisse struct drm_encoder base; 4195137ee94SAlex Deucher uint32_t encoder_enum; 420771fe6b9SJerome Glisse uint32_t encoder_id; 421771fe6b9SJerome Glisse uint32_t devices; 4224ce001abSDave Airlie uint32_t active_device; 423771fe6b9SJerome Glisse uint32_t flags; 424771fe6b9SJerome Glisse uint32_t pixel_clock; 425771fe6b9SJerome Glisse enum radeon_rmx_type rmx_type; 4265b1714d3SAlex Deucher enum radeon_underscan_type underscan_type; 4275bccf5e3SMarius Gröger uint32_t underscan_hborder; 4285bccf5e3SMarius Gröger uint32_t underscan_vborder; 429de2103e4SAlex Deucher struct drm_display_mode native_mode; 430771fe6b9SJerome Glisse void *enc_priv; 43158bd0863SChristian König int audio_polling_active; 4323e4b9982SAlex Deucher bool is_ext_encoder; 43336868bdaSAlex Deucher u16 caps; 434771fe6b9SJerome Glisse }; 435771fe6b9SJerome Glisse 436771fe6b9SJerome Glisse struct radeon_connector_atom_dig { 437771fe6b9SJerome Glisse uint32_t igp_lane_info; 4384143e919SAlex Deucher /* displayport */ 439746c1aa4SDave Airlie struct radeon_i2c_chan *dp_i2c_bus; 4401a644cd4SDaniel Vetter u8 dpcd[DP_RECEIVER_CAP_SIZE]; 4414143e919SAlex Deucher u8 dp_sink_type; 4425801ead6SAlex Deucher int dp_clock; 4435801ead6SAlex Deucher int dp_lane_count; 4448b834852SAlex Deucher bool edp_on; 445771fe6b9SJerome Glisse }; 446771fe6b9SJerome Glisse 447eed45b30SAlex Deucher struct radeon_gpio_rec { 448eed45b30SAlex Deucher bool valid; 449eed45b30SAlex Deucher u8 id; 450eed45b30SAlex Deucher u32 reg; 451eed45b30SAlex Deucher u32 mask; 452eed45b30SAlex Deucher }; 453eed45b30SAlex Deucher 454eed45b30SAlex Deucher struct radeon_hpd { 455eed45b30SAlex Deucher enum radeon_hpd_id hpd; 456eed45b30SAlex Deucher u8 plugged_state; 457eed45b30SAlex Deucher struct radeon_gpio_rec gpio; 458eed45b30SAlex Deucher }; 459eed45b30SAlex Deucher 46026b5bc98SAlex Deucher struct radeon_router { 46126b5bc98SAlex Deucher u32 router_id; 46226b5bc98SAlex Deucher struct radeon_i2c_bus_rec i2c_info; 46326b5bc98SAlex Deucher u8 i2c_addr; 464fb939dfcSAlex Deucher /* i2c mux */ 465fb939dfcSAlex Deucher bool ddc_valid; 466fb939dfcSAlex Deucher u8 ddc_mux_type; 467fb939dfcSAlex Deucher u8 ddc_mux_control_pin; 468fb939dfcSAlex Deucher u8 ddc_mux_state; 469fb939dfcSAlex Deucher /* clock/data mux */ 470fb939dfcSAlex Deucher bool cd_valid; 471fb939dfcSAlex Deucher u8 cd_mux_type; 472fb939dfcSAlex Deucher u8 cd_mux_control_pin; 473fb939dfcSAlex Deucher u8 cd_mux_state; 47426b5bc98SAlex Deucher }; 47526b5bc98SAlex Deucher 4768666c076SAlex Deucher enum radeon_connector_audio { 4778666c076SAlex Deucher RADEON_AUDIO_DISABLE = 0, 4788666c076SAlex Deucher RADEON_AUDIO_ENABLE = 1, 4798666c076SAlex Deucher RADEON_AUDIO_AUTO = 2 4808666c076SAlex Deucher }; 4818666c076SAlex Deucher 482771fe6b9SJerome Glisse struct radeon_connector { 483771fe6b9SJerome Glisse struct drm_connector base; 484771fe6b9SJerome Glisse uint32_t connector_id; 485771fe6b9SJerome Glisse uint32_t devices; 486771fe6b9SJerome Glisse struct radeon_i2c_chan *ddc_bus; 4875b1714d3SAlex Deucher /* some systems have an hdmi and vga port with a shared ddc line */ 4880294cf4fSAlex Deucher bool shared_ddc; 4894ce001abSDave Airlie bool use_digital; 4904ce001abSDave Airlie /* we need to mind the EDID between detect 4914ce001abSDave Airlie and get modes due to analog/digital/tvencoder */ 4924ce001abSDave Airlie struct edid *edid; 493771fe6b9SJerome Glisse void *con_priv; 494445282dbSDave Airlie bool dac_load_detect; 495d0d0a225SAlex Deucher bool detected_by_load; /* if the connection status was determined by load */ 496b75fad06SAlex Deucher uint16_t connector_object_id; 497eed45b30SAlex Deucher struct radeon_hpd hpd; 49826b5bc98SAlex Deucher struct radeon_router router; 49926b5bc98SAlex Deucher struct radeon_i2c_chan *router_bus; 5008666c076SAlex Deucher enum radeon_connector_audio audio; 501771fe6b9SJerome Glisse }; 502771fe6b9SJerome Glisse 503771fe6b9SJerome Glisse struct radeon_framebuffer { 504771fe6b9SJerome Glisse struct drm_framebuffer base; 505771fe6b9SJerome Glisse struct drm_gem_object *obj; 506771fe6b9SJerome Glisse }; 507771fe6b9SJerome Glisse 508996d5c59SAlex Deucher #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 509996d5c59SAlex Deucher ((em) == ATOM_ENCODER_MODE_DP_MST)) 5106383cf7dSMario Kleiner 5117062ab67SChristian König struct atom_clock_dividers { 5127062ab67SChristian König u32 post_div; 5137062ab67SChristian König union { 5147062ab67SChristian König struct { 5157062ab67SChristian König #ifdef __BIG_ENDIAN 5167062ab67SChristian König u32 reserved : 6; 5177062ab67SChristian König u32 whole_fb_div : 12; 5187062ab67SChristian König u32 frac_fb_div : 14; 5197062ab67SChristian König #else 5207062ab67SChristian König u32 frac_fb_div : 14; 5217062ab67SChristian König u32 whole_fb_div : 12; 5227062ab67SChristian König u32 reserved : 6; 5237062ab67SChristian König #endif 5247062ab67SChristian König }; 5257062ab67SChristian König u32 fb_div; 5267062ab67SChristian König }; 5277062ab67SChristian König u32 ref_div; 5287062ab67SChristian König bool enable_post_div; 5297062ab67SChristian König bool enable_dithen; 5307062ab67SChristian König u32 vco_mode; 5317062ab67SChristian König u32 real_clock; 5329219ed65SAlex Deucher /* added for CI */ 5339219ed65SAlex Deucher u32 post_divider; 5349219ed65SAlex Deucher u32 flags; 5357062ab67SChristian König }; 5367062ab67SChristian König 537eaa778afSAlex Deucher struct atom_mpll_param { 538eaa778afSAlex Deucher union { 539eaa778afSAlex Deucher struct { 540eaa778afSAlex Deucher #ifdef __BIG_ENDIAN 541eaa778afSAlex Deucher u32 reserved : 8; 542eaa778afSAlex Deucher u32 clkfrac : 12; 543eaa778afSAlex Deucher u32 clkf : 12; 544eaa778afSAlex Deucher #else 545eaa778afSAlex Deucher u32 clkf : 12; 546eaa778afSAlex Deucher u32 clkfrac : 12; 547eaa778afSAlex Deucher u32 reserved : 8; 548eaa778afSAlex Deucher #endif 549eaa778afSAlex Deucher }; 550eaa778afSAlex Deucher u32 fb_div; 551eaa778afSAlex Deucher }; 552eaa778afSAlex Deucher u32 post_div; 553eaa778afSAlex Deucher u32 bwcntl; 554eaa778afSAlex Deucher u32 dll_speed; 555eaa778afSAlex Deucher u32 vco_mode; 556eaa778afSAlex Deucher u32 yclk_sel; 557eaa778afSAlex Deucher u32 qdr; 558eaa778afSAlex Deucher u32 half_rate; 559eaa778afSAlex Deucher }; 560eaa778afSAlex Deucher 561ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR5 0x50 562ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR4 0x40 563ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR3 0x30 564ae5b0abbSAlex Deucher #define MEM_TYPE_DDR2 0x20 565ae5b0abbSAlex Deucher #define MEM_TYPE_GDDR1 0x10 566ae5b0abbSAlex Deucher #define MEM_TYPE_DDR3 0xb0 567ae5b0abbSAlex Deucher #define MEM_TYPE_MASK 0xf0 568ae5b0abbSAlex Deucher 569ae5b0abbSAlex Deucher struct atom_memory_info { 570ae5b0abbSAlex Deucher u8 mem_vendor; 571ae5b0abbSAlex Deucher u8 mem_type; 572ae5b0abbSAlex Deucher }; 573ae5b0abbSAlex Deucher 574ae5b0abbSAlex Deucher #define MAX_AC_TIMING_ENTRIES 16 575ae5b0abbSAlex Deucher 576ae5b0abbSAlex Deucher struct atom_memory_clock_range_table 577ae5b0abbSAlex Deucher { 578ae5b0abbSAlex Deucher u8 num_entries; 579ae5b0abbSAlex Deucher u8 rsv[3]; 580ae5b0abbSAlex Deucher u32 mclk[MAX_AC_TIMING_ENTRIES]; 581ae5b0abbSAlex Deucher }; 582ae5b0abbSAlex Deucher 583ae5b0abbSAlex Deucher #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 584ae5b0abbSAlex Deucher #define VBIOS_MAX_AC_TIMING_ENTRIES 20 585ae5b0abbSAlex Deucher 586ae5b0abbSAlex Deucher struct atom_mc_reg_entry { 587ae5b0abbSAlex Deucher u32 mclk_max; 588ae5b0abbSAlex Deucher u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 589ae5b0abbSAlex Deucher }; 590ae5b0abbSAlex Deucher 591ae5b0abbSAlex Deucher struct atom_mc_register_address { 592ae5b0abbSAlex Deucher u16 s1; 593ae5b0abbSAlex Deucher u8 pre_reg_data; 594ae5b0abbSAlex Deucher }; 595ae5b0abbSAlex Deucher 596ae5b0abbSAlex Deucher struct atom_mc_reg_table { 597ae5b0abbSAlex Deucher u8 last; 598ae5b0abbSAlex Deucher u8 num_entries; 599ae5b0abbSAlex Deucher struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 600ae5b0abbSAlex Deucher struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 601ae5b0abbSAlex Deucher }; 602ae5b0abbSAlex Deucher 603ae5b0abbSAlex Deucher #define MAX_VOLTAGE_ENTRIES 32 604ae5b0abbSAlex Deucher 605ae5b0abbSAlex Deucher struct atom_voltage_table_entry 606ae5b0abbSAlex Deucher { 607ae5b0abbSAlex Deucher u16 value; 608ae5b0abbSAlex Deucher u32 smio_low; 609ae5b0abbSAlex Deucher }; 610ae5b0abbSAlex Deucher 611ae5b0abbSAlex Deucher struct atom_voltage_table 612ae5b0abbSAlex Deucher { 613ae5b0abbSAlex Deucher u32 count; 614ae5b0abbSAlex Deucher u32 mask_low; 61565171944SAlex Deucher u32 phase_delay; 616ae5b0abbSAlex Deucher struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 617ae5b0abbSAlex Deucher }; 618ae5b0abbSAlex Deucher 619d79766faSAlex Deucher extern enum radeon_tv_std 620d79766faSAlex Deucher radeon_combios_get_tv_info(struct radeon_device *rdev); 621d79766faSAlex Deucher extern enum radeon_tv_std 622d79766faSAlex Deucher radeon_atombios_get_tv_info(struct radeon_device *rdev); 6234a6369e9SAlex Deucher extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 6242abba66eSAlex Deucher u16 *vddc, u16 *vddci, u16 *mvdd); 625d79766faSAlex Deucher 6265b1714d3SAlex Deucher extern struct drm_connector * 6275b1714d3SAlex Deucher radeon_get_connector_for_encoder(struct drm_encoder *encoder); 6289aa59993SAlex Deucher extern struct drm_connector * 6299aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 6309aa59993SAlex Deucher extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 6319aa59993SAlex Deucher u32 pixel_clock); 6325b1714d3SAlex Deucher 6331d33e1fcSAlex Deucher extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 6341d33e1fcSAlex Deucher extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 635d7fa8bb3SAlex Deucher extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 636d7fa8bb3SAlex Deucher extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 637eccea792SAlex Deucher extern int radeon_get_monitor_bpc(struct drm_connector *connector); 638d7fa8bb3SAlex Deucher 639d4877cf2SAlex Deucher extern void radeon_connector_hotplug(struct drm_connector *connector); 640224d94b1SAlex Deucher extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 6415801ead6SAlex Deucher struct drm_display_mode *mode); 6425801ead6SAlex Deucher extern void radeon_dp_set_link_config(struct drm_connector *connector, 643e811f5aeSLaurent Pinchart const struct drm_display_mode *mode); 644224d94b1SAlex Deucher extern void radeon_dp_link_train(struct drm_encoder *encoder, 6455801ead6SAlex Deucher struct drm_connector *connector); 646d5811e87SAlex Deucher extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 6474143e919SAlex Deucher extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 6489fa05c98SAlex Deucher extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 649386d4d75SAlex Deucher extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 650386d4d75SAlex Deucher struct drm_connector *connector); 651558e27dbSAlex Deucher extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 652ac89af1eSAlex Deucher extern void radeon_atom_encoder_init(struct radeon_device *rdev); 653f3f1f03eSAlex Deucher extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 6545801ead6SAlex Deucher extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 6555801ead6SAlex Deucher int action, uint8_t lane_num, 6565801ead6SAlex Deucher uint8_t lane_set); 657591a10e1SAlex Deucher extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 6583f03ced8SAlex Deucher extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 659746c1aa4SDave Airlie extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 660834b2904SAlex Deucher u8 write_byte, u8 *read_byte); 661746c1aa4SDave Airlie 662f376b94fSAlex Deucher extern void radeon_i2c_init(struct radeon_device *rdev); 663f376b94fSAlex Deucher extern void radeon_i2c_fini(struct radeon_device *rdev); 664f376b94fSAlex Deucher extern void radeon_combios_i2c_init(struct radeon_device *rdev); 665f376b94fSAlex Deucher extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 666f376b94fSAlex Deucher extern void radeon_i2c_add(struct radeon_device *rdev, 667f376b94fSAlex Deucher struct radeon_i2c_bus_rec *rec, 668f376b94fSAlex Deucher const char *name); 669f376b94fSAlex Deucher extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 670f376b94fSAlex Deucher struct radeon_i2c_bus_rec *i2c_bus); 671746c1aa4SDave Airlie extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 6726a93cb25SAlex Deucher struct radeon_i2c_bus_rec *rec, 6736a93cb25SAlex Deucher const char *name); 674771fe6b9SJerome Glisse extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 675771fe6b9SJerome Glisse struct radeon_i2c_bus_rec *rec, 676771fe6b9SJerome Glisse const char *name); 677771fe6b9SJerome Glisse extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 6785a6f98f5SAlex Deucher extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 679fcec570bSAlex Deucher u8 slave_addr, 680fcec570bSAlex Deucher u8 addr, 681fcec570bSAlex Deucher u8 *val); 6825a6f98f5SAlex Deucher extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 683fcec570bSAlex Deucher u8 slave_addr, 684fcec570bSAlex Deucher u8 addr, 685fcec570bSAlex Deucher u8 val); 686fb939dfcSAlex Deucher extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 687fb939dfcSAlex Deucher extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 6880a9069d3SNiels Ole Salscheider extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 689771fe6b9SJerome Glisse extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 690771fe6b9SJerome Glisse 691771fe6b9SJerome Glisse extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 692771fe6b9SJerome Glisse 693ba032a58SAlex Deucher extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 694ba032a58SAlex Deucher struct radeon_atom_ss *ss, 695ba032a58SAlex Deucher int id); 696ba032a58SAlex Deucher extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 697ba032a58SAlex Deucher struct radeon_atom_ss *ss, 698ba032a58SAlex Deucher int id, u32 clock); 699ba032a58SAlex Deucher 700f523f74eSAlex Deucher extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 701771fe6b9SJerome Glisse uint64_t freq, 702771fe6b9SJerome Glisse uint32_t *dot_clock_p, 703771fe6b9SJerome Glisse uint32_t *fb_div_p, 704771fe6b9SJerome Glisse uint32_t *frac_fb_div_p, 705771fe6b9SJerome Glisse uint32_t *ref_div_p, 706fc10332bSAlex Deucher uint32_t *post_div_p); 707771fe6b9SJerome Glisse 708f523f74eSAlex Deucher extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 709f523f74eSAlex Deucher u32 freq, 710f523f74eSAlex Deucher u32 *dot_clock_p, 711f523f74eSAlex Deucher u32 *fb_div_p, 712f523f74eSAlex Deucher u32 *frac_fb_div_p, 713f523f74eSAlex Deucher u32 *ref_div_p, 714f523f74eSAlex Deucher u32 *post_div_p); 715f523f74eSAlex Deucher 7161f3b6a45SDave Airlie extern void radeon_setup_encoder_clones(struct drm_device *dev); 7171f3b6a45SDave Airlie 718771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 719771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 720771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 721771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 722771fe6b9SJerome Glisse struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 72399999aaaSAlex Deucher extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 72432f48ffeSAlex Deucher extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 725771fe6b9SJerome Glisse extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 7262dafb74dSAlex Deucher extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 7274ce001abSDave Airlie extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 728771fe6b9SJerome Glisse 729771fe6b9SJerome Glisse extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 730771fe6b9SJerome Glisse extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 731771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 7324dd19b0dSChris Ball extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 7334dd19b0dSChris Ball struct drm_framebuffer *fb, 73421c74a8eSJason Wessel int x, int y, 73521c74a8eSJason Wessel enum mode_set_atomic state); 736771fe6b9SJerome Glisse extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 737771fe6b9SJerome Glisse struct drm_display_mode *mode, 738771fe6b9SJerome Glisse struct drm_display_mode *adjusted_mode, 739771fe6b9SJerome Glisse int x, int y, 740771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 741771fe6b9SJerome Glisse extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 742771fe6b9SJerome Glisse 743771fe6b9SJerome Glisse extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 744771fe6b9SJerome Glisse struct drm_framebuffer *old_fb); 7454dd19b0dSChris Ball extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 7464dd19b0dSChris Ball struct drm_framebuffer *fb, 74721c74a8eSJason Wessel int x, int y, 74821c74a8eSJason Wessel enum mode_set_atomic state); 7494dd19b0dSChris Ball extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 7504dd19b0dSChris Ball struct drm_framebuffer *fb, 7514dd19b0dSChris Ball int x, int y, int atomic); 752771fe6b9SJerome Glisse extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 753771fe6b9SJerome Glisse struct drm_file *file_priv, 754771fe6b9SJerome Glisse uint32_t handle, 755771fe6b9SJerome Glisse uint32_t width, 756771fe6b9SJerome Glisse uint32_t height); 757771fe6b9SJerome Glisse extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 758771fe6b9SJerome Glisse int x, int y); 759771fe6b9SJerome Glisse 760f5a80209SMario Kleiner extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 761f5a80209SMario Kleiner int *vpos, int *hpos); 7626383cf7dSMario Kleiner 7633c537889SAlex Deucher extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 7643c537889SAlex Deucher extern struct edid * 765c324acd5SAlex Deucher radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 766771fe6b9SJerome Glisse extern bool radeon_atom_get_clock_info(struct drm_device *dev); 767771fe6b9SJerome Glisse extern bool radeon_combios_get_clock_info(struct drm_device *dev); 768771fe6b9SJerome Glisse extern struct radeon_encoder_atom_dig * 769771fe6b9SJerome Glisse radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 770fcec570bSAlex Deucher extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 771445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 772fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 773445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 774fcec570bSAlex Deucher extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 775445282dbSDave Airlie struct radeon_encoder_int_tmds *tmds); 776fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 777fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 778fcec570bSAlex Deucher extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 779fcec570bSAlex Deucher struct radeon_encoder_ext_tmds *tmds); 7806fe7ac3fSAlex Deucher extern struct radeon_encoder_primary_dac * 7816fe7ac3fSAlex Deucher radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 7826fe7ac3fSAlex Deucher extern struct radeon_encoder_tv_dac * 7836fe7ac3fSAlex Deucher radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 784771fe6b9SJerome Glisse extern struct radeon_encoder_lvds * 785771fe6b9SJerome Glisse radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 786771fe6b9SJerome Glisse extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 787771fe6b9SJerome Glisse extern struct radeon_encoder_tv_dac * 788771fe6b9SJerome Glisse radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 789771fe6b9SJerome Glisse extern struct radeon_encoder_primary_dac * 790771fe6b9SJerome Glisse radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 791fcec570bSAlex Deucher extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 792fcec570bSAlex Deucher extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 793771fe6b9SJerome Glisse extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 794771fe6b9SJerome Glisse extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 795771fe6b9SJerome Glisse extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 796771fe6b9SJerome Glisse extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 797f657c2a7SYang Zhao extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 798f657c2a7SYang Zhao extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 799771fe6b9SJerome Glisse extern void 800771fe6b9SJerome Glisse radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 801771fe6b9SJerome Glisse extern void 802771fe6b9SJerome Glisse radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 803771fe6b9SJerome Glisse extern void 804771fe6b9SJerome Glisse radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 805771fe6b9SJerome Glisse extern void 806771fe6b9SJerome Glisse radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 807771fe6b9SJerome Glisse extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 808771fe6b9SJerome Glisse u16 blue, int regno); 809b8c00ac5SDave Airlie extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 810b8c00ac5SDave Airlie u16 *blue, int regno); 811aaefcd42SDave Airlie int radeon_framebuffer_init(struct drm_device *dev, 81238651674SDave Airlie struct radeon_framebuffer *rfb, 813308e5bcbSJesse Barnes struct drm_mode_fb_cmd2 *mode_cmd, 814771fe6b9SJerome Glisse struct drm_gem_object *obj); 815771fe6b9SJerome Glisse 816771fe6b9SJerome Glisse int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 817771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 818771fe6b9SJerome Glisse bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 819771fe6b9SJerome Glisse void radeon_atombios_init_crtc(struct drm_device *dev, 820771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 821771fe6b9SJerome Glisse void radeon_legacy_init_crtc(struct drm_device *dev, 822771fe6b9SJerome Glisse struct radeon_crtc *radeon_crtc); 823771fe6b9SJerome Glisse 824771fe6b9SJerome Glisse void radeon_get_clock_info(struct drm_device *dev); 825771fe6b9SJerome Glisse 826771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 827771fe6b9SJerome Glisse extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 828771fe6b9SJerome Glisse 829771fe6b9SJerome Glisse void radeon_enc_destroy(struct drm_encoder *encoder); 830771fe6b9SJerome Glisse void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 831771fe6b9SJerome Glisse void radeon_combios_asic_init(struct drm_device *dev); 832c93bb85bSJerome Glisse bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 833e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 834c93bb85bSJerome Glisse struct drm_display_mode *adjusted_mode); 8353515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 8363515387bSAlex Deucher struct drm_display_mode *adjusted_mode); 8374ce001abSDave Airlie void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 838771fe6b9SJerome Glisse 8394ce001abSDave Airlie /* legacy tv */ 8404ce001abSDave Airlie void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 8414ce001abSDave Airlie uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 8424ce001abSDave Airlie uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 8434ce001abSDave Airlie void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 8444ce001abSDave Airlie uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 8454ce001abSDave Airlie uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 8464ce001abSDave Airlie void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 8474ce001abSDave Airlie uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 8484ce001abSDave Airlie uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 8494ce001abSDave Airlie void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 8504ce001abSDave Airlie struct drm_display_mode *mode, 8514ce001abSDave Airlie struct drm_display_mode *adjusted_mode); 85238651674SDave Airlie 853134b480fSAlex Deucher /* fmt blocks */ 854134b480fSAlex Deucher void avivo_program_fmt(struct drm_encoder *encoder); 855134b480fSAlex Deucher void dce3_program_fmt(struct drm_encoder *encoder); 856134b480fSAlex Deucher void dce4_program_fmt(struct drm_encoder *encoder); 857134b480fSAlex Deucher void dce8_program_fmt(struct drm_encoder *encoder); 858134b480fSAlex Deucher 85938651674SDave Airlie /* fbdev layer */ 86038651674SDave Airlie int radeon_fbdev_init(struct radeon_device *rdev); 86138651674SDave Airlie void radeon_fbdev_fini(struct radeon_device *rdev); 86238651674SDave Airlie void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 86338651674SDave Airlie int radeon_fbdev_total_size(struct radeon_device *rdev); 86438651674SDave Airlie bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 865eb1f8e4fSDave Airlie 866eb1f8e4fSDave Airlie void radeon_fb_output_poll_changed(struct radeon_device *rdev); 8676f34be50SAlex Deucher 8686f34be50SAlex Deucher void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 8696f34be50SAlex Deucher 870ff72145bSDave Airlie int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 871771fe6b9SJerome Glisse #endif 872