1 // SPDX-License-Identifier: MIT 2 #include <drm/drmP.h> 3 #include <drm/drm_crtc_helper.h> 4 #include "radeon.h" 5 6 /* 7 * Integrated TV out support based on the GATOS code by 8 * Federico Ulivi <fulivi@lycos.com> 9 */ 10 11 12 /* 13 * Limits of h/v positions (hPos & vPos) 14 */ 15 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ 16 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ 17 18 /* 19 * Unit for hPos (in TV clock periods) 20 */ 21 #define H_POS_UNIT 10 22 23 /* 24 * Indexes in h. code timing table for horizontal line position adjustment 25 */ 26 #define H_TABLE_POS1 6 27 #define H_TABLE_POS2 8 28 29 /* 30 * Limits of hor. size (hSize) 31 */ 32 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ 33 34 /* tv standard constants */ 35 #define NTSC_TV_CLOCK_T 233 36 #define NTSC_TV_VFTOTAL 1 37 #define NTSC_TV_LINES_PER_FRAME 525 38 #define NTSC_TV_ZERO_H_SIZE 479166 39 #define NTSC_TV_H_SIZE_UNIT 9478 40 41 #define PAL_TV_CLOCK_T 188 42 #define PAL_TV_VFTOTAL 3 43 #define PAL_TV_LINES_PER_FRAME 625 44 #define PAL_TV_ZERO_H_SIZE 473200 45 #define PAL_TV_H_SIZE_UNIT 9360 46 47 /* tv pll setting for 27 mhz ref clk */ 48 #define NTSC_TV_PLL_M_27 22 49 #define NTSC_TV_PLL_N_27 175 50 #define NTSC_TV_PLL_P_27 5 51 52 #define PAL_TV_PLL_M_27 113 53 #define PAL_TV_PLL_N_27 668 54 #define PAL_TV_PLL_P_27 3 55 56 /* tv pll setting for 14 mhz ref clk */ 57 #define NTSC_TV_PLL_M_14 33 58 #define NTSC_TV_PLL_N_14 693 59 #define NTSC_TV_PLL_P_14 7 60 61 #define PAL_TV_PLL_M_14 19 62 #define PAL_TV_PLL_N_14 353 63 #define PAL_TV_PLL_P_14 5 64 65 #define VERT_LEAD_IN_LINES 2 66 #define FRAC_BITS 0xe 67 #define FRAC_MASK 0x3fff 68 69 struct radeon_tv_mode_constants { 70 uint16_t hor_resolution; 71 uint16_t ver_resolution; 72 enum radeon_tv_std standard; 73 uint16_t hor_total; 74 uint16_t ver_total; 75 uint16_t hor_start; 76 uint16_t hor_syncstart; 77 uint16_t ver_syncstart; 78 unsigned def_restart; 79 uint16_t crtcPLL_N; 80 uint8_t crtcPLL_M; 81 uint8_t crtcPLL_post_div; 82 unsigned pix_to_tv; 83 }; 84 85 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 86 0x0007, 87 0x003f, 88 0x0263, 89 0x0a24, 90 0x2a6b, 91 0x0a36, 92 0x126d, /* H_TABLE_POS1 */ 93 0x1bfe, 94 0x1a8f, /* H_TABLE_POS2 */ 95 0x1ec7, 96 0x3863, 97 0x1bfe, 98 0x1bfe, 99 0x1a2a, 100 0x1e95, 101 0x0e31, 102 0x201b, 103 0 104 }; 105 106 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 107 0x2001, 108 0x200d, 109 0x1006, 110 0x0c06, 111 0x1006, 112 0x1818, 113 0x21e3, 114 0x1006, 115 0x0c06, 116 0x1006, 117 0x1817, 118 0x21d4, 119 0x0002, 120 0 121 }; 122 123 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 124 0x0007, 125 0x0058, 126 0x027c, 127 0x0a31, 128 0x2a77, 129 0x0a95, 130 0x124f, /* H_TABLE_POS1 */ 131 0x1bfe, 132 0x1b22, /* H_TABLE_POS2 */ 133 0x1ef9, 134 0x387c, 135 0x1bfe, 136 0x1bfe, 137 0x1b31, 138 0x1eb5, 139 0x0e43, 140 0x201b, 141 0 142 }; 143 144 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 145 0x2001, 146 0x200c, 147 0x1005, 148 0x0c05, 149 0x1005, 150 0x1401, 151 0x1821, 152 0x2240, 153 0x1005, 154 0x0c05, 155 0x1005, 156 0x1401, 157 0x1822, 158 0x2230, 159 0x0002, 160 0 161 }; 162 163 /********************************************************************** 164 * 165 * availableModes 166 * 167 * Table of all allowed modes for tv output 168 * 169 **********************************************************************/ 170 static const struct radeon_tv_mode_constants available_tv_modes[] = { 171 { /* NTSC timing for 27 Mhz ref clk */ 172 800, /* horResolution */ 173 600, /* verResolution */ 174 TV_STD_NTSC, /* standard */ 175 990, /* horTotal */ 176 740, /* verTotal */ 177 813, /* horStart */ 178 824, /* horSyncStart */ 179 632, /* verSyncStart */ 180 625592, /* defRestart */ 181 592, /* crtcPLL_N */ 182 91, /* crtcPLL_M */ 183 4, /* crtcPLL_postDiv */ 184 1022, /* pixToTV */ 185 }, 186 { /* PAL timing for 27 Mhz ref clk */ 187 800, /* horResolution */ 188 600, /* verResolution */ 189 TV_STD_PAL, /* standard */ 190 1144, /* horTotal */ 191 706, /* verTotal */ 192 812, /* horStart */ 193 824, /* horSyncStart */ 194 669, /* verSyncStart */ 195 696700, /* defRestart */ 196 1382, /* crtcPLL_N */ 197 231, /* crtcPLL_M */ 198 4, /* crtcPLL_postDiv */ 199 759, /* pixToTV */ 200 }, 201 { /* NTSC timing for 14 Mhz ref clk */ 202 800, /* horResolution */ 203 600, /* verResolution */ 204 TV_STD_NTSC, /* standard */ 205 1018, /* horTotal */ 206 727, /* verTotal */ 207 813, /* horStart */ 208 840, /* horSyncStart */ 209 633, /* verSyncStart */ 210 630627, /* defRestart */ 211 347, /* crtcPLL_N */ 212 14, /* crtcPLL_M */ 213 8, /* crtcPLL_postDiv */ 214 1022, /* pixToTV */ 215 }, 216 { /* PAL timing for 14 Mhz ref clk */ 217 800, /* horResolution */ 218 600, /* verResolution */ 219 TV_STD_PAL, /* standard */ 220 1131, /* horTotal */ 221 742, /* verTotal */ 222 813, /* horStart */ 223 840, /* horSyncStart */ 224 633, /* verSyncStart */ 225 708369, /* defRestart */ 226 211, /* crtcPLL_N */ 227 9, /* crtcPLL_M */ 228 8, /* crtcPLL_postDiv */ 229 759, /* pixToTV */ 230 }, 231 }; 232 233 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) 234 235 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, 236 uint16_t *pll_ref_freq) 237 { 238 struct drm_device *dev = radeon_encoder->base.dev; 239 struct radeon_device *rdev = dev->dev_private; 240 struct radeon_crtc *radeon_crtc; 241 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 242 const struct radeon_tv_mode_constants *const_ptr; 243 struct radeon_pll *pll; 244 245 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 246 if (radeon_crtc->crtc_id == 1) 247 pll = &rdev->clock.p2pll; 248 else 249 pll = &rdev->clock.p1pll; 250 251 if (pll_ref_freq) 252 *pll_ref_freq = pll->reference_freq; 253 254 if (tv_dac->tv_std == TV_STD_NTSC || 255 tv_dac->tv_std == TV_STD_NTSC_J || 256 tv_dac->tv_std == TV_STD_PAL_M) { 257 if (pll->reference_freq == 2700) 258 const_ptr = &available_tv_modes[0]; 259 else 260 const_ptr = &available_tv_modes[2]; 261 } else { 262 if (pll->reference_freq == 2700) 263 const_ptr = &available_tv_modes[1]; 264 else 265 const_ptr = &available_tv_modes[3]; 266 } 267 return const_ptr; 268 } 269 270 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; 271 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; 272 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; 273 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; 274 275 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, 276 unsigned n_wait_loops, unsigned cnt_threshold) 277 { 278 struct drm_device *dev = encoder->dev; 279 struct radeon_device *rdev = dev->dev_private; 280 uint32_t save_pll_test; 281 unsigned int i, j; 282 283 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); 284 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); 285 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); 286 287 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); 288 for (i = 0; i < n_tests; i++) { 289 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); 290 for (j = 0; j < n_wait_loops; j++) 291 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) 292 break; 293 } 294 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); 295 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); 296 } 297 298 299 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, 300 uint16_t addr, uint32_t value) 301 { 302 struct drm_device *dev = radeon_encoder->base.dev; 303 struct radeon_device *rdev = dev->dev_private; 304 uint32_t tmp; 305 int i = 0; 306 307 WREG32(RADEON_TV_HOST_WRITE_DATA, value); 308 309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 310 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 311 312 do { 313 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 314 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) 315 break; 316 i++; 317 } while (i < 10000); 318 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 319 } 320 321 #if 0 /* included for completeness */ 322 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 323 { 324 struct drm_device *dev = radeon_encoder->base.dev; 325 struct radeon_device *rdev = dev->dev_private; 326 uint32_t tmp; 327 int i = 0; 328 329 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 330 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 331 332 do { 333 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 334 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) 335 break; 336 i++; 337 } while (i < 10000); 338 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 339 return RREG32(RADEON_TV_HOST_READ_DATA); 340 } 341 #endif 342 343 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) 344 { 345 uint16_t h_table; 346 347 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { 348 case 0: 349 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; 350 break; 351 case 1: 352 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; 353 break; 354 case 2: 355 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; 356 break; 357 default: 358 h_table = 0; 359 break; 360 } 361 return h_table; 362 } 363 364 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) 365 { 366 uint16_t v_table; 367 368 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { 369 case 0: 370 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; 371 break; 372 case 1: 373 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; 374 break; 375 case 2: 376 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; 377 break; 378 default: 379 v_table = 0; 380 break; 381 } 382 return v_table; 383 } 384 385 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) 386 { 387 struct drm_device *dev = radeon_encoder->base.dev; 388 struct radeon_device *rdev = dev->dev_private; 389 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 390 uint16_t h_table, v_table; 391 uint32_t tmp; 392 int i; 393 394 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); 395 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); 396 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); 397 398 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { 399 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); 400 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); 401 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) 402 break; 403 } 404 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { 405 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); 406 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); 407 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) 408 break; 409 } 410 } 411 412 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) 413 { 414 struct drm_device *dev = radeon_encoder->base.dev; 415 struct radeon_device *rdev = dev->dev_private; 416 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 417 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); 418 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); 419 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); 420 } 421 422 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) 423 { 424 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 425 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 426 int restart; 427 unsigned int h_total, v_total, f_total; 428 int v_offset, h_offset; 429 u16 p1, p2, h_inc; 430 bool h_changed; 431 const struct radeon_tv_mode_constants *const_ptr; 432 433 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 434 if (!const_ptr) 435 return false; 436 437 h_total = const_ptr->hor_total; 438 v_total = const_ptr->ver_total; 439 440 if (tv_dac->tv_std == TV_STD_NTSC || 441 tv_dac->tv_std == TV_STD_NTSC_J || 442 tv_dac->tv_std == TV_STD_PAL_M || 443 tv_dac->tv_std == TV_STD_PAL_60) 444 f_total = NTSC_TV_VFTOTAL + 1; 445 else 446 f_total = PAL_TV_VFTOTAL + 1; 447 448 /* adjust positions 1&2 in hor. cod timing table */ 449 h_offset = tv_dac->h_pos * H_POS_UNIT; 450 451 if (tv_dac->tv_std == TV_STD_NTSC || 452 tv_dac->tv_std == TV_STD_NTSC_J || 453 tv_dac->tv_std == TV_STD_PAL_M) { 454 h_offset -= 50; 455 p1 = hor_timing_NTSC[H_TABLE_POS1]; 456 p2 = hor_timing_NTSC[H_TABLE_POS2]; 457 } else { 458 p1 = hor_timing_PAL[H_TABLE_POS1]; 459 p2 = hor_timing_PAL[H_TABLE_POS2]; 460 } 461 462 p1 = (u16)((int)p1 + h_offset); 463 p2 = (u16)((int)p2 - h_offset); 464 465 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || 466 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); 467 468 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; 469 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; 470 471 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ 472 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; 473 474 /* adjust restart */ 475 restart = const_ptr->def_restart; 476 477 /* 478 * convert v_pos TV lines to n. of CRTC pixels 479 */ 480 if (tv_dac->tv_std == TV_STD_NTSC || 481 tv_dac->tv_std == TV_STD_NTSC_J || 482 tv_dac->tv_std == TV_STD_PAL_M || 483 tv_dac->tv_std == TV_STD_PAL_60) 484 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 485 else 486 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 487 488 restart -= v_offset + h_offset; 489 490 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 491 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 492 493 tv_dac->tv.hrestart = restart % h_total; 494 restart /= h_total; 495 tv_dac->tv.vrestart = restart % v_total; 496 restart /= v_total; 497 tv_dac->tv.frestart = restart % f_total; 498 499 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", 500 (unsigned)tv_dac->tv.frestart, 501 (unsigned)tv_dac->tv.vrestart, 502 (unsigned)tv_dac->tv.hrestart); 503 504 /* compute h_inc from hsize */ 505 if (tv_dac->tv_std == TV_STD_NTSC || 506 tv_dac->tv_std == TV_STD_NTSC_J || 507 tv_dac->tv_std == TV_STD_PAL_M) 508 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / 509 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); 510 else 511 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / 512 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); 513 514 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 515 ((u32)h_inc << RADEON_H_INC_SHIFT); 516 517 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 518 519 return h_changed; 520 } 521 522 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 523 struct drm_display_mode *mode, 524 struct drm_display_mode *adjusted_mode) 525 { 526 struct drm_device *dev = encoder->dev; 527 struct radeon_device *rdev = dev->dev_private; 528 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 529 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 530 const struct radeon_tv_mode_constants *const_ptr; 531 struct radeon_crtc *radeon_crtc; 532 int i; 533 uint16_t pll_ref_freq; 534 uint32_t vert_space, flicker_removal, tmp; 535 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; 536 uint32_t tv_modulator_cntl1, tv_modulator_cntl2; 537 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; 538 uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; 539 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; 540 uint32_t m, n, p; 541 const uint16_t *hor_timing; 542 const uint16_t *vert_timing; 543 544 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); 545 if (!const_ptr) 546 return; 547 548 radeon_crtc = to_radeon_crtc(encoder->crtc); 549 550 tv_master_cntl = (RADEON_VIN_ASYNC_RST | 551 RADEON_CRT_FIFO_CE_EN | 552 RADEON_TV_FIFO_CE_EN | 553 RADEON_TV_ON); 554 555 if (!ASIC_IS_R300(rdev)) 556 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; 557 558 if (tv_dac->tv_std == TV_STD_NTSC || 559 tv_dac->tv_std == TV_STD_NTSC_J) 560 tv_master_cntl |= RADEON_RESTART_PHASE_FIX; 561 562 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | 563 RADEON_SYNC_TIP_LEVEL | 564 RADEON_YFLT_EN | 565 RADEON_UVFLT_EN | 566 (6 << RADEON_CY_FILT_BLEND_SHIFT)); 567 568 if (tv_dac->tv_std == TV_STD_NTSC || 569 tv_dac->tv_std == TV_STD_NTSC_J) { 570 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | 571 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 572 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | 573 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 574 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { 575 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; 576 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | 577 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 578 } else { 579 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | 580 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | 581 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 582 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | 583 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 584 } 585 586 587 tv_rgb_cntl = (RADEON_RGB_DITHER_EN 588 | RADEON_TVOUT_SCALE_EN 589 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) 590 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) 591 | RADEON_RGB_ATTEN_SEL(0x3) 592 | RADEON_RGB_ATTEN_VAL(0xc)); 593 594 if (radeon_crtc->crtc_id == 1) 595 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; 596 else { 597 if (radeon_crtc->rmx_type != RMX_OFF) 598 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; 599 else 600 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; 601 } 602 603 if (tv_dac->tv_std == TV_STD_NTSC || 604 tv_dac->tv_std == TV_STD_NTSC_J || 605 tv_dac->tv_std == TV_STD_PAL_M || 606 tv_dac->tv_std == TV_STD_PAL_60) 607 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; 608 else 609 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; 610 611 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); 612 tmp &= 0xe3ff0000; 613 tmp |= (vert_space * (1 << FRAC_BITS) / 10000); 614 tv_vscaler_cntl1 = tmp; 615 616 if (pll_ref_freq == 2700) 617 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; 618 619 if (const_ptr->hor_resolution == 1024) 620 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); 621 else 622 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); 623 624 /* scale up for int divide */ 625 tmp = const_ptr->ver_total * 2 * 1000; 626 if (tv_dac->tv_std == TV_STD_NTSC || 627 tv_dac->tv_std == TV_STD_NTSC_J || 628 tv_dac->tv_std == TV_STD_PAL_M || 629 tv_dac->tv_std == TV_STD_PAL_60) { 630 tmp /= NTSC_TV_LINES_PER_FRAME; 631 } else { 632 tmp /= PAL_TV_LINES_PER_FRAME; 633 } 634 flicker_removal = (tmp + 500) / 1000; 635 636 if (flicker_removal < 3) 637 flicker_removal = 3; 638 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) { 639 if (flicker_removal == SLOPE_limit[i]) 640 break; 641 } 642 643 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 644 5001) / 10000 / 8 | ((SLOPE_value[i] * 645 (1 << (FRAC_BITS - 1)) / 8) << 16); 646 tv_y_fall_cntl = 647 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | 648 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / 649 1024; 650 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| 651 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; 652 653 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; 654 tv_vscaler_cntl2 |= (0x10 << 24) | 655 RADEON_DITHER_MODE | 656 RADEON_Y_OUTPUT_DITHER_EN | 657 RADEON_UV_OUTPUT_DITHER_EN | 658 RADEON_UV_TO_BUF_DITHER_EN; 659 660 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; 661 tmp = ((16384 * 256 * 10) / tmp + 5) / 10; 662 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; 663 tv_dac->tv.timing_cntl = tmp; 664 665 if (tv_dac->tv_std == TV_STD_NTSC || 666 tv_dac->tv_std == TV_STD_NTSC_J || 667 tv_dac->tv_std == TV_STD_PAL_M || 668 tv_dac->tv_std == TV_STD_PAL_60) 669 tv_dac_cntl = tv_dac->ntsc_tvdac_adj; 670 else 671 tv_dac_cntl = tv_dac->pal_tvdac_adj; 672 673 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 674 675 if (tv_dac->tv_std == TV_STD_NTSC || 676 tv_dac->tv_std == TV_STD_NTSC_J) 677 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 678 else 679 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 680 681 if (tv_dac->tv_std == TV_STD_NTSC || 682 tv_dac->tv_std == TV_STD_NTSC_J) { 683 if (pll_ref_freq == 2700) { 684 m = NTSC_TV_PLL_M_27; 685 n = NTSC_TV_PLL_N_27; 686 p = NTSC_TV_PLL_P_27; 687 } else { 688 m = NTSC_TV_PLL_M_14; 689 n = NTSC_TV_PLL_N_14; 690 p = NTSC_TV_PLL_P_14; 691 } 692 } else { 693 if (pll_ref_freq == 2700) { 694 m = PAL_TV_PLL_M_27; 695 n = PAL_TV_PLL_N_27; 696 p = PAL_TV_PLL_P_27; 697 } else { 698 m = PAL_TV_PLL_M_14; 699 n = PAL_TV_PLL_N_14; 700 p = PAL_TV_PLL_P_14; 701 } 702 } 703 704 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | 705 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | 706 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | 707 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | 708 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); 709 710 tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | 711 ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | 712 ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | 713 RADEON_TVCLK_SRC_SEL_TVPLL | 714 RADEON_TVPLL_TEST_DIS); 715 716 tv_dac->tv.tv_uv_adr = 0xc8; 717 718 if (tv_dac->tv_std == TV_STD_NTSC || 719 tv_dac->tv_std == TV_STD_NTSC_J || 720 tv_dac->tv_std == TV_STD_PAL_M || 721 tv_dac->tv_std == TV_STD_PAL_60) { 722 tv_ftotal = NTSC_TV_VFTOTAL; 723 hor_timing = hor_timing_NTSC; 724 vert_timing = vert_timing_NTSC; 725 } else { 726 hor_timing = hor_timing_PAL; 727 vert_timing = vert_timing_PAL; 728 tv_ftotal = PAL_TV_VFTOTAL; 729 } 730 731 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { 732 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) 733 break; 734 } 735 736 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { 737 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) 738 break; 739 } 740 741 radeon_legacy_tv_init_restarts(encoder); 742 743 /* play with DAC_CNTL */ 744 /* play with GPIOPAD_A */ 745 /* DISP_OUTPUT_CNTL */ 746 /* use reference freq */ 747 748 /* program the TV registers */ 749 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 750 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); 751 752 tmp = RREG32(RADEON_TV_DAC_CNTL); 753 tmp &= ~RADEON_TV_DAC_NBLANK; 754 tmp |= RADEON_TV_DAC_BGSLEEP | 755 RADEON_TV_DAC_RDACPD | 756 RADEON_TV_DAC_GDACPD | 757 RADEON_TV_DAC_BDACPD; 758 WREG32(RADEON_TV_DAC_CNTL, tmp); 759 760 /* TV PLL */ 761 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); 762 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); 763 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); 764 765 radeon_wait_pll_lock(encoder, 200, 800, 135); 766 767 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); 768 769 radeon_wait_pll_lock(encoder, 300, 160, 27); 770 radeon_wait_pll_lock(encoder, 200, 800, 135); 771 772 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); 773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); 774 775 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); 776 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); 777 778 /* TV HV */ 779 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); 780 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); 781 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); 782 WREG32(RADEON_TV_HSTART, const_ptr->hor_start); 783 784 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); 785 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); 786 WREG32(RADEON_TV_FTOTAL, tv_ftotal); 787 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); 788 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); 789 790 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); 791 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); 792 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); 793 794 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 795 RADEON_CRT_ASYNC_RST)); 796 797 /* TV restarts */ 798 radeon_legacy_write_tv_restarts(radeon_encoder); 799 800 /* tv timings */ 801 radeon_restore_tv_timing_tables(radeon_encoder); 802 803 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); 804 805 /* tv std */ 806 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); 807 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); 808 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); 809 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); 810 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | 811 RADEON_C_GRN_EN | 812 RADEON_CMP_BLU_EN | 813 RADEON_DAC_DITHER_EN)); 814 815 WREG32(RADEON_TV_CRC_CNTL, 0); 816 817 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 818 819 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | 820 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); 821 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | 822 (0x100 << RADEON_Y_GAIN_SHIFT))); 823 824 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 825 826 } 827 828 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 829 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 830 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) 831 { 832 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 833 const struct radeon_tv_mode_constants *const_ptr; 834 uint32_t tmp; 835 836 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 837 if (!const_ptr) 838 return; 839 840 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | 841 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); 842 843 tmp = *h_sync_strt_wid; 844 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); 845 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | 846 (const_ptr->hor_syncstart & 7); 847 *h_sync_strt_wid = tmp; 848 849 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | 850 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); 851 852 tmp = *v_sync_strt_wid; 853 tmp &= ~RADEON_CRTC_V_SYNC_STRT; 854 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); 855 *v_sync_strt_wid = tmp; 856 } 857 858 static int get_post_div(int value) 859 { 860 int post_div; 861 switch (value) { 862 case 1: post_div = 0; break; 863 case 2: post_div = 1; break; 864 case 3: post_div = 4; break; 865 case 4: post_div = 2; break; 866 case 6: post_div = 6; break; 867 case 8: post_div = 3; break; 868 case 12: post_div = 7; break; 869 case 16: 870 default: post_div = 5; break; 871 } 872 return post_div; 873 } 874 875 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 876 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 877 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) 878 { 879 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 880 const struct radeon_tv_mode_constants *const_ptr; 881 882 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 883 if (!const_ptr) 884 return; 885 886 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; 887 888 *ppll_ref_div = const_ptr->crtcPLL_M; 889 890 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 891 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); 892 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; 893 } 894 895 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 896 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 897 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) 898 { 899 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 900 const struct radeon_tv_mode_constants *const_ptr; 901 902 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 903 if (!const_ptr) 904 return; 905 906 *htotal2_cntl = (const_ptr->hor_total & 0x7); 907 908 *p2pll_ref_div = const_ptr->crtcPLL_M; 909 910 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 911 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; 912 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; 913 } 914 915