1 #include "drmP.h"
2 #include "drm_crtc_helper.h"
3 #include "radeon.h"
4 
5 /*
6  * Integrated TV out support based on the GATOS code by
7  * Federico Ulivi <fulivi@lycos.com>
8  */
9 
10 
11 /*
12  * Limits of h/v positions (hPos & vPos)
13  */
14 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
15 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
16 
17 /*
18  * Unit for hPos (in TV clock periods)
19  */
20 #define H_POS_UNIT 10
21 
22 /*
23  * Indexes in h. code timing table for horizontal line position adjustment
24  */
25 #define H_TABLE_POS1 6
26 #define H_TABLE_POS2 8
27 
28 /*
29  * Limits of hor. size (hSize)
30  */
31 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
32 
33 /* tv standard constants */
34 #define NTSC_TV_CLOCK_T 233
35 #define NTSC_TV_VFTOTAL 1
36 #define NTSC_TV_LINES_PER_FRAME 525
37 #define NTSC_TV_ZERO_H_SIZE 479166
38 #define NTSC_TV_H_SIZE_UNIT 9478
39 
40 #define PAL_TV_CLOCK_T 188
41 #define PAL_TV_VFTOTAL 3
42 #define PAL_TV_LINES_PER_FRAME 625
43 #define PAL_TV_ZERO_H_SIZE 473200
44 #define PAL_TV_H_SIZE_UNIT 9360
45 
46 /* tv pll setting for 27 mhz ref clk */
47 #define NTSC_TV_PLL_M_27 22
48 #define NTSC_TV_PLL_N_27 175
49 #define NTSC_TV_PLL_P_27 5
50 
51 #define PAL_TV_PLL_M_27 113
52 #define PAL_TV_PLL_N_27 668
53 #define PAL_TV_PLL_P_27 3
54 
55 /* tv pll setting for 14 mhz ref clk */
56 #define NTSC_TV_PLL_M_14 33
57 #define NTSC_TV_PLL_N_14 693
58 #define NTSC_TV_PLL_P_14 7
59 
60 #define PAL_TV_PLL_M_14 19
61 #define PAL_TV_PLL_N_14 353
62 #define PAL_TV_PLL_P_14 5
63 
64 #define VERT_LEAD_IN_LINES 2
65 #define FRAC_BITS 0xe
66 #define FRAC_MASK 0x3fff
67 
68 struct radeon_tv_mode_constants {
69 	uint16_t hor_resolution;
70 	uint16_t ver_resolution;
71 	enum radeon_tv_std standard;
72 	uint16_t hor_total;
73 	uint16_t ver_total;
74 	uint16_t hor_start;
75 	uint16_t hor_syncstart;
76 	uint16_t ver_syncstart;
77 	unsigned def_restart;
78 	uint16_t crtcPLL_N;
79 	uint8_t  crtcPLL_M;
80 	uint8_t  crtcPLL_post_div;
81 	unsigned pix_to_tv;
82 };
83 
84 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
85 	0x0007,
86 	0x003f,
87 	0x0263,
88 	0x0a24,
89 	0x2a6b,
90 	0x0a36,
91 	0x126d, /* H_TABLE_POS1 */
92 	0x1bfe,
93 	0x1a8f, /* H_TABLE_POS2 */
94 	0x1ec7,
95 	0x3863,
96 	0x1bfe,
97 	0x1bfe,
98 	0x1a2a,
99 	0x1e95,
100 	0x0e31,
101 	0x201b,
102 	0
103 };
104 
105 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
106 	0x2001,
107 	0x200d,
108 	0x1006,
109 	0x0c06,
110 	0x1006,
111 	0x1818,
112 	0x21e3,
113 	0x1006,
114 	0x0c06,
115 	0x1006,
116 	0x1817,
117 	0x21d4,
118 	0x0002,
119 	0
120 };
121 
122 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
123 	0x0007,
124 	0x0058,
125 	0x027c,
126 	0x0a31,
127 	0x2a77,
128 	0x0a95,
129 	0x124f, /* H_TABLE_POS1 */
130 	0x1bfe,
131 	0x1b22, /* H_TABLE_POS2 */
132 	0x1ef9,
133 	0x387c,
134 	0x1bfe,
135 	0x1bfe,
136 	0x1b31,
137 	0x1eb5,
138 	0x0e43,
139 	0x201b,
140 	0
141 };
142 
143 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
144 	0x2001,
145 	0x200c,
146 	0x1005,
147 	0x0c05,
148 	0x1005,
149 	0x1401,
150 	0x1821,
151 	0x2240,
152 	0x1005,
153 	0x0c05,
154 	0x1005,
155 	0x1401,
156 	0x1822,
157 	0x2230,
158 	0x0002,
159 	0
160 };
161 
162 /**********************************************************************
163  *
164  * availableModes
165  *
166  * Table of all allowed modes for tv output
167  *
168  **********************************************************************/
169 static const struct radeon_tv_mode_constants available_tv_modes[] = {
170 	{   /* NTSC timing for 27 Mhz ref clk */
171 		800,                /* horResolution */
172 		600,                /* verResolution */
173 		TV_STD_NTSC,        /* standard */
174 		990,                /* horTotal */
175 		740,                /* verTotal */
176 		813,                /* horStart */
177 		824,                /* horSyncStart */
178 		632,                /* verSyncStart */
179 		625592,             /* defRestart */
180 		592,                /* crtcPLL_N */
181 		91,                 /* crtcPLL_M */
182 		4,                  /* crtcPLL_postDiv */
183 		1022,               /* pixToTV */
184 	},
185 	{   /* PAL timing for 27 Mhz ref clk */
186 		800,               /* horResolution */
187 		600,               /* verResolution */
188 		TV_STD_PAL,        /* standard */
189 		1144,              /* horTotal */
190 		706,               /* verTotal */
191 		812,               /* horStart */
192 		824,               /* horSyncStart */
193 		669,               /* verSyncStart */
194 		696700,            /* defRestart */
195 		1382,              /* crtcPLL_N */
196 		231,               /* crtcPLL_M */
197 		4,                 /* crtcPLL_postDiv */
198 		759,               /* pixToTV */
199 	},
200 	{   /* NTSC timing for 14 Mhz ref clk */
201 		800,                /* horResolution */
202 		600,                /* verResolution */
203 		TV_STD_NTSC,        /* standard */
204 		1018,               /* horTotal */
205 		727,                /* verTotal */
206 		813,                /* horStart */
207 		840,                /* horSyncStart */
208 		633,                /* verSyncStart */
209 		630627,             /* defRestart */
210 		347,                /* crtcPLL_N */
211 		14,                 /* crtcPLL_M */
212 		8,                  /* crtcPLL_postDiv */
213 		1022,               /* pixToTV */
214 	},
215 	{ /* PAL timing for 14 Mhz ref clk */
216 		800,                /* horResolution */
217 		600,                /* verResolution */
218 		TV_STD_PAL,         /* standard */
219 		1131,               /* horTotal */
220 		742,                /* verTotal */
221 		813,                /* horStart */
222 		840,                /* horSyncStart */
223 		633,                /* verSyncStart */
224 		708369,             /* defRestart */
225 		211,                /* crtcPLL_N */
226 		9,                  /* crtcPLL_M */
227 		8,                  /* crtcPLL_postDiv */
228 		759,                /* pixToTV */
229 	},
230 };
231 
232 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
233 
234 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder,
235 									    uint16_t *pll_ref_freq)
236 {
237 	struct drm_device *dev = radeon_encoder->base.dev;
238 	struct radeon_device *rdev = dev->dev_private;
239 	struct radeon_crtc *radeon_crtc;
240 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
241 	const struct radeon_tv_mode_constants *const_ptr;
242 	struct radeon_pll *pll;
243 
244 	radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
245 	if (radeon_crtc->crtc_id == 1)
246 		pll = &rdev->clock.p2pll;
247 	else
248 		pll = &rdev->clock.p1pll;
249 
250 	if (pll_ref_freq)
251 		*pll_ref_freq = pll->reference_freq;
252 
253 	if (tv_dac->tv_std == TV_STD_NTSC ||
254 	    tv_dac->tv_std == TV_STD_NTSC_J ||
255 	    tv_dac->tv_std == TV_STD_PAL_M) {
256 		if (pll->reference_freq == 2700)
257 			const_ptr = &available_tv_modes[0];
258 		else
259 			const_ptr = &available_tv_modes[2];
260 	} else {
261 		if (pll->reference_freq == 2700)
262 			const_ptr = &available_tv_modes[1];
263 		else
264 			const_ptr = &available_tv_modes[3];
265 	}
266 	return const_ptr;
267 }
268 
269 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
270 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
271 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
272 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
273 
274 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests,
275 				 unsigned n_wait_loops, unsigned cnt_threshold)
276 {
277 	struct drm_device *dev = encoder->dev;
278 	struct radeon_device *rdev = dev->dev_private;
279 	uint32_t save_pll_test;
280 	unsigned int i, j;
281 
282 	WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
283 	save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
284 	WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
285 
286 	WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
287 	for (i = 0; i < n_tests; i++) {
288 		WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
289 		for (j = 0; j < n_wait_loops; j++)
290 			if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold)
291 				break;
292 	}
293 	WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
294 	WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
295 }
296 
297 
298 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder,
299 					uint16_t addr, uint32_t value)
300 {
301 	struct drm_device *dev = radeon_encoder->base.dev;
302 	struct radeon_device *rdev = dev->dev_private;
303 	uint32_t tmp;
304 	int i = 0;
305 
306 	WREG32(RADEON_TV_HOST_WRITE_DATA, value);
307 
308 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
309 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
310 
311 	do {
312 		tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
313 		if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
314 			break;
315 		i++;
316 	} while (i < 10000);
317 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
318 }
319 
320 #if 0 /* included for completeness */
321 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr)
322 {
323 	struct drm_device *dev = radeon_encoder->base.dev;
324 	struct radeon_device *rdev = dev->dev_private;
325 	uint32_t tmp;
326 	int i = 0;
327 
328 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
329 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
330 
331 	do {
332 		tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
333 		if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
334 			break;
335 		i++;
336 	} while (i < 10000);
337 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
338 	return RREG32(RADEON_TV_HOST_READ_DATA);
339 }
340 #endif
341 
342 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
343 {
344 	uint16_t h_table;
345 
346 	switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
347 	case 0:
348 		h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
349 		break;
350 	case 1:
351 		h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
352 		break;
353 	case 2:
354 		h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
355 		break;
356 	default:
357 		h_table = 0;
358 		break;
359 	}
360 	return h_table;
361 }
362 
363 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
364 {
365 	uint16_t v_table;
366 
367 	switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
368 	case 0:
369 		v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
370 		break;
371 	case 1:
372 		v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
373 		break;
374 	case 2:
375 		v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
376 		break;
377 	default:
378 		v_table = 0;
379 		break;
380 	}
381 	return v_table;
382 }
383 
384 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder)
385 {
386 	struct drm_device *dev = radeon_encoder->base.dev;
387 	struct radeon_device *rdev = dev->dev_private;
388 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
389 	uint16_t h_table, v_table;
390 	uint32_t tmp;
391 	int i;
392 
393 	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
394 	h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
395 	v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
396 
397 	for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {
398 		tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
399 		radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
400 		if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
401 			break;
402 	}
403 	for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {
404 		tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
405 		radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
406 		if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
407 			break;
408 	}
409 }
410 
411 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder)
412 {
413 	struct drm_device *dev = radeon_encoder->base.dev;
414 	struct radeon_device *rdev = dev->dev_private;
415 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
416 	WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
417 	WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
418 	WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
419 }
420 
421 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
422 {
423 	struct drm_device *dev = encoder->dev;
424 	struct radeon_device *rdev = dev->dev_private;
425 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
426 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
427 	struct radeon_crtc *radeon_crtc;
428 	int restart;
429 	unsigned int h_total, v_total, f_total;
430 	int v_offset, h_offset;
431 	u16 p1, p2, h_inc;
432 	bool h_changed;
433 	const struct radeon_tv_mode_constants *const_ptr;
434 	struct radeon_pll *pll;
435 
436 	radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
437 	if (radeon_crtc->crtc_id == 1)
438 		pll = &rdev->clock.p2pll;
439 	else
440 		pll = &rdev->clock.p1pll;
441 
442 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
443 	if (!const_ptr)
444 		return false;
445 
446 	h_total = const_ptr->hor_total;
447 	v_total = const_ptr->ver_total;
448 
449 	if (tv_dac->tv_std == TV_STD_NTSC ||
450 	    tv_dac->tv_std == TV_STD_NTSC_J ||
451 	    tv_dac->tv_std == TV_STD_PAL_M ||
452 	    tv_dac->tv_std == TV_STD_PAL_60)
453 		f_total = NTSC_TV_VFTOTAL + 1;
454 	else
455 		f_total = PAL_TV_VFTOTAL + 1;
456 
457 	/* adjust positions 1&2 in hor. cod timing table */
458 	h_offset = tv_dac->h_pos * H_POS_UNIT;
459 
460 	if (tv_dac->tv_std == TV_STD_NTSC ||
461 	    tv_dac->tv_std == TV_STD_NTSC_J ||
462 	    tv_dac->tv_std == TV_STD_PAL_M) {
463 		h_offset -= 50;
464 		p1 = hor_timing_NTSC[H_TABLE_POS1];
465 		p2 = hor_timing_NTSC[H_TABLE_POS2];
466 	} else {
467 		p1 = hor_timing_PAL[H_TABLE_POS1];
468 		p2 = hor_timing_PAL[H_TABLE_POS2];
469 	}
470 
471 	p1 = (u16)((int)p1 + h_offset);
472 	p2 = (u16)((int)p2 - h_offset);
473 
474 	h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
475 		     p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
476 
477 	tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
478 	tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
479 
480 	/* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
481 	h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
482 
483 	/* adjust restart */
484 	restart = const_ptr->def_restart;
485 
486 	/*
487 	 * convert v_pos TV lines to n. of CRTC pixels
488 	 */
489 	if (tv_dac->tv_std == TV_STD_NTSC ||
490 	    tv_dac->tv_std == TV_STD_NTSC_J ||
491 	    tv_dac->tv_std == TV_STD_PAL_M ||
492 	    tv_dac->tv_std == TV_STD_PAL_60)
493 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
494 	else
495 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
496 
497 	restart -= v_offset + h_offset;
498 
499 	DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
500 		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
501 
502 	tv_dac->tv.hrestart = restart % h_total;
503 	restart /= h_total;
504 	tv_dac->tv.vrestart = restart % v_total;
505 	restart /= v_total;
506 	tv_dac->tv.frestart = restart % f_total;
507 
508 	DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n",
509 		  (unsigned)tv_dac->tv.frestart,
510 		  (unsigned)tv_dac->tv.vrestart,
511 		  (unsigned)tv_dac->tv.hrestart);
512 
513 	/* compute h_inc from hsize */
514 	if (tv_dac->tv_std == TV_STD_NTSC ||
515 	    tv_dac->tv_std == TV_STD_NTSC_J ||
516 	    tv_dac->tv_std == TV_STD_PAL_M)
517 		h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
518 			      (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
519 	else
520 		h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
521 			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
522 
523 	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
524 		((u32)h_inc << RADEON_H_INC_SHIFT);
525 
526 	DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
527 
528 	return h_changed;
529 }
530 
531 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
532 			       struct drm_display_mode *mode,
533 			       struct drm_display_mode *adjusted_mode)
534 {
535 	struct drm_device *dev = encoder->dev;
536 	struct radeon_device *rdev = dev->dev_private;
537 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
538 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
539 	const struct radeon_tv_mode_constants *const_ptr;
540 	struct radeon_crtc *radeon_crtc;
541 	int i;
542 	uint16_t pll_ref_freq;
543 	uint32_t vert_space, flicker_removal, tmp;
544 	uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
545 	uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
546 	uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
547 	uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
548 	uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
549 	uint32_t m, n, p;
550 	const uint16_t *hor_timing;
551 	const uint16_t *vert_timing;
552 
553 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
554 	if (!const_ptr)
555 		return;
556 
557 	radeon_crtc = to_radeon_crtc(encoder->crtc);
558 
559 	tv_master_cntl = (RADEON_VIN_ASYNC_RST |
560 			  RADEON_CRT_FIFO_CE_EN |
561 			  RADEON_TV_FIFO_CE_EN |
562 			  RADEON_TV_ON);
563 
564 	if (!ASIC_IS_R300(rdev))
565 		tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
566 
567 	if (tv_dac->tv_std == TV_STD_NTSC ||
568 	    tv_dac->tv_std == TV_STD_NTSC_J)
569 		tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
570 
571 	tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT |
572 			      RADEON_SYNC_TIP_LEVEL |
573 			      RADEON_YFLT_EN |
574 			      RADEON_UVFLT_EN |
575 			      (6 << RADEON_CY_FILT_BLEND_SHIFT));
576 
577 	if (tv_dac->tv_std == TV_STD_NTSC ||
578 	    tv_dac->tv_std == TV_STD_NTSC_J) {
579 		tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |
580 			(0x3b << RADEON_BLANK_LEVEL_SHIFT);
581 		tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
582 			((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
583 	} else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
584 		tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
585 		tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
586 			((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
587 	} else {
588 		tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN |
589 			(0x3b << RADEON_SET_UP_LEVEL_SHIFT) |
590 			(0x3b << RADEON_BLANK_LEVEL_SHIFT);
591 		tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
592 			((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
593 	}
594 
595 
596 	tv_rgb_cntl = (RADEON_RGB_DITHER_EN
597 		       | RADEON_TVOUT_SCALE_EN
598 		       | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
599 		       | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
600 		       | RADEON_RGB_ATTEN_SEL(0x3)
601 		       | RADEON_RGB_ATTEN_VAL(0xc));
602 
603 	if (radeon_crtc->crtc_id == 1)
604 		tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
605 	else {
606 		if (radeon_crtc->rmx_type != RMX_OFF)
607 			tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
608 		else
609 			tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
610 	}
611 
612 	if (tv_dac->tv_std == TV_STD_NTSC ||
613 	    tv_dac->tv_std == TV_STD_NTSC_J ||
614 	    tv_dac->tv_std == TV_STD_PAL_M ||
615 	    tv_dac->tv_std == TV_STD_PAL_60)
616 		vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
617 	else
618 		vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
619 
620 	tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
621 	tmp &= 0xe3ff0000;
622 	tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
623 	tv_vscaler_cntl1 = tmp;
624 
625 	if (pll_ref_freq == 2700)
626 		tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
627 
628 	if (const_ptr->hor_resolution == 1024)
629 		tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
630 	else
631 		tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
632 
633 	/* scale up for int divide */
634 	tmp = const_ptr->ver_total * 2 * 1000;
635 	if (tv_dac->tv_std == TV_STD_NTSC ||
636 	    tv_dac->tv_std == TV_STD_NTSC_J ||
637 	    tv_dac->tv_std == TV_STD_PAL_M ||
638 	    tv_dac->tv_std == TV_STD_PAL_60) {
639 		tmp /= NTSC_TV_LINES_PER_FRAME;
640 	} else {
641 		tmp /= PAL_TV_LINES_PER_FRAME;
642 	}
643 	flicker_removal = (tmp + 500) / 1000;
644 
645 	if (flicker_removal < 3)
646 		flicker_removal = 3;
647 	for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
648 		if (flicker_removal == SLOPE_limit[i])
649 			break;
650 	}
651 
652 	tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) +
653 				5001) / 10000 / 8 | ((SLOPE_value[i] *
654 				(1 << (FRAC_BITS - 1)) / 8) << 16);
655 	tv_y_fall_cntl =
656 		(YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
657 		RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
658 		1024;
659 	tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG|
660 		(flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
661 
662 	tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
663 	tv_vscaler_cntl2 |= (0x10 << 24) |
664 		RADEON_DITHER_MODE |
665 		RADEON_Y_OUTPUT_DITHER_EN |
666 		RADEON_UV_OUTPUT_DITHER_EN |
667 		RADEON_UV_TO_BUF_DITHER_EN;
668 
669 	tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
670 	tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
671 	tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
672 	tv_dac->tv.timing_cntl = tmp;
673 
674 	if (tv_dac->tv_std == TV_STD_NTSC ||
675 	    tv_dac->tv_std == TV_STD_NTSC_J ||
676 	    tv_dac->tv_std == TV_STD_PAL_M ||
677 	    tv_dac->tv_std == TV_STD_PAL_60)
678 		tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
679 	else
680 		tv_dac_cntl = tv_dac->pal_tvdac_adj;
681 
682 	tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
683 
684 	if (tv_dac->tv_std == TV_STD_NTSC ||
685 	    tv_dac->tv_std == TV_STD_NTSC_J)
686 		tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
687 	else
688 		tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
689 
690 	if (tv_dac->tv_std == TV_STD_NTSC ||
691 	    tv_dac->tv_std == TV_STD_NTSC_J) {
692 		if (pll_ref_freq == 2700) {
693 			m = NTSC_TV_PLL_M_27;
694 			n = NTSC_TV_PLL_N_27;
695 			p = NTSC_TV_PLL_P_27;
696 		} else {
697 			m = NTSC_TV_PLL_M_14;
698 			n = NTSC_TV_PLL_N_14;
699 			p = NTSC_TV_PLL_P_14;
700 		}
701 	} else {
702 		if (pll_ref_freq == 2700) {
703 			m = PAL_TV_PLL_M_27;
704 			n = PAL_TV_PLL_N_27;
705 			p = PAL_TV_PLL_P_27;
706 		} else {
707 			m = PAL_TV_PLL_M_14;
708 			n = PAL_TV_PLL_N_14;
709 			p = PAL_TV_PLL_P_14;
710 		}
711 	}
712 
713 	tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
714 		(((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
715 		((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
716 		(((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
717 		((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
718 
719 	tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
720 			((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
721 			((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
722 			RADEON_TVCLK_SRC_SEL_TVPLL |
723 			RADEON_TVPLL_TEST_DIS);
724 
725 	tv_dac->tv.tv_uv_adr = 0xc8;
726 
727 	if (tv_dac->tv_std == TV_STD_NTSC ||
728 	    tv_dac->tv_std == TV_STD_NTSC_J ||
729 	    tv_dac->tv_std == TV_STD_PAL_M ||
730 	    tv_dac->tv_std == TV_STD_PAL_60) {
731 		tv_ftotal = NTSC_TV_VFTOTAL;
732 		hor_timing = hor_timing_NTSC;
733 		vert_timing = vert_timing_NTSC;
734 	} else {
735 		hor_timing = hor_timing_PAL;
736 		vert_timing = vert_timing_PAL;
737 		tv_ftotal = PAL_TV_VFTOTAL;
738 	}
739 
740 	for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
741 		if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
742 			break;
743 	}
744 
745 	for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
746 		if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
747 			break;
748 	}
749 
750 	radeon_legacy_tv_init_restarts(encoder);
751 
752 	/* play with DAC_CNTL */
753 	/* play with GPIOPAD_A */
754 	/* DISP_OUTPUT_CNTL */
755 	/* use reference freq */
756 
757 	/* program the TV registers */
758 	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
759 				       RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST));
760 
761 	tmp = RREG32(RADEON_TV_DAC_CNTL);
762 	tmp &= ~RADEON_TV_DAC_NBLANK;
763 	tmp |= RADEON_TV_DAC_BGSLEEP |
764 		RADEON_TV_DAC_RDACPD |
765 		RADEON_TV_DAC_GDACPD |
766 		RADEON_TV_DAC_BDACPD;
767 	WREG32(RADEON_TV_DAC_CNTL, tmp);
768 
769 	/* TV PLL */
770 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
771 	WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
772 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
773 
774 	radeon_wait_pll_lock(encoder, 200, 800, 135);
775 
776 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
777 
778 	radeon_wait_pll_lock(encoder, 300, 160, 27);
779 	radeon_wait_pll_lock(encoder, 200, 800, 135);
780 
781 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
782 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
783 
784 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
785 	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
786 
787 	/* TV HV */
788 	WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
789 	WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
790 	WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
791 	WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
792 
793 	WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
794 	WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
795 	WREG32(RADEON_TV_FTOTAL, tv_ftotal);
796 	WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
797 	WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
798 
799 	WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
800 	WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
801 	WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
802 
803 	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
804 				       RADEON_CRT_ASYNC_RST));
805 
806 	/* TV restarts */
807 	radeon_legacy_write_tv_restarts(radeon_encoder);
808 
809 	/* tv timings */
810 	radeon_restore_tv_timing_tables(radeon_encoder);
811 
812 	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
813 
814 	/* tv std */
815 	WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
816 	WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
817 	WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
818 	WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
819 	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
820 					    RADEON_C_GRN_EN |
821 					    RADEON_CMP_BLU_EN |
822 					    RADEON_DAC_DITHER_EN));
823 
824 	WREG32(RADEON_TV_CRC_CNTL, 0);
825 
826 	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
827 
828 	WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
829 					       (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));
830 	WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
831 						(0x100 << RADEON_Y_GAIN_SHIFT)));
832 
833 	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
834 
835 }
836 
837 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
838 				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
839 				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)
840 {
841 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
842 	const struct radeon_tv_mode_constants *const_ptr;
843 	uint32_t tmp;
844 
845 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
846 	if (!const_ptr)
847 		return;
848 
849 	*h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
850 		(((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
851 
852 	tmp = *h_sync_strt_wid;
853 	tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
854 	tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
855 		(const_ptr->hor_syncstart & 7);
856 	*h_sync_strt_wid = tmp;
857 
858 	*v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
859 		((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
860 
861 	tmp = *v_sync_strt_wid;
862 	tmp &= ~RADEON_CRTC_V_SYNC_STRT;
863 	tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
864 	*v_sync_strt_wid = tmp;
865 }
866 
867 static inline int get_post_div(int value)
868 {
869 	int post_div;
870 	switch (value) {
871 	case 1: post_div = 0; break;
872 	case 2: post_div = 1; break;
873 	case 3: post_div = 4; break;
874 	case 4: post_div = 2; break;
875 	case 6: post_div = 6; break;
876 	case 8: post_div = 3; break;
877 	case 12: post_div = 7; break;
878 	case 16:
879 	default: post_div = 5; break;
880 	}
881 	return post_div;
882 }
883 
884 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
885 				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
886 				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl)
887 {
888 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
889 	const struct radeon_tv_mode_constants *const_ptr;
890 
891 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
892 	if (!const_ptr)
893 		return;
894 
895 	*htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
896 
897 	*ppll_ref_div = const_ptr->crtcPLL_M;
898 
899 	*ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
900 	*pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
901 	*pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
902 }
903 
904 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
905 				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
906 				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)
907 {
908 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
909 	const struct radeon_tv_mode_constants *const_ptr;
910 
911 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
912 	if (!const_ptr)
913 		return;
914 
915 	*htotal2_cntl = (const_ptr->hor_total & 0x7);
916 
917 	*p2pll_ref_div = const_ptr->crtcPLL_M;
918 
919 	*p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
920 	*pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
921 	*pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL;
922 }
923 
924