1 // SPDX-License-Identifier: GPL-2.0 2 #include <drm/drmP.h> 3 #include <drm/drm_crtc_helper.h> 4 #include "radeon.h" 5 6 /* 7 * Integrated TV out support based on the GATOS code by 8 * Federico Ulivi <fulivi@lycos.com> 9 */ 10 11 12 /* 13 * Limits of h/v positions (hPos & vPos) 14 */ 15 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ 16 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ 17 18 /* 19 * Unit for hPos (in TV clock periods) 20 */ 21 #define H_POS_UNIT 10 22 23 /* 24 * Indexes in h. code timing table for horizontal line position adjustment 25 */ 26 #define H_TABLE_POS1 6 27 #define H_TABLE_POS2 8 28 29 /* 30 * Limits of hor. size (hSize) 31 */ 32 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ 33 34 /* tv standard constants */ 35 #define NTSC_TV_CLOCK_T 233 36 #define NTSC_TV_VFTOTAL 1 37 #define NTSC_TV_LINES_PER_FRAME 525 38 #define NTSC_TV_ZERO_H_SIZE 479166 39 #define NTSC_TV_H_SIZE_UNIT 9478 40 41 #define PAL_TV_CLOCK_T 188 42 #define PAL_TV_VFTOTAL 3 43 #define PAL_TV_LINES_PER_FRAME 625 44 #define PAL_TV_ZERO_H_SIZE 473200 45 #define PAL_TV_H_SIZE_UNIT 9360 46 47 /* tv pll setting for 27 mhz ref clk */ 48 #define NTSC_TV_PLL_M_27 22 49 #define NTSC_TV_PLL_N_27 175 50 #define NTSC_TV_PLL_P_27 5 51 52 #define PAL_TV_PLL_M_27 113 53 #define PAL_TV_PLL_N_27 668 54 #define PAL_TV_PLL_P_27 3 55 56 /* tv pll setting for 14 mhz ref clk */ 57 #define NTSC_TV_PLL_M_14 33 58 #define NTSC_TV_PLL_N_14 693 59 #define NTSC_TV_PLL_P_14 7 60 61 #define PAL_TV_PLL_M_14 19 62 #define PAL_TV_PLL_N_14 353 63 #define PAL_TV_PLL_P_14 5 64 65 #define VERT_LEAD_IN_LINES 2 66 #define FRAC_BITS 0xe 67 #define FRAC_MASK 0x3fff 68 69 struct radeon_tv_mode_constants { 70 uint16_t hor_resolution; 71 uint16_t ver_resolution; 72 enum radeon_tv_std standard; 73 uint16_t hor_total; 74 uint16_t ver_total; 75 uint16_t hor_start; 76 uint16_t hor_syncstart; 77 uint16_t ver_syncstart; 78 unsigned def_restart; 79 uint16_t crtcPLL_N; 80 uint8_t crtcPLL_M; 81 uint8_t crtcPLL_post_div; 82 unsigned pix_to_tv; 83 }; 84 85 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 86 0x0007, 87 0x003f, 88 0x0263, 89 0x0a24, 90 0x2a6b, 91 0x0a36, 92 0x126d, /* H_TABLE_POS1 */ 93 0x1bfe, 94 0x1a8f, /* H_TABLE_POS2 */ 95 0x1ec7, 96 0x3863, 97 0x1bfe, 98 0x1bfe, 99 0x1a2a, 100 0x1e95, 101 0x0e31, 102 0x201b, 103 0 104 }; 105 106 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 107 0x2001, 108 0x200d, 109 0x1006, 110 0x0c06, 111 0x1006, 112 0x1818, 113 0x21e3, 114 0x1006, 115 0x0c06, 116 0x1006, 117 0x1817, 118 0x21d4, 119 0x0002, 120 0 121 }; 122 123 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 124 0x0007, 125 0x0058, 126 0x027c, 127 0x0a31, 128 0x2a77, 129 0x0a95, 130 0x124f, /* H_TABLE_POS1 */ 131 0x1bfe, 132 0x1b22, /* H_TABLE_POS2 */ 133 0x1ef9, 134 0x387c, 135 0x1bfe, 136 0x1bfe, 137 0x1b31, 138 0x1eb5, 139 0x0e43, 140 0x201b, 141 0 142 }; 143 144 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 145 0x2001, 146 0x200c, 147 0x1005, 148 0x0c05, 149 0x1005, 150 0x1401, 151 0x1821, 152 0x2240, 153 0x1005, 154 0x0c05, 155 0x1005, 156 0x1401, 157 0x1822, 158 0x2230, 159 0x0002, 160 0 161 }; 162 163 /********************************************************************** 164 * 165 * availableModes 166 * 167 * Table of all allowed modes for tv output 168 * 169 **********************************************************************/ 170 static const struct radeon_tv_mode_constants available_tv_modes[] = { 171 { /* NTSC timing for 27 Mhz ref clk */ 172 800, /* horResolution */ 173 600, /* verResolution */ 174 TV_STD_NTSC, /* standard */ 175 990, /* horTotal */ 176 740, /* verTotal */ 177 813, /* horStart */ 178 824, /* horSyncStart */ 179 632, /* verSyncStart */ 180 625592, /* defRestart */ 181 592, /* crtcPLL_N */ 182 91, /* crtcPLL_M */ 183 4, /* crtcPLL_postDiv */ 184 1022, /* pixToTV */ 185 }, 186 { /* PAL timing for 27 Mhz ref clk */ 187 800, /* horResolution */ 188 600, /* verResolution */ 189 TV_STD_PAL, /* standard */ 190 1144, /* horTotal */ 191 706, /* verTotal */ 192 812, /* horStart */ 193 824, /* horSyncStart */ 194 669, /* verSyncStart */ 195 696700, /* defRestart */ 196 1382, /* crtcPLL_N */ 197 231, /* crtcPLL_M */ 198 4, /* crtcPLL_postDiv */ 199 759, /* pixToTV */ 200 }, 201 { /* NTSC timing for 14 Mhz ref clk */ 202 800, /* horResolution */ 203 600, /* verResolution */ 204 TV_STD_NTSC, /* standard */ 205 1018, /* horTotal */ 206 727, /* verTotal */ 207 813, /* horStart */ 208 840, /* horSyncStart */ 209 633, /* verSyncStart */ 210 630627, /* defRestart */ 211 347, /* crtcPLL_N */ 212 14, /* crtcPLL_M */ 213 8, /* crtcPLL_postDiv */ 214 1022, /* pixToTV */ 215 }, 216 { /* PAL timing for 14 Mhz ref clk */ 217 800, /* horResolution */ 218 600, /* verResolution */ 219 TV_STD_PAL, /* standard */ 220 1131, /* horTotal */ 221 742, /* verTotal */ 222 813, /* horStart */ 223 840, /* horSyncStart */ 224 633, /* verSyncStart */ 225 708369, /* defRestart */ 226 211, /* crtcPLL_N */ 227 9, /* crtcPLL_M */ 228 8, /* crtcPLL_postDiv */ 229 759, /* pixToTV */ 230 }, 231 }; 232 233 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) 234 235 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, 236 uint16_t *pll_ref_freq) 237 { 238 struct drm_device *dev = radeon_encoder->base.dev; 239 struct radeon_device *rdev = dev->dev_private; 240 struct radeon_crtc *radeon_crtc; 241 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 242 const struct radeon_tv_mode_constants *const_ptr; 243 struct radeon_pll *pll; 244 245 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 246 if (radeon_crtc->crtc_id == 1) 247 pll = &rdev->clock.p2pll; 248 else 249 pll = &rdev->clock.p1pll; 250 251 if (pll_ref_freq) 252 *pll_ref_freq = pll->reference_freq; 253 254 if (tv_dac->tv_std == TV_STD_NTSC || 255 tv_dac->tv_std == TV_STD_NTSC_J || 256 tv_dac->tv_std == TV_STD_PAL_M) { 257 if (pll->reference_freq == 2700) 258 const_ptr = &available_tv_modes[0]; 259 else 260 const_ptr = &available_tv_modes[2]; 261 } else { 262 if (pll->reference_freq == 2700) 263 const_ptr = &available_tv_modes[1]; 264 else 265 const_ptr = &available_tv_modes[3]; 266 } 267 return const_ptr; 268 } 269 270 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; 271 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; 272 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; 273 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; 274 275 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, 276 unsigned n_wait_loops, unsigned cnt_threshold) 277 { 278 struct drm_device *dev = encoder->dev; 279 struct radeon_device *rdev = dev->dev_private; 280 uint32_t save_pll_test; 281 unsigned int i, j; 282 283 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); 284 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); 285 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); 286 287 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); 288 for (i = 0; i < n_tests; i++) { 289 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); 290 for (j = 0; j < n_wait_loops; j++) 291 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) 292 break; 293 } 294 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); 295 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); 296 } 297 298 299 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, 300 uint16_t addr, uint32_t value) 301 { 302 struct drm_device *dev = radeon_encoder->base.dev; 303 struct radeon_device *rdev = dev->dev_private; 304 uint32_t tmp; 305 int i = 0; 306 307 WREG32(RADEON_TV_HOST_WRITE_DATA, value); 308 309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 310 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 311 312 do { 313 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 314 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) 315 break; 316 i++; 317 } while (i < 10000); 318 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 319 } 320 321 #if 0 /* included for completeness */ 322 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 323 { 324 struct drm_device *dev = radeon_encoder->base.dev; 325 struct radeon_device *rdev = dev->dev_private; 326 uint32_t tmp; 327 int i = 0; 328 329 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 330 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 331 332 do { 333 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 334 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) 335 break; 336 i++; 337 } while (i < 10000); 338 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 339 return RREG32(RADEON_TV_HOST_READ_DATA); 340 } 341 #endif 342 343 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) 344 { 345 uint16_t h_table; 346 347 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { 348 case 0: 349 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; 350 break; 351 case 1: 352 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; 353 break; 354 case 2: 355 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; 356 break; 357 default: 358 h_table = 0; 359 break; 360 } 361 return h_table; 362 } 363 364 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) 365 { 366 uint16_t v_table; 367 368 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { 369 case 0: 370 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; 371 break; 372 case 1: 373 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; 374 break; 375 case 2: 376 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; 377 break; 378 default: 379 v_table = 0; 380 break; 381 } 382 return v_table; 383 } 384 385 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) 386 { 387 struct drm_device *dev = radeon_encoder->base.dev; 388 struct radeon_device *rdev = dev->dev_private; 389 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 390 uint16_t h_table, v_table; 391 uint32_t tmp; 392 int i; 393 394 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); 395 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); 396 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); 397 398 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { 399 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); 400 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); 401 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) 402 break; 403 } 404 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { 405 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); 406 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); 407 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) 408 break; 409 } 410 } 411 412 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) 413 { 414 struct drm_device *dev = radeon_encoder->base.dev; 415 struct radeon_device *rdev = dev->dev_private; 416 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 417 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); 418 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); 419 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); 420 } 421 422 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) 423 { 424 struct drm_device *dev = encoder->dev; 425 struct radeon_device *rdev = dev->dev_private; 426 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 427 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 428 struct radeon_crtc *radeon_crtc; 429 int restart; 430 unsigned int h_total, v_total, f_total; 431 int v_offset, h_offset; 432 u16 p1, p2, h_inc; 433 bool h_changed; 434 const struct radeon_tv_mode_constants *const_ptr; 435 struct radeon_pll *pll; 436 437 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 438 if (radeon_crtc->crtc_id == 1) 439 pll = &rdev->clock.p2pll; 440 else 441 pll = &rdev->clock.p1pll; 442 443 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 444 if (!const_ptr) 445 return false; 446 447 h_total = const_ptr->hor_total; 448 v_total = const_ptr->ver_total; 449 450 if (tv_dac->tv_std == TV_STD_NTSC || 451 tv_dac->tv_std == TV_STD_NTSC_J || 452 tv_dac->tv_std == TV_STD_PAL_M || 453 tv_dac->tv_std == TV_STD_PAL_60) 454 f_total = NTSC_TV_VFTOTAL + 1; 455 else 456 f_total = PAL_TV_VFTOTAL + 1; 457 458 /* adjust positions 1&2 in hor. cod timing table */ 459 h_offset = tv_dac->h_pos * H_POS_UNIT; 460 461 if (tv_dac->tv_std == TV_STD_NTSC || 462 tv_dac->tv_std == TV_STD_NTSC_J || 463 tv_dac->tv_std == TV_STD_PAL_M) { 464 h_offset -= 50; 465 p1 = hor_timing_NTSC[H_TABLE_POS1]; 466 p2 = hor_timing_NTSC[H_TABLE_POS2]; 467 } else { 468 p1 = hor_timing_PAL[H_TABLE_POS1]; 469 p2 = hor_timing_PAL[H_TABLE_POS2]; 470 } 471 472 p1 = (u16)((int)p1 + h_offset); 473 p2 = (u16)((int)p2 - h_offset); 474 475 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || 476 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); 477 478 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; 479 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; 480 481 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ 482 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; 483 484 /* adjust restart */ 485 restart = const_ptr->def_restart; 486 487 /* 488 * convert v_pos TV lines to n. of CRTC pixels 489 */ 490 if (tv_dac->tv_std == TV_STD_NTSC || 491 tv_dac->tv_std == TV_STD_NTSC_J || 492 tv_dac->tv_std == TV_STD_PAL_M || 493 tv_dac->tv_std == TV_STD_PAL_60) 494 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 495 else 496 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 497 498 restart -= v_offset + h_offset; 499 500 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 501 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 502 503 tv_dac->tv.hrestart = restart % h_total; 504 restart /= h_total; 505 tv_dac->tv.vrestart = restart % v_total; 506 restart /= v_total; 507 tv_dac->tv.frestart = restart % f_total; 508 509 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", 510 (unsigned)tv_dac->tv.frestart, 511 (unsigned)tv_dac->tv.vrestart, 512 (unsigned)tv_dac->tv.hrestart); 513 514 /* compute h_inc from hsize */ 515 if (tv_dac->tv_std == TV_STD_NTSC || 516 tv_dac->tv_std == TV_STD_NTSC_J || 517 tv_dac->tv_std == TV_STD_PAL_M) 518 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / 519 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); 520 else 521 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / 522 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); 523 524 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 525 ((u32)h_inc << RADEON_H_INC_SHIFT); 526 527 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 528 529 return h_changed; 530 } 531 532 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 533 struct drm_display_mode *mode, 534 struct drm_display_mode *adjusted_mode) 535 { 536 struct drm_device *dev = encoder->dev; 537 struct radeon_device *rdev = dev->dev_private; 538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 539 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 540 const struct radeon_tv_mode_constants *const_ptr; 541 struct radeon_crtc *radeon_crtc; 542 int i; 543 uint16_t pll_ref_freq; 544 uint32_t vert_space, flicker_removal, tmp; 545 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; 546 uint32_t tv_modulator_cntl1, tv_modulator_cntl2; 547 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; 548 uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; 549 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; 550 uint32_t m, n, p; 551 const uint16_t *hor_timing; 552 const uint16_t *vert_timing; 553 554 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); 555 if (!const_ptr) 556 return; 557 558 radeon_crtc = to_radeon_crtc(encoder->crtc); 559 560 tv_master_cntl = (RADEON_VIN_ASYNC_RST | 561 RADEON_CRT_FIFO_CE_EN | 562 RADEON_TV_FIFO_CE_EN | 563 RADEON_TV_ON); 564 565 if (!ASIC_IS_R300(rdev)) 566 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; 567 568 if (tv_dac->tv_std == TV_STD_NTSC || 569 tv_dac->tv_std == TV_STD_NTSC_J) 570 tv_master_cntl |= RADEON_RESTART_PHASE_FIX; 571 572 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | 573 RADEON_SYNC_TIP_LEVEL | 574 RADEON_YFLT_EN | 575 RADEON_UVFLT_EN | 576 (6 << RADEON_CY_FILT_BLEND_SHIFT)); 577 578 if (tv_dac->tv_std == TV_STD_NTSC || 579 tv_dac->tv_std == TV_STD_NTSC_J) { 580 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | 581 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 582 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | 583 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 584 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { 585 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; 586 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | 587 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 588 } else { 589 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | 590 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | 591 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 592 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | 593 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 594 } 595 596 597 tv_rgb_cntl = (RADEON_RGB_DITHER_EN 598 | RADEON_TVOUT_SCALE_EN 599 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) 600 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) 601 | RADEON_RGB_ATTEN_SEL(0x3) 602 | RADEON_RGB_ATTEN_VAL(0xc)); 603 604 if (radeon_crtc->crtc_id == 1) 605 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; 606 else { 607 if (radeon_crtc->rmx_type != RMX_OFF) 608 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; 609 else 610 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; 611 } 612 613 if (tv_dac->tv_std == TV_STD_NTSC || 614 tv_dac->tv_std == TV_STD_NTSC_J || 615 tv_dac->tv_std == TV_STD_PAL_M || 616 tv_dac->tv_std == TV_STD_PAL_60) 617 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; 618 else 619 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; 620 621 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); 622 tmp &= 0xe3ff0000; 623 tmp |= (vert_space * (1 << FRAC_BITS) / 10000); 624 tv_vscaler_cntl1 = tmp; 625 626 if (pll_ref_freq == 2700) 627 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; 628 629 if (const_ptr->hor_resolution == 1024) 630 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); 631 else 632 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); 633 634 /* scale up for int divide */ 635 tmp = const_ptr->ver_total * 2 * 1000; 636 if (tv_dac->tv_std == TV_STD_NTSC || 637 tv_dac->tv_std == TV_STD_NTSC_J || 638 tv_dac->tv_std == TV_STD_PAL_M || 639 tv_dac->tv_std == TV_STD_PAL_60) { 640 tmp /= NTSC_TV_LINES_PER_FRAME; 641 } else { 642 tmp /= PAL_TV_LINES_PER_FRAME; 643 } 644 flicker_removal = (tmp + 500) / 1000; 645 646 if (flicker_removal < 3) 647 flicker_removal = 3; 648 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) { 649 if (flicker_removal == SLOPE_limit[i]) 650 break; 651 } 652 653 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 654 5001) / 10000 / 8 | ((SLOPE_value[i] * 655 (1 << (FRAC_BITS - 1)) / 8) << 16); 656 tv_y_fall_cntl = 657 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | 658 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / 659 1024; 660 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| 661 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; 662 663 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; 664 tv_vscaler_cntl2 |= (0x10 << 24) | 665 RADEON_DITHER_MODE | 666 RADEON_Y_OUTPUT_DITHER_EN | 667 RADEON_UV_OUTPUT_DITHER_EN | 668 RADEON_UV_TO_BUF_DITHER_EN; 669 670 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; 671 tmp = ((16384 * 256 * 10) / tmp + 5) / 10; 672 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; 673 tv_dac->tv.timing_cntl = tmp; 674 675 if (tv_dac->tv_std == TV_STD_NTSC || 676 tv_dac->tv_std == TV_STD_NTSC_J || 677 tv_dac->tv_std == TV_STD_PAL_M || 678 tv_dac->tv_std == TV_STD_PAL_60) 679 tv_dac_cntl = tv_dac->ntsc_tvdac_adj; 680 else 681 tv_dac_cntl = tv_dac->pal_tvdac_adj; 682 683 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 684 685 if (tv_dac->tv_std == TV_STD_NTSC || 686 tv_dac->tv_std == TV_STD_NTSC_J) 687 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 688 else 689 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 690 691 if (tv_dac->tv_std == TV_STD_NTSC || 692 tv_dac->tv_std == TV_STD_NTSC_J) { 693 if (pll_ref_freq == 2700) { 694 m = NTSC_TV_PLL_M_27; 695 n = NTSC_TV_PLL_N_27; 696 p = NTSC_TV_PLL_P_27; 697 } else { 698 m = NTSC_TV_PLL_M_14; 699 n = NTSC_TV_PLL_N_14; 700 p = NTSC_TV_PLL_P_14; 701 } 702 } else { 703 if (pll_ref_freq == 2700) { 704 m = PAL_TV_PLL_M_27; 705 n = PAL_TV_PLL_N_27; 706 p = PAL_TV_PLL_P_27; 707 } else { 708 m = PAL_TV_PLL_M_14; 709 n = PAL_TV_PLL_N_14; 710 p = PAL_TV_PLL_P_14; 711 } 712 } 713 714 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | 715 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | 716 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | 717 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | 718 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); 719 720 tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | 721 ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | 722 ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | 723 RADEON_TVCLK_SRC_SEL_TVPLL | 724 RADEON_TVPLL_TEST_DIS); 725 726 tv_dac->tv.tv_uv_adr = 0xc8; 727 728 if (tv_dac->tv_std == TV_STD_NTSC || 729 tv_dac->tv_std == TV_STD_NTSC_J || 730 tv_dac->tv_std == TV_STD_PAL_M || 731 tv_dac->tv_std == TV_STD_PAL_60) { 732 tv_ftotal = NTSC_TV_VFTOTAL; 733 hor_timing = hor_timing_NTSC; 734 vert_timing = vert_timing_NTSC; 735 } else { 736 hor_timing = hor_timing_PAL; 737 vert_timing = vert_timing_PAL; 738 tv_ftotal = PAL_TV_VFTOTAL; 739 } 740 741 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { 742 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) 743 break; 744 } 745 746 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { 747 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) 748 break; 749 } 750 751 radeon_legacy_tv_init_restarts(encoder); 752 753 /* play with DAC_CNTL */ 754 /* play with GPIOPAD_A */ 755 /* DISP_OUTPUT_CNTL */ 756 /* use reference freq */ 757 758 /* program the TV registers */ 759 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 760 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); 761 762 tmp = RREG32(RADEON_TV_DAC_CNTL); 763 tmp &= ~RADEON_TV_DAC_NBLANK; 764 tmp |= RADEON_TV_DAC_BGSLEEP | 765 RADEON_TV_DAC_RDACPD | 766 RADEON_TV_DAC_GDACPD | 767 RADEON_TV_DAC_BDACPD; 768 WREG32(RADEON_TV_DAC_CNTL, tmp); 769 770 /* TV PLL */ 771 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); 772 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); 773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); 774 775 radeon_wait_pll_lock(encoder, 200, 800, 135); 776 777 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); 778 779 radeon_wait_pll_lock(encoder, 300, 160, 27); 780 radeon_wait_pll_lock(encoder, 200, 800, 135); 781 782 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); 783 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); 784 785 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); 786 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); 787 788 /* TV HV */ 789 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); 790 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); 791 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); 792 WREG32(RADEON_TV_HSTART, const_ptr->hor_start); 793 794 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); 795 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); 796 WREG32(RADEON_TV_FTOTAL, tv_ftotal); 797 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); 798 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); 799 800 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); 801 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); 802 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); 803 804 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 805 RADEON_CRT_ASYNC_RST)); 806 807 /* TV restarts */ 808 radeon_legacy_write_tv_restarts(radeon_encoder); 809 810 /* tv timings */ 811 radeon_restore_tv_timing_tables(radeon_encoder); 812 813 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); 814 815 /* tv std */ 816 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); 817 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); 818 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); 819 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); 820 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | 821 RADEON_C_GRN_EN | 822 RADEON_CMP_BLU_EN | 823 RADEON_DAC_DITHER_EN)); 824 825 WREG32(RADEON_TV_CRC_CNTL, 0); 826 827 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 828 829 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | 830 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); 831 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | 832 (0x100 << RADEON_Y_GAIN_SHIFT))); 833 834 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 835 836 } 837 838 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 839 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 840 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) 841 { 842 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 843 const struct radeon_tv_mode_constants *const_ptr; 844 uint32_t tmp; 845 846 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 847 if (!const_ptr) 848 return; 849 850 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | 851 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); 852 853 tmp = *h_sync_strt_wid; 854 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); 855 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | 856 (const_ptr->hor_syncstart & 7); 857 *h_sync_strt_wid = tmp; 858 859 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | 860 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); 861 862 tmp = *v_sync_strt_wid; 863 tmp &= ~RADEON_CRTC_V_SYNC_STRT; 864 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); 865 *v_sync_strt_wid = tmp; 866 } 867 868 static int get_post_div(int value) 869 { 870 int post_div; 871 switch (value) { 872 case 1: post_div = 0; break; 873 case 2: post_div = 1; break; 874 case 3: post_div = 4; break; 875 case 4: post_div = 2; break; 876 case 6: post_div = 6; break; 877 case 8: post_div = 3; break; 878 case 12: post_div = 7; break; 879 case 16: 880 default: post_div = 5; break; 881 } 882 return post_div; 883 } 884 885 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 886 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 887 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) 888 { 889 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 890 const struct radeon_tv_mode_constants *const_ptr; 891 892 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 893 if (!const_ptr) 894 return; 895 896 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; 897 898 *ppll_ref_div = const_ptr->crtcPLL_M; 899 900 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 901 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); 902 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; 903 } 904 905 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 906 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 907 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) 908 { 909 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 910 const struct radeon_tv_mode_constants *const_ptr; 911 912 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 913 if (!const_ptr) 914 return; 915 916 *htotal2_cntl = (const_ptr->hor_total & 0x7); 917 918 *p2pll_ref_div = const_ptr->crtcPLL_M; 919 920 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 921 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; 922 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; 923 } 924 925