1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "atom.h"
32 #include <linux/backlight.h>
33 #ifdef CONFIG_PMAC_BACKLIGHT
34 #include <asm/backlight.h>
35 #endif
36 
37 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
38 {
39 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
40 	const struct drm_encoder_helper_funcs *encoder_funcs;
41 
42 	encoder_funcs = encoder->helper_private;
43 	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
44 	radeon_encoder->active_device = 0;
45 }
46 
47 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
48 {
49 	struct drm_device *dev = encoder->dev;
50 	struct radeon_device *rdev = dev->dev_private;
51 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
52 	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
53 	int panel_pwr_delay = 2000;
54 	bool is_mac = false;
55 	uint8_t backlight_level;
56 	DRM_DEBUG_KMS("\n");
57 
58 	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
59 	backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
60 
61 	if (radeon_encoder->enc_priv) {
62 		if (rdev->is_atom_bios) {
63 			struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
64 			panel_pwr_delay = lvds->panel_pwr_delay;
65 			if (lvds->bl_dev)
66 				backlight_level = lvds->backlight_level;
67 		} else {
68 			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
69 			panel_pwr_delay = lvds->panel_pwr_delay;
70 			if (lvds->bl_dev)
71 				backlight_level = lvds->backlight_level;
72 		}
73 	}
74 
75 	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
76 	 * Taken from radeonfb.
77 	 */
78 	if ((rdev->mode_info.connector_table == CT_IBOOK) ||
79 	    (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
80 	    (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
81 	    (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
82 		is_mac = true;
83 
84 	switch (mode) {
85 	case DRM_MODE_DPMS_ON:
86 		disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
87 		disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
88 		WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
89 		lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
90 		lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
91 		WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
92 		mdelay(1);
93 
94 		lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
95 		lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
96 		WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
97 
98 		lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
99 				   RADEON_LVDS_BL_MOD_LEVEL_MASK);
100 		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
101 				  RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
102 				  (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
103 		if (is_mac)
104 			lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
105 		mdelay(panel_pwr_delay);
106 		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
107 		break;
108 	case DRM_MODE_DPMS_STANDBY:
109 	case DRM_MODE_DPMS_SUSPEND:
110 	case DRM_MODE_DPMS_OFF:
111 		pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
112 		WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
113 		lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
114 		if (is_mac) {
115 			lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
116 			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
117 			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
118 		} else {
119 			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
120 			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
121 		}
122 		mdelay(panel_pwr_delay);
123 		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
124 		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
125 		mdelay(panel_pwr_delay);
126 		break;
127 	}
128 
129 	if (rdev->is_atom_bios)
130 		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
131 	else
132 		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
133 
134 }
135 
136 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
137 {
138 	struct radeon_device *rdev = encoder->dev->dev_private;
139 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
140 	DRM_DEBUG("\n");
141 
142 	if (radeon_encoder->enc_priv) {
143 		if (rdev->is_atom_bios) {
144 			struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
145 			lvds->dpms_mode = mode;
146 		} else {
147 			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
148 			lvds->dpms_mode = mode;
149 		}
150 	}
151 
152 	radeon_legacy_lvds_update(encoder, mode);
153 }
154 
155 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
156 {
157 	struct radeon_device *rdev = encoder->dev->dev_private;
158 
159 	if (rdev->is_atom_bios)
160 		radeon_atom_output_lock(encoder, true);
161 	else
162 		radeon_combios_output_lock(encoder, true);
163 	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
164 }
165 
166 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
167 {
168 	struct radeon_device *rdev = encoder->dev->dev_private;
169 
170 	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
171 	if (rdev->is_atom_bios)
172 		radeon_atom_output_lock(encoder, false);
173 	else
174 		radeon_combios_output_lock(encoder, false);
175 }
176 
177 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
178 					struct drm_display_mode *mode,
179 					struct drm_display_mode *adjusted_mode)
180 {
181 	struct drm_device *dev = encoder->dev;
182 	struct radeon_device *rdev = dev->dev_private;
183 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
184 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
185 	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
186 
187 	DRM_DEBUG_KMS("\n");
188 
189 	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
190 	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
191 
192 	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
193 	if (rdev->is_atom_bios) {
194 		/* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
195 		 * need to call that on resume to set up the reg properly.
196 		 */
197 		radeon_encoder->pixel_clock = adjusted_mode->clock;
198 		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
199 		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
200 	} else {
201 		struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
202 		if (lvds) {
203 			DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
204 			lvds_gen_cntl = lvds->lvds_gen_cntl;
205 			lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
206 					      (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
207 			lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
208 					     (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
209 		} else
210 			lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
211 	}
212 	lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
213 	lvds_gen_cntl &= ~(RADEON_LVDS_ON |
214 			   RADEON_LVDS_BLON |
215 			   RADEON_LVDS_EN |
216 			   RADEON_LVDS_RST_FM);
217 
218 	if (ASIC_IS_R300(rdev))
219 		lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
220 
221 	if (radeon_crtc->crtc_id == 0) {
222 		if (ASIC_IS_R300(rdev)) {
223 			if (radeon_encoder->rmx_type != RMX_OFF)
224 				lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
225 		} else
226 			lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
227 	} else {
228 		if (ASIC_IS_R300(rdev))
229 			lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
230 		else
231 			lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
232 	}
233 
234 	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
235 	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
236 	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
237 
238 	if (rdev->family == CHIP_RV410)
239 		WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
240 
241 	if (rdev->is_atom_bios)
242 		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
243 	else
244 		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
245 }
246 
247 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
248 				     const struct drm_display_mode *mode,
249 				     struct drm_display_mode *adjusted_mode)
250 {
251 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
252 
253 	/* set the active encoder to connector routing */
254 	radeon_encoder_set_active_device(encoder);
255 	drm_mode_set_crtcinfo(adjusted_mode, 0);
256 
257 	/* get the native mode for LVDS */
258 	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
259 		radeon_panel_mode_fixup(encoder, adjusted_mode);
260 
261 	return true;
262 }
263 
264 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
265 	.dpms = radeon_legacy_lvds_dpms,
266 	.mode_fixup = radeon_legacy_mode_fixup,
267 	.prepare = radeon_legacy_lvds_prepare,
268 	.mode_set = radeon_legacy_lvds_mode_set,
269 	.commit = radeon_legacy_lvds_commit,
270 	.disable = radeon_legacy_encoder_disable,
271 };
272 
273 u8
274 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
275 {
276 	struct drm_device *dev = radeon_encoder->base.dev;
277 	struct radeon_device *rdev = dev->dev_private;
278 	u8 backlight_level;
279 
280 	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
281 			   RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
282 
283 	return backlight_level;
284 }
285 
286 void
287 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
288 {
289 	struct drm_device *dev = radeon_encoder->base.dev;
290 	struct radeon_device *rdev = dev->dev_private;
291 	int dpms_mode = DRM_MODE_DPMS_ON;
292 
293 	if (radeon_encoder->enc_priv) {
294 		if (rdev->is_atom_bios) {
295 			struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
296 			if (lvds->backlight_level > 0)
297 				dpms_mode = lvds->dpms_mode;
298 			else
299 				dpms_mode = DRM_MODE_DPMS_OFF;
300 			lvds->backlight_level = level;
301 		} else {
302 			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
303 			if (lvds->backlight_level > 0)
304 				dpms_mode = lvds->dpms_mode;
305 			else
306 				dpms_mode = DRM_MODE_DPMS_OFF;
307 			lvds->backlight_level = level;
308 		}
309 	}
310 
311 	radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
312 }
313 
314 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
315 
316 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
317 {
318 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
319 	uint8_t level;
320 
321 	/* Convert brightness to hardware level */
322 	if (bd->props.brightness < 0)
323 		level = 0;
324 	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
325 		level = RADEON_MAX_BL_LEVEL;
326 	else
327 		level = bd->props.brightness;
328 
329 	if (pdata->negative)
330 		level = RADEON_MAX_BL_LEVEL - level;
331 
332 	return level;
333 }
334 
335 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
336 {
337 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
338 	struct radeon_encoder *radeon_encoder = pdata->encoder;
339 
340 	radeon_legacy_set_backlight_level(radeon_encoder,
341 					  radeon_legacy_lvds_level(bd));
342 
343 	return 0;
344 }
345 
346 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
347 {
348 	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
349 	struct radeon_encoder *radeon_encoder = pdata->encoder;
350 	struct drm_device *dev = radeon_encoder->base.dev;
351 	struct radeon_device *rdev = dev->dev_private;
352 	uint8_t backlight_level;
353 
354 	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
355 			   RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
356 
357 	return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
358 }
359 
360 static const struct backlight_ops radeon_backlight_ops = {
361 	.get_brightness = radeon_legacy_backlight_get_brightness,
362 	.update_status	= radeon_legacy_backlight_update_status,
363 };
364 
365 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
366 				  struct drm_connector *drm_connector)
367 {
368 	struct drm_device *dev = radeon_encoder->base.dev;
369 	struct radeon_device *rdev = dev->dev_private;
370 	struct backlight_device *bd;
371 	struct backlight_properties props;
372 	struct radeon_backlight_privdata *pdata;
373 	uint8_t backlight_level;
374 	char bl_name[16];
375 
376 	if (!radeon_encoder->enc_priv)
377 		return;
378 
379 #ifdef CONFIG_PMAC_BACKLIGHT
380 	if (!pmac_has_backlight_type("ati") &&
381 	    !pmac_has_backlight_type("mnca"))
382 		return;
383 #endif
384 
385 	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
386 	if (!pdata) {
387 		DRM_ERROR("Memory allocation failed\n");
388 		goto error;
389 	}
390 
391 	memset(&props, 0, sizeof(props));
392 	props.max_brightness = RADEON_MAX_BL_LEVEL;
393 	props.type = BACKLIGHT_RAW;
394 	snprintf(bl_name, sizeof(bl_name),
395 		 "radeon_bl%d", dev->primary->index);
396 	bd = backlight_device_register(bl_name, drm_connector->kdev,
397 				       pdata, &radeon_backlight_ops, &props);
398 	if (IS_ERR(bd)) {
399 		DRM_ERROR("Backlight registration failed\n");
400 		goto error;
401 	}
402 
403 	pdata->encoder = radeon_encoder;
404 
405 	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
406 			   RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
407 
408 	/* First, try to detect backlight level sense based on the assumption
409 	 * that firmware set it up at full brightness
410 	 */
411 	if (backlight_level == 0)
412 		pdata->negative = true;
413 	else if (backlight_level == 0xff)
414 		pdata->negative = false;
415 	else {
416 		/* XXX hack... maybe some day we can figure out in what direction
417 		 * backlight should work on a given panel?
418 		 */
419 		pdata->negative = (rdev->family != CHIP_RV200 &&
420 				   rdev->family != CHIP_RV250 &&
421 				   rdev->family != CHIP_RV280 &&
422 				   rdev->family != CHIP_RV350);
423 
424 #ifdef CONFIG_PMAC_BACKLIGHT
425 		pdata->negative = (pdata->negative ||
426 				   of_machine_is_compatible("PowerBook4,3") ||
427 				   of_machine_is_compatible("PowerBook6,3") ||
428 				   of_machine_is_compatible("PowerBook6,5"));
429 #endif
430 	}
431 
432 	if (rdev->is_atom_bios) {
433 		struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
434 		lvds->bl_dev = bd;
435 	} else {
436 		struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
437 		lvds->bl_dev = bd;
438 	}
439 
440 	bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
441 	bd->props.power = FB_BLANK_UNBLANK;
442 	backlight_update_status(bd);
443 
444 	DRM_INFO("radeon legacy LVDS backlight initialized\n");
445 	rdev->mode_info.bl_encoder = radeon_encoder;
446 
447 	return;
448 
449 error:
450 	kfree(pdata);
451 	return;
452 }
453 
454 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
455 {
456 	struct drm_device *dev = radeon_encoder->base.dev;
457 	struct radeon_device *rdev = dev->dev_private;
458 	struct backlight_device *bd = NULL;
459 
460 	if (!radeon_encoder->enc_priv)
461 		return;
462 
463 	if (rdev->is_atom_bios) {
464 		struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
465 		bd = lvds->bl_dev;
466 		lvds->bl_dev = NULL;
467 	} else {
468 		struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
469 		bd = lvds->bl_dev;
470 		lvds->bl_dev = NULL;
471 	}
472 
473 	if (bd) {
474 		struct radeon_backlight_privdata *pdata;
475 
476 		pdata = bl_get_data(bd);
477 		backlight_device_unregister(bd);
478 		kfree(pdata);
479 
480 		DRM_INFO("radeon legacy LVDS backlight unloaded\n");
481 	}
482 }
483 
484 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
485 
486 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
487 {
488 }
489 
490 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
491 {
492 }
493 
494 #endif
495 
496 
497 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
498 {
499 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
500 
501 	if (radeon_encoder->enc_priv) {
502 		radeon_legacy_backlight_exit(radeon_encoder);
503 		kfree(radeon_encoder->enc_priv);
504 	}
505 	drm_encoder_cleanup(encoder);
506 	kfree(radeon_encoder);
507 }
508 
509 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
510 	.destroy = radeon_lvds_enc_destroy,
511 };
512 
513 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
514 {
515 	struct drm_device *dev = encoder->dev;
516 	struct radeon_device *rdev = dev->dev_private;
517 	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
518 	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
519 	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
520 
521 	DRM_DEBUG_KMS("\n");
522 
523 	switch (mode) {
524 	case DRM_MODE_DPMS_ON:
525 		crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
526 		dac_cntl &= ~RADEON_DAC_PDWN;
527 		dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
528 				    RADEON_DAC_PDWN_G |
529 				    RADEON_DAC_PDWN_B);
530 		break;
531 	case DRM_MODE_DPMS_STANDBY:
532 	case DRM_MODE_DPMS_SUSPEND:
533 	case DRM_MODE_DPMS_OFF:
534 		crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
535 		dac_cntl |= RADEON_DAC_PDWN;
536 		dac_macro_cntl |= (RADEON_DAC_PDWN_R |
537 				   RADEON_DAC_PDWN_G |
538 				   RADEON_DAC_PDWN_B);
539 		break;
540 	}
541 
542 	/* handled in radeon_crtc_dpms() */
543 	if (!(rdev->flags & RADEON_SINGLE_CRTC))
544 		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
545 	WREG32(RADEON_DAC_CNTL, dac_cntl);
546 	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
547 
548 	if (rdev->is_atom_bios)
549 		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
550 	else
551 		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
552 
553 }
554 
555 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
556 {
557 	struct radeon_device *rdev = encoder->dev->dev_private;
558 
559 	if (rdev->is_atom_bios)
560 		radeon_atom_output_lock(encoder, true);
561 	else
562 		radeon_combios_output_lock(encoder, true);
563 	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
564 }
565 
566 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
567 {
568 	struct radeon_device *rdev = encoder->dev->dev_private;
569 
570 	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
571 
572 	if (rdev->is_atom_bios)
573 		radeon_atom_output_lock(encoder, false);
574 	else
575 		radeon_combios_output_lock(encoder, false);
576 }
577 
578 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
579 					       struct drm_display_mode *mode,
580 					       struct drm_display_mode *adjusted_mode)
581 {
582 	struct drm_device *dev = encoder->dev;
583 	struct radeon_device *rdev = dev->dev_private;
584 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
585 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
586 	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
587 
588 	DRM_DEBUG_KMS("\n");
589 
590 	if (radeon_crtc->crtc_id == 0) {
591 		if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
592 			disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
593 				~(RADEON_DISP_DAC_SOURCE_MASK);
594 			WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
595 		} else {
596 			dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
597 			WREG32(RADEON_DAC_CNTL2, dac2_cntl);
598 		}
599 	} else {
600 		if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
601 			disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
602 				~(RADEON_DISP_DAC_SOURCE_MASK);
603 			disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
604 			WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
605 		} else {
606 			dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
607 			WREG32(RADEON_DAC_CNTL2, dac2_cntl);
608 		}
609 	}
610 
611 	dac_cntl = (RADEON_DAC_MASK_ALL |
612 		    RADEON_DAC_VGA_ADR_EN |
613 		    /* TODO 6-bits */
614 		    RADEON_DAC_8BIT_EN);
615 
616 	WREG32_P(RADEON_DAC_CNTL,
617 		       dac_cntl,
618 		       RADEON_DAC_RANGE_CNTL |
619 		       RADEON_DAC_BLANKING);
620 
621 	if (radeon_encoder->enc_priv) {
622 		struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
623 		dac_macro_cntl = p_dac->ps2_pdac_adj;
624 	} else
625 		dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
626 	dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
627 	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
628 
629 	if (rdev->is_atom_bios)
630 		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
631 	else
632 		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
633 }
634 
635 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
636 								  struct drm_connector *connector)
637 {
638 	struct drm_device *dev = encoder->dev;
639 	struct radeon_device *rdev = dev->dev_private;
640 	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
641 	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
642 	enum drm_connector_status found = connector_status_disconnected;
643 	bool color = true;
644 
645 	/* just don't bother on RN50 those chip are often connected to remoting
646 	 * console hw and often we get failure to load detect those. So to make
647 	 * everyone happy report the encoder as always connected.
648 	 */
649 	if (ASIC_IS_RN50(rdev)) {
650 		return connector_status_connected;
651 	}
652 
653 	/* save the regs we need */
654 	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
655 	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
656 	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
657 	dac_cntl = RREG32(RADEON_DAC_CNTL);
658 	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
659 
660 	tmp = vclk_ecp_cntl &
661 		~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
662 	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
663 
664 	tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
665 	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
666 
667 	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
668 		RADEON_DAC_FORCE_DATA_EN;
669 
670 	if (color)
671 		tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
672 	else
673 		tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
674 
675 	if (ASIC_IS_R300(rdev))
676 		tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
677 	else if (ASIC_IS_RV100(rdev))
678 		tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
679 	else
680 		tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
681 
682 	WREG32(RADEON_DAC_EXT_CNTL, tmp);
683 
684 	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
685 	tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
686 	WREG32(RADEON_DAC_CNTL, tmp);
687 
688 	tmp = dac_macro_cntl;
689 	tmp &= ~(RADEON_DAC_PDWN_R |
690 		 RADEON_DAC_PDWN_G |
691 		 RADEON_DAC_PDWN_B);
692 
693 	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
694 
695 	mdelay(2);
696 
697 	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
698 		found = connector_status_connected;
699 
700 	/* restore the regs we used */
701 	WREG32(RADEON_DAC_CNTL, dac_cntl);
702 	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
703 	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
704 	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
705 	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
706 
707 	return found;
708 }
709 
710 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
711 	.dpms = radeon_legacy_primary_dac_dpms,
712 	.mode_fixup = radeon_legacy_mode_fixup,
713 	.prepare = radeon_legacy_primary_dac_prepare,
714 	.mode_set = radeon_legacy_primary_dac_mode_set,
715 	.commit = radeon_legacy_primary_dac_commit,
716 	.detect = radeon_legacy_primary_dac_detect,
717 	.disable = radeon_legacy_encoder_disable,
718 };
719 
720 
721 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
722 	.destroy = radeon_enc_destroy,
723 };
724 
725 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
726 {
727 	struct drm_device *dev = encoder->dev;
728 	struct radeon_device *rdev = dev->dev_private;
729 	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
730 	DRM_DEBUG_KMS("\n");
731 
732 	switch (mode) {
733 	case DRM_MODE_DPMS_ON:
734 		fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
735 		break;
736 	case DRM_MODE_DPMS_STANDBY:
737 	case DRM_MODE_DPMS_SUSPEND:
738 	case DRM_MODE_DPMS_OFF:
739 		fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
740 		break;
741 	}
742 
743 	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
744 
745 	if (rdev->is_atom_bios)
746 		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
747 	else
748 		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
749 
750 }
751 
752 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
753 {
754 	struct radeon_device *rdev = encoder->dev->dev_private;
755 
756 	if (rdev->is_atom_bios)
757 		radeon_atom_output_lock(encoder, true);
758 	else
759 		radeon_combios_output_lock(encoder, true);
760 	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
761 }
762 
763 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
764 {
765 	struct radeon_device *rdev = encoder->dev->dev_private;
766 
767 	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
768 
769 	if (rdev->is_atom_bios)
770 		radeon_atom_output_lock(encoder, true);
771 	else
772 		radeon_combios_output_lock(encoder, true);
773 }
774 
775 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
776 					    struct drm_display_mode *mode,
777 					    struct drm_display_mode *adjusted_mode)
778 {
779 	struct drm_device *dev = encoder->dev;
780 	struct radeon_device *rdev = dev->dev_private;
781 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
782 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
783 	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
784 	int i;
785 
786 	DRM_DEBUG_KMS("\n");
787 
788 	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
789 	tmp &= 0xfffff;
790 	if (rdev->family == CHIP_RV280) {
791 		/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
792 		tmp ^= (1 << 22);
793 		tmds_pll_cntl ^= (1 << 22);
794 	}
795 
796 	if (radeon_encoder->enc_priv) {
797 		struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
798 
799 		for (i = 0; i < 4; i++) {
800 			if (tmds->tmds_pll[i].freq == 0)
801 				break;
802 			if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
803 				tmp = tmds->tmds_pll[i].value ;
804 				break;
805 			}
806 		}
807 	}
808 
809 	if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
810 		if (tmp & 0xfff00000)
811 			tmds_pll_cntl = tmp;
812 		else {
813 			tmds_pll_cntl &= 0xfff00000;
814 			tmds_pll_cntl |= tmp;
815 		}
816 	} else
817 		tmds_pll_cntl = tmp;
818 
819 	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
820 		~(RADEON_TMDS_TRANSMITTER_PLLRST);
821 
822 	if (rdev->family == CHIP_R200 ||
823 	    rdev->family == CHIP_R100 ||
824 	    ASIC_IS_R300(rdev))
825 		tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
826 	else /* RV chips got this bit reversed */
827 		tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
828 
829 	fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
830 		      (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
831 		       RADEON_FP_CRTC_DONT_SHADOW_HEND));
832 
833 	fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
834 
835 	fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
836 			 RADEON_FP_DFP_SYNC_SEL |
837 			 RADEON_FP_CRT_SYNC_SEL |
838 			 RADEON_FP_CRTC_LOCK_8DOT |
839 			 RADEON_FP_USE_SHADOW_EN |
840 			 RADEON_FP_CRTC_USE_SHADOW_VEND |
841 			 RADEON_FP_CRT_SYNC_ALT);
842 
843 	if (1) /*  FIXME rgbBits == 8 */
844 		fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
845 	else
846 		fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
847 
848 	if (radeon_crtc->crtc_id == 0) {
849 		if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
850 			fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
851 			if (radeon_encoder->rmx_type != RMX_OFF)
852 				fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
853 			else
854 				fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
855 		} else
856 			fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
857 	} else {
858 		if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
859 			fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
860 			fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
861 		} else
862 			fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
863 	}
864 
865 	WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
866 	WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
867 	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
868 
869 	if (rdev->is_atom_bios)
870 		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
871 	else
872 		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
873 }
874 
875 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
876 	.dpms = radeon_legacy_tmds_int_dpms,
877 	.mode_fixup = radeon_legacy_mode_fixup,
878 	.prepare = radeon_legacy_tmds_int_prepare,
879 	.mode_set = radeon_legacy_tmds_int_mode_set,
880 	.commit = radeon_legacy_tmds_int_commit,
881 	.disable = radeon_legacy_encoder_disable,
882 };
883 
884 
885 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
886 	.destroy = radeon_enc_destroy,
887 };
888 
889 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
890 {
891 	struct drm_device *dev = encoder->dev;
892 	struct radeon_device *rdev = dev->dev_private;
893 	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
894 	DRM_DEBUG_KMS("\n");
895 
896 	switch (mode) {
897 	case DRM_MODE_DPMS_ON:
898 		fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
899 		fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
900 		break;
901 	case DRM_MODE_DPMS_STANDBY:
902 	case DRM_MODE_DPMS_SUSPEND:
903 	case DRM_MODE_DPMS_OFF:
904 		fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
905 		fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
906 		break;
907 	}
908 
909 	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
910 
911 	if (rdev->is_atom_bios)
912 		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
913 	else
914 		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
915 
916 }
917 
918 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
919 {
920 	struct radeon_device *rdev = encoder->dev->dev_private;
921 
922 	if (rdev->is_atom_bios)
923 		radeon_atom_output_lock(encoder, true);
924 	else
925 		radeon_combios_output_lock(encoder, true);
926 	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
927 }
928 
929 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
930 {
931 	struct radeon_device *rdev = encoder->dev->dev_private;
932 	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
933 
934 	if (rdev->is_atom_bios)
935 		radeon_atom_output_lock(encoder, false);
936 	else
937 		radeon_combios_output_lock(encoder, false);
938 }
939 
940 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
941 					    struct drm_display_mode *mode,
942 					    struct drm_display_mode *adjusted_mode)
943 {
944 	struct drm_device *dev = encoder->dev;
945 	struct radeon_device *rdev = dev->dev_private;
946 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
947 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
948 	uint32_t fp2_gen_cntl;
949 
950 	DRM_DEBUG_KMS("\n");
951 
952 	if (rdev->is_atom_bios) {
953 		radeon_encoder->pixel_clock = adjusted_mode->clock;
954 		atombios_dvo_setup(encoder, ATOM_ENABLE);
955 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
956 	} else {
957 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
958 
959 		if (1) /*  FIXME rgbBits == 8 */
960 			fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
961 		else
962 			fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
963 
964 		fp2_gen_cntl &= ~(RADEON_FP2_ON |
965 				  RADEON_FP2_DVO_EN |
966 				  RADEON_FP2_DVO_RATE_SEL_SDR);
967 
968 		/* XXX: these are oem specific */
969 		if (ASIC_IS_R300(rdev)) {
970 			if ((dev->pdev->device == 0x4850) &&
971 			    (dev->pdev->subsystem_vendor == 0x1028) &&
972 			    (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
973 				fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
974 			else
975 				fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
976 
977 			/*if (mode->clock > 165000)
978 			  fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
979 		}
980 		if (!radeon_combios_external_tmds_setup(encoder))
981 			radeon_external_tmds_setup(encoder);
982 	}
983 
984 	if (radeon_crtc->crtc_id == 0) {
985 		if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
986 			fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
987 			if (radeon_encoder->rmx_type != RMX_OFF)
988 				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
989 			else
990 				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
991 		} else
992 			fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
993 	} else {
994 		if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
995 			fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
996 			fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
997 		} else
998 			fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
999 	}
1000 
1001 	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1002 
1003 	if (rdev->is_atom_bios)
1004 		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1005 	else
1006 		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1007 }
1008 
1009 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1010 {
1011 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1012 	/* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1013 	kfree(radeon_encoder->enc_priv);
1014 	drm_encoder_cleanup(encoder);
1015 	kfree(radeon_encoder);
1016 }
1017 
1018 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1019 	.dpms = radeon_legacy_tmds_ext_dpms,
1020 	.mode_fixup = radeon_legacy_mode_fixup,
1021 	.prepare = radeon_legacy_tmds_ext_prepare,
1022 	.mode_set = radeon_legacy_tmds_ext_mode_set,
1023 	.commit = radeon_legacy_tmds_ext_commit,
1024 	.disable = radeon_legacy_encoder_disable,
1025 };
1026 
1027 
1028 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1029 	.destroy = radeon_ext_tmds_enc_destroy,
1030 };
1031 
1032 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1033 {
1034 	struct drm_device *dev = encoder->dev;
1035 	struct radeon_device *rdev = dev->dev_private;
1036 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1037 	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1038 	uint32_t tv_master_cntl = 0;
1039 	bool is_tv;
1040 	DRM_DEBUG_KMS("\n");
1041 
1042 	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1043 
1044 	if (rdev->family == CHIP_R200)
1045 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1046 	else {
1047 		if (is_tv)
1048 			tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1049 		else
1050 			crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1051 		tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1052 	}
1053 
1054 	switch (mode) {
1055 	case DRM_MODE_DPMS_ON:
1056 		if (rdev->family == CHIP_R200) {
1057 			fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1058 		} else {
1059 			if (is_tv)
1060 				tv_master_cntl |= RADEON_TV_ON;
1061 			else
1062 				crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1063 
1064 			if (rdev->family == CHIP_R420 ||
1065 			    rdev->family == CHIP_R423 ||
1066 			    rdev->family == CHIP_RV410)
1067 				tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1068 						 R420_TV_DAC_GDACPD |
1069 						 R420_TV_DAC_BDACPD |
1070 						 RADEON_TV_DAC_BGSLEEP);
1071 			else
1072 				tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1073 						 RADEON_TV_DAC_GDACPD |
1074 						 RADEON_TV_DAC_BDACPD |
1075 						 RADEON_TV_DAC_BGSLEEP);
1076 		}
1077 		break;
1078 	case DRM_MODE_DPMS_STANDBY:
1079 	case DRM_MODE_DPMS_SUSPEND:
1080 	case DRM_MODE_DPMS_OFF:
1081 		if (rdev->family == CHIP_R200)
1082 			fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1083 		else {
1084 			if (is_tv)
1085 				tv_master_cntl &= ~RADEON_TV_ON;
1086 			else
1087 				crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1088 
1089 			if (rdev->family == CHIP_R420 ||
1090 			    rdev->family == CHIP_R423 ||
1091 			    rdev->family == CHIP_RV410)
1092 				tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1093 						R420_TV_DAC_GDACPD |
1094 						R420_TV_DAC_BDACPD |
1095 						RADEON_TV_DAC_BGSLEEP);
1096 			else
1097 				tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1098 						RADEON_TV_DAC_GDACPD |
1099 						RADEON_TV_DAC_BDACPD |
1100 						RADEON_TV_DAC_BGSLEEP);
1101 		}
1102 		break;
1103 	}
1104 
1105 	if (rdev->family == CHIP_R200) {
1106 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1107 	} else {
1108 		if (is_tv)
1109 			WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1110 		/* handled in radeon_crtc_dpms() */
1111 		else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1112 			WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1113 		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1114 	}
1115 
1116 	if (rdev->is_atom_bios)
1117 		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1118 	else
1119 		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1120 
1121 }
1122 
1123 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1124 {
1125 	struct radeon_device *rdev = encoder->dev->dev_private;
1126 
1127 	if (rdev->is_atom_bios)
1128 		radeon_atom_output_lock(encoder, true);
1129 	else
1130 		radeon_combios_output_lock(encoder, true);
1131 	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1132 }
1133 
1134 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1135 {
1136 	struct radeon_device *rdev = encoder->dev->dev_private;
1137 
1138 	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1139 
1140 	if (rdev->is_atom_bios)
1141 		radeon_atom_output_lock(encoder, true);
1142 	else
1143 		radeon_combios_output_lock(encoder, true);
1144 }
1145 
1146 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1147 		struct drm_display_mode *mode,
1148 		struct drm_display_mode *adjusted_mode)
1149 {
1150 	struct drm_device *dev = encoder->dev;
1151 	struct radeon_device *rdev = dev->dev_private;
1152 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1153 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1154 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1155 	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1156 	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1157 	bool is_tv = false;
1158 
1159 	DRM_DEBUG_KMS("\n");
1160 
1161 	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1162 
1163 	if (rdev->family != CHIP_R200) {
1164 		tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1165 		if (rdev->family == CHIP_R420 ||
1166 		    rdev->family == CHIP_R423 ||
1167 		    rdev->family == CHIP_RV410) {
1168 			tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1169 					 RADEON_TV_DAC_BGADJ_MASK |
1170 					 R420_TV_DAC_DACADJ_MASK |
1171 					 R420_TV_DAC_RDACPD |
1172 					 R420_TV_DAC_GDACPD |
1173 					 R420_TV_DAC_BDACPD |
1174 					 R420_TV_DAC_TVENABLE);
1175 		} else {
1176 			tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1177 					 RADEON_TV_DAC_BGADJ_MASK |
1178 					 RADEON_TV_DAC_DACADJ_MASK |
1179 					 RADEON_TV_DAC_RDACPD |
1180 					 RADEON_TV_DAC_GDACPD |
1181 					 RADEON_TV_DAC_BDACPD);
1182 		}
1183 
1184 		tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1185 
1186 		if (is_tv) {
1187 			if (tv_dac->tv_std == TV_STD_NTSC ||
1188 			    tv_dac->tv_std == TV_STD_NTSC_J ||
1189 			    tv_dac->tv_std == TV_STD_PAL_M ||
1190 			    tv_dac->tv_std == TV_STD_PAL_60)
1191 				tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1192 			else
1193 				tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1194 
1195 			if (tv_dac->tv_std == TV_STD_NTSC ||
1196 			    tv_dac->tv_std == TV_STD_NTSC_J)
1197 				tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1198 			else
1199 				tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1200 		} else
1201 			tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1202 					tv_dac->ps2_tvdac_adj);
1203 
1204 		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1205 	}
1206 
1207 	if (ASIC_IS_R300(rdev)) {
1208 		gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1209 		disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1210 	} else if (rdev->family != CHIP_R200)
1211 		disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1212 	else if (rdev->family == CHIP_R200)
1213 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1214 
1215 	if (rdev->family >= CHIP_R200)
1216 		disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1217 
1218 	if (is_tv) {
1219 		uint32_t dac_cntl;
1220 
1221 		dac_cntl = RREG32(RADEON_DAC_CNTL);
1222 		dac_cntl &= ~RADEON_DAC_TVO_EN;
1223 		WREG32(RADEON_DAC_CNTL, dac_cntl);
1224 
1225 		if (ASIC_IS_R300(rdev))
1226 			gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1227 
1228 		dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1229 		if (radeon_crtc->crtc_id == 0) {
1230 			if (ASIC_IS_R300(rdev)) {
1231 				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1232 				disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1233 						     RADEON_DISP_TV_SOURCE_CRTC);
1234 			}
1235 			if (rdev->family >= CHIP_R200) {
1236 				disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1237 			} else {
1238 				disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1239 			}
1240 		} else {
1241 			if (ASIC_IS_R300(rdev)) {
1242 				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1243 				disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1244 			}
1245 			if (rdev->family >= CHIP_R200) {
1246 				disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1247 			} else {
1248 				disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1249 			}
1250 		}
1251 		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1252 	} else {
1253 
1254 		dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1255 
1256 		if (radeon_crtc->crtc_id == 0) {
1257 			if (ASIC_IS_R300(rdev)) {
1258 				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1259 				disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1260 			} else if (rdev->family == CHIP_R200) {
1261 				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1262 						  RADEON_FP2_DVO_RATE_SEL_SDR);
1263 			} else
1264 				disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1265 		} else {
1266 			if (ASIC_IS_R300(rdev)) {
1267 				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1268 				disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1269 			} else if (rdev->family == CHIP_R200) {
1270 				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1271 						  RADEON_FP2_DVO_RATE_SEL_SDR);
1272 				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1273 			} else
1274 				disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1275 		}
1276 		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1277 	}
1278 
1279 	if (ASIC_IS_R300(rdev)) {
1280 		WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1281 		WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1282 	} else if (rdev->family != CHIP_R200)
1283 		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1284 	else if (rdev->family == CHIP_R200)
1285 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1286 
1287 	if (rdev->family >= CHIP_R200)
1288 		WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1289 
1290 	if (is_tv)
1291 		radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1292 
1293 	if (rdev->is_atom_bios)
1294 		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1295 	else
1296 		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1297 
1298 }
1299 
1300 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1301 				  struct drm_connector *connector)
1302 {
1303 	struct drm_device *dev = encoder->dev;
1304 	struct radeon_device *rdev = dev->dev_private;
1305 	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1306 	uint32_t disp_output_cntl, gpiopad_a, tmp;
1307 	bool found = false;
1308 
1309 	/* save regs needed */
1310 	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1311 	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1312 	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1313 	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1314 	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1315 	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1316 
1317 	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1318 
1319 	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1320 
1321 	WREG32(RADEON_CRTC2_GEN_CNTL,
1322 	       RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1323 
1324 	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1325 	tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1326 	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1327 
1328 	WREG32(RADEON_DAC_EXT_CNTL,
1329 	       RADEON_DAC2_FORCE_BLANK_OFF_EN |
1330 	       RADEON_DAC2_FORCE_DATA_EN |
1331 	       RADEON_DAC_FORCE_DATA_SEL_RGB |
1332 	       (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1333 
1334 	WREG32(RADEON_TV_DAC_CNTL,
1335 	       RADEON_TV_DAC_STD_NTSC |
1336 	       (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1337 	       (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1338 
1339 	RREG32(RADEON_TV_DAC_CNTL);
1340 	mdelay(4);
1341 
1342 	WREG32(RADEON_TV_DAC_CNTL,
1343 	       RADEON_TV_DAC_NBLANK |
1344 	       RADEON_TV_DAC_NHOLD |
1345 	       RADEON_TV_MONITOR_DETECT_EN |
1346 	       RADEON_TV_DAC_STD_NTSC |
1347 	       (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1348 	       (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1349 
1350 	RREG32(RADEON_TV_DAC_CNTL);
1351 	mdelay(6);
1352 
1353 	tmp = RREG32(RADEON_TV_DAC_CNTL);
1354 	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1355 		found = true;
1356 		DRM_DEBUG_KMS("S-video TV connection detected\n");
1357 	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1358 		found = true;
1359 		DRM_DEBUG_KMS("Composite TV connection detected\n");
1360 	}
1361 
1362 	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1363 	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1364 	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1365 	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1366 	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1367 	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1368 	return found;
1369 }
1370 
1371 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1372 				    struct drm_connector *connector)
1373 {
1374 	struct drm_device *dev = encoder->dev;
1375 	struct radeon_device *rdev = dev->dev_private;
1376 	uint32_t tv_dac_cntl, dac_cntl2;
1377 	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1378 	bool found = false;
1379 
1380 	if (ASIC_IS_R300(rdev))
1381 		return r300_legacy_tv_detect(encoder, connector);
1382 
1383 	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1384 	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1385 	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1386 	config_cntl = RREG32(RADEON_CONFIG_CNTL);
1387 	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1388 
1389 	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1390 	WREG32(RADEON_DAC_CNTL2, tmp);
1391 
1392 	tmp = tv_master_cntl | RADEON_TV_ON;
1393 	tmp &= ~(RADEON_TV_ASYNC_RST |
1394 		 RADEON_RESTART_PHASE_FIX |
1395 		 RADEON_CRT_FIFO_CE_EN |
1396 		 RADEON_TV_FIFO_CE_EN |
1397 		 RADEON_RE_SYNC_NOW_SEL_MASK);
1398 	tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1399 	WREG32(RADEON_TV_MASTER_CNTL, tmp);
1400 
1401 	tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1402 		RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1403 		(8 << RADEON_TV_DAC_BGADJ_SHIFT);
1404 
1405 	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1406 		tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1407 	else
1408 		tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1409 	WREG32(RADEON_TV_DAC_CNTL, tmp);
1410 
1411 	tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1412 		RADEON_RED_MX_FORCE_DAC_DATA |
1413 		RADEON_GRN_MX_FORCE_DAC_DATA |
1414 		RADEON_BLU_MX_FORCE_DAC_DATA |
1415 		(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1416 	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1417 
1418 	mdelay(3);
1419 	tmp = RREG32(RADEON_TV_DAC_CNTL);
1420 	if (tmp & RADEON_TV_DAC_GDACDET) {
1421 		found = true;
1422 		DRM_DEBUG_KMS("S-video TV connection detected\n");
1423 	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1424 		found = true;
1425 		DRM_DEBUG_KMS("Composite TV connection detected\n");
1426 	}
1427 
1428 	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1429 	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1430 	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1431 	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1432 	return found;
1433 }
1434 
1435 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1436 					 struct drm_connector *connector)
1437 {
1438 	struct drm_device *dev = encoder->dev;
1439 	struct radeon_device *rdev = dev->dev_private;
1440 	uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1441 	uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1442 	uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1443 	uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1444 	uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1445 	bool found = false;
1446 	int i;
1447 
1448 	/* save the regs we need */
1449 	gpio_monid = RREG32(RADEON_GPIO_MONID);
1450 	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1451 	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1452 	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1453 	disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1454 	disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1455 	disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1456 	disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1457 	disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1458 	disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1459 	crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1460 	crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1461 	crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1462 	crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1463 
1464 	tmp = RREG32(RADEON_GPIO_MONID);
1465 	tmp &= ~RADEON_GPIO_A_0;
1466 	WREG32(RADEON_GPIO_MONID, tmp);
1467 
1468 	WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1469 				     RADEON_FP2_PANEL_FORMAT |
1470 				     R200_FP2_SOURCE_SEL_TRANS_UNIT |
1471 				     RADEON_FP2_DVO_EN |
1472 				     R200_FP2_DVO_RATE_SEL_SDR));
1473 
1474 	WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1475 					 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1476 
1477 	WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1478 				       RADEON_CRTC2_DISP_REQ_EN_B));
1479 
1480 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1481 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1482 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1483 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1484 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1485 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1486 
1487 	WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1488 	WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1489 	WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1490 	WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1491 
1492 	for (i = 0; i < 200; i++) {
1493 		tmp = RREG32(RADEON_GPIO_MONID);
1494 		if (tmp & RADEON_GPIO_Y_0)
1495 			found = true;
1496 
1497 		if (found)
1498 			break;
1499 
1500 		if (!drm_can_sleep())
1501 			mdelay(1);
1502 		else
1503 			msleep(1);
1504 	}
1505 
1506 	/* restore the regs we used */
1507 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1508 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1509 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1510 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1511 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1512 	WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1513 	WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1514 	WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1515 	WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1516 	WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1517 	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1518 	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1519 	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1520 	WREG32(RADEON_GPIO_MONID, gpio_monid);
1521 
1522 	return found;
1523 }
1524 
1525 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1526 							     struct drm_connector *connector)
1527 {
1528 	struct drm_device *dev = encoder->dev;
1529 	struct radeon_device *rdev = dev->dev_private;
1530 	uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1531 	uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1532 	uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1533 	enum drm_connector_status found = connector_status_disconnected;
1534 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1535 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1536 	bool color = true;
1537 	struct drm_crtc *crtc;
1538 
1539 	/* find out if crtc2 is in use or if this encoder is using it */
1540 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1541 		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1542 		if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1543 			if (encoder->crtc != crtc) {
1544 				return connector_status_disconnected;
1545 			}
1546 		}
1547 	}
1548 
1549 	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1550 	    connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1551 	    connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1552 		bool tv_detect;
1553 
1554 		if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1555 			return connector_status_disconnected;
1556 
1557 		tv_detect = radeon_legacy_tv_detect(encoder, connector);
1558 		if (tv_detect && tv_dac)
1559 			found = connector_status_connected;
1560 		return found;
1561 	}
1562 
1563 	/* don't probe if the encoder is being used for something else not CRT related */
1564 	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1565 		DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1566 		return connector_status_disconnected;
1567 	}
1568 
1569 	/* R200 uses an external DAC for secondary DAC */
1570 	if (rdev->family == CHIP_R200) {
1571 		if (radeon_legacy_ext_dac_detect(encoder, connector))
1572 			found = connector_status_connected;
1573 		return found;
1574 	}
1575 
1576 	/* save the regs we need */
1577 	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1578 
1579 	if (rdev->flags & RADEON_SINGLE_CRTC) {
1580 		crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1581 	} else {
1582 		if (ASIC_IS_R300(rdev)) {
1583 			gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1584 			disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1585 		} else {
1586 			disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1587 		}
1588 		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1589 	}
1590 	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1591 	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1592 	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1593 
1594 	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1595 			       | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1596 	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1597 
1598 	if (rdev->flags & RADEON_SINGLE_CRTC) {
1599 		tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1600 		WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1601 	} else {
1602 		tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1603 		tmp |= RADEON_CRTC2_CRT2_ON |
1604 			(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1605 		WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1606 
1607 		if (ASIC_IS_R300(rdev)) {
1608 			WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1609 			tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1610 			tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1611 			WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1612 		} else {
1613 			tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1614 			WREG32(RADEON_DISP_HW_DEBUG, tmp);
1615 		}
1616 	}
1617 
1618 	tmp = RADEON_TV_DAC_NBLANK |
1619 		RADEON_TV_DAC_NHOLD |
1620 		RADEON_TV_MONITOR_DETECT_EN |
1621 		RADEON_TV_DAC_STD_PS2;
1622 
1623 	WREG32(RADEON_TV_DAC_CNTL, tmp);
1624 
1625 	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1626 		RADEON_DAC2_FORCE_DATA_EN;
1627 
1628 	if (color)
1629 		tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1630 	else
1631 		tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1632 
1633 	if (ASIC_IS_R300(rdev))
1634 		tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1635 	else
1636 		tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1637 
1638 	WREG32(RADEON_DAC_EXT_CNTL, tmp);
1639 
1640 	tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1641 	WREG32(RADEON_DAC_CNTL2, tmp);
1642 
1643 	mdelay(10);
1644 
1645 	if (ASIC_IS_R300(rdev)) {
1646 		if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1647 			found = connector_status_connected;
1648 	} else {
1649 		if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1650 			found = connector_status_connected;
1651 	}
1652 
1653 	/* restore regs we used */
1654 	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1655 	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1656 	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1657 
1658 	if (rdev->flags & RADEON_SINGLE_CRTC) {
1659 		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1660 	} else {
1661 		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1662 		if (ASIC_IS_R300(rdev)) {
1663 			WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1664 			WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1665 		} else {
1666 			WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1667 		}
1668 	}
1669 
1670 	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1671 
1672 	return found;
1673 
1674 }
1675 
1676 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1677 	.dpms = radeon_legacy_tv_dac_dpms,
1678 	.mode_fixup = radeon_legacy_mode_fixup,
1679 	.prepare = radeon_legacy_tv_dac_prepare,
1680 	.mode_set = radeon_legacy_tv_dac_mode_set,
1681 	.commit = radeon_legacy_tv_dac_commit,
1682 	.detect = radeon_legacy_tv_dac_detect,
1683 	.disable = radeon_legacy_encoder_disable,
1684 };
1685 
1686 
1687 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1688 	.destroy = radeon_enc_destroy,
1689 };
1690 
1691 
1692 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1693 {
1694 	struct drm_device *dev = encoder->base.dev;
1695 	struct radeon_device *rdev = dev->dev_private;
1696 	struct radeon_encoder_int_tmds *tmds = NULL;
1697 	bool ret;
1698 
1699 	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1700 
1701 	if (!tmds)
1702 		return NULL;
1703 
1704 	if (rdev->is_atom_bios)
1705 		ret = radeon_atombios_get_tmds_info(encoder, tmds);
1706 	else
1707 		ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1708 
1709 	if (ret == false)
1710 		radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1711 
1712 	return tmds;
1713 }
1714 
1715 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1716 {
1717 	struct drm_device *dev = encoder->base.dev;
1718 	struct radeon_device *rdev = dev->dev_private;
1719 	struct radeon_encoder_ext_tmds *tmds = NULL;
1720 	bool ret;
1721 
1722 	if (rdev->is_atom_bios)
1723 		return NULL;
1724 
1725 	tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1726 
1727 	if (!tmds)
1728 		return NULL;
1729 
1730 	ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1731 
1732 	if (ret == false)
1733 		radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1734 
1735 	return tmds;
1736 }
1737 
1738 void
1739 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1740 {
1741 	struct radeon_device *rdev = dev->dev_private;
1742 	struct drm_encoder *encoder;
1743 	struct radeon_encoder *radeon_encoder;
1744 
1745 	/* see if we already added it */
1746 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1747 		radeon_encoder = to_radeon_encoder(encoder);
1748 		if (radeon_encoder->encoder_enum == encoder_enum) {
1749 			radeon_encoder->devices |= supported_device;
1750 			return;
1751 		}
1752 
1753 	}
1754 
1755 	/* add a new one */
1756 	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1757 	if (!radeon_encoder)
1758 		return;
1759 
1760 	encoder = &radeon_encoder->base;
1761 	if (rdev->flags & RADEON_SINGLE_CRTC)
1762 		encoder->possible_crtcs = 0x1;
1763 	else
1764 		encoder->possible_crtcs = 0x3;
1765 
1766 	radeon_encoder->enc_priv = NULL;
1767 
1768 	radeon_encoder->encoder_enum = encoder_enum;
1769 	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1770 	radeon_encoder->devices = supported_device;
1771 	radeon_encoder->rmx_type = RMX_OFF;
1772 
1773 	switch (radeon_encoder->encoder_id) {
1774 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1775 		encoder->possible_crtcs = 0x1;
1776 		drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
1777 				 DRM_MODE_ENCODER_LVDS, NULL);
1778 		drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1779 		if (rdev->is_atom_bios)
1780 			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1781 		else
1782 			radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1783 		radeon_encoder->rmx_type = RMX_FULL;
1784 		break;
1785 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1786 		drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
1787 				 DRM_MODE_ENCODER_TMDS, NULL);
1788 		drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1789 		radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1790 		break;
1791 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1792 		drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
1793 				 DRM_MODE_ENCODER_DAC, NULL);
1794 		drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1795 		if (rdev->is_atom_bios)
1796 			radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1797 		else
1798 			radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1799 		break;
1800 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1801 		drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1802 				 DRM_MODE_ENCODER_TVDAC, NULL);
1803 		drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1804 		if (rdev->is_atom_bios)
1805 			radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1806 		else
1807 			radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1808 		break;
1809 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1810 		drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1811 				 DRM_MODE_ENCODER_TMDS, NULL);
1812 		drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1813 		if (!rdev->is_atom_bios)
1814 			radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1815 		break;
1816 	}
1817 }
1818