1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon_fixed.h" 30 #include "radeon.h" 31 32 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 33 struct drm_display_mode *mode, 34 struct drm_display_mode *adjusted_mode) 35 { 36 struct drm_device *dev = crtc->dev; 37 struct radeon_device *rdev = dev->dev_private; 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 int xres = mode->hdisplay; 40 int yres = mode->vdisplay; 41 bool hscale = true, vscale = true; 42 int hsync_wid; 43 int vsync_wid; 44 int hsync_start; 45 int blank_width; 46 u32 scale, inc, crtc_more_cntl; 47 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 48 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 49 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 50 struct radeon_native_mode *native_mode = &radeon_crtc->native_mode; 51 52 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 53 (RADEON_VERT_STRETCH_RESERVED | 54 RADEON_VERT_AUTO_RATIO_INC); 55 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 56 (RADEON_HORZ_FP_LOOP_STRETCH | 57 RADEON_HORZ_AUTO_RATIO_INC); 58 59 crtc_more_cntl = 0; 60 if ((rdev->family == CHIP_RS100) || 61 (rdev->family == CHIP_RS200)) { 62 /* This is to workaround the asic bug for RMX, some versions 63 of BIOS dosen't have this register initialized correctly. */ 64 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 65 } 66 67 68 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 69 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 70 71 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 72 if (!hsync_wid) 73 hsync_wid = 1; 74 hsync_start = mode->crtc_hsync_start - 8; 75 76 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 77 | ((hsync_wid & 0x3f) << 16) 78 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 79 ? RADEON_CRTC_H_SYNC_POL 80 : 0)); 81 82 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 83 | ((mode->crtc_vdisplay - 1) << 16)); 84 85 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 86 if (!vsync_wid) 87 vsync_wid = 1; 88 89 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 90 | ((vsync_wid & 0x1f) << 16) 91 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 92 ? RADEON_CRTC_V_SYNC_POL 93 : 0)); 94 95 fp_horz_vert_active = 0; 96 97 if (native_mode->panel_xres == 0 || 98 native_mode->panel_yres == 0) { 99 hscale = false; 100 vscale = false; 101 } else { 102 if (xres > native_mode->panel_xres) 103 xres = native_mode->panel_xres; 104 if (yres > native_mode->panel_yres) 105 yres = native_mode->panel_yres; 106 107 if (xres == native_mode->panel_xres) 108 hscale = false; 109 if (yres == native_mode->panel_yres) 110 vscale = false; 111 } 112 113 switch (radeon_crtc->rmx_type) { 114 case RMX_FULL: 115 case RMX_ASPECT: 116 if (!hscale) 117 fp_horz_stretch |= ((xres/8-1) << 16); 118 else { 119 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 120 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 121 / native_mode->panel_xres + 1; 122 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 123 RADEON_HORZ_STRETCH_BLEND | 124 RADEON_HORZ_STRETCH_ENABLE | 125 ((native_mode->panel_xres/8-1) << 16)); 126 } 127 128 if (!vscale) 129 fp_vert_stretch |= ((yres-1) << 12); 130 else { 131 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 132 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 133 / native_mode->panel_yres + 1; 134 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 135 RADEON_VERT_STRETCH_ENABLE | 136 RADEON_VERT_STRETCH_BLEND | 137 ((native_mode->panel_yres-1) << 12)); 138 } 139 break; 140 case RMX_CENTER: 141 fp_horz_stretch |= ((xres/8-1) << 16); 142 fp_vert_stretch |= ((yres-1) << 12); 143 144 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 145 RADEON_CRTC_AUTO_VERT_CENTER_EN); 146 147 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 148 if (blank_width > 110) 149 blank_width = 110; 150 151 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 152 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 153 154 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 155 if (!hsync_wid) 156 hsync_wid = 1; 157 158 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 159 | ((hsync_wid & 0x3f) << 16) 160 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 161 ? RADEON_CRTC_H_SYNC_POL 162 : 0)); 163 164 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 165 | ((mode->crtc_vdisplay - 1) << 16)); 166 167 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 168 if (!vsync_wid) 169 vsync_wid = 1; 170 171 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 172 | ((vsync_wid & 0x1f) << 16) 173 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 174 ? RADEON_CRTC_V_SYNC_POL 175 : 0))); 176 177 fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) | 178 (((native_mode->panel_xres / 8) & 0x1ff) << 16)); 179 break; 180 case RMX_OFF: 181 default: 182 fp_horz_stretch |= ((xres/8-1) << 16); 183 fp_vert_stretch |= ((yres-1) << 12); 184 break; 185 } 186 187 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 188 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 189 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 190 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 191 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 192 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 193 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 194 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 195 } 196 197 void radeon_restore_common_regs(struct drm_device *dev) 198 { 199 /* don't need this yet */ 200 } 201 202 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 203 { 204 struct radeon_device *rdev = dev->dev_private; 205 int i = 0; 206 207 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 208 the cause yet, but this workaround will mask the problem for now. 209 Other chips usually will pass at the very first test, so the 210 workaround shouldn't have any effect on them. */ 211 for (i = 0; 212 (i < 10000 && 213 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 214 i++); 215 } 216 217 static void radeon_pll_write_update(struct drm_device *dev) 218 { 219 struct radeon_device *rdev = dev->dev_private; 220 221 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 222 223 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 224 RADEON_PPLL_ATOMIC_UPDATE_W, 225 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 226 } 227 228 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 229 { 230 struct radeon_device *rdev = dev->dev_private; 231 int i = 0; 232 233 234 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 235 the cause yet, but this workaround will mask the problem for now. 236 Other chips usually will pass at the very first test, so the 237 workaround shouldn't have any effect on them. */ 238 for (i = 0; 239 (i < 10000 && 240 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 241 i++); 242 } 243 244 static void radeon_pll2_write_update(struct drm_device *dev) 245 { 246 struct radeon_device *rdev = dev->dev_private; 247 248 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 249 250 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 251 RADEON_P2PLL_ATOMIC_UPDATE_W, 252 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 253 } 254 255 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 256 uint16_t fb_div) 257 { 258 unsigned int vcoFreq; 259 260 if (!ref_div) 261 return 1; 262 263 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; 264 265 /* 266 * This is horribly crude: the VCO frequency range is divided into 267 * 3 parts, each part having a fixed PLL gain value. 268 */ 269 if (vcoFreq >= 30000) 270 /* 271 * [300..max] MHz : 7 272 */ 273 return 7; 274 else if (vcoFreq >= 18000) 275 /* 276 * [180..300) MHz : 4 277 */ 278 return 4; 279 else 280 /* 281 * [0..180) MHz : 1 282 */ 283 return 1; 284 } 285 286 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 287 { 288 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 289 struct drm_device *dev = crtc->dev; 290 struct radeon_device *rdev = dev->dev_private; 291 uint32_t mask; 292 293 if (radeon_crtc->crtc_id) 294 mask = (RADEON_CRTC2_EN | 295 RADEON_CRTC2_DISP_DIS | 296 RADEON_CRTC2_VSYNC_DIS | 297 RADEON_CRTC2_HSYNC_DIS | 298 RADEON_CRTC2_DISP_REQ_EN_B); 299 else 300 mask = (RADEON_CRTC_DISPLAY_DIS | 301 RADEON_CRTC_VSYNC_DIS | 302 RADEON_CRTC_HSYNC_DIS); 303 304 switch (mode) { 305 case DRM_MODE_DPMS_ON: 306 if (radeon_crtc->crtc_id) 307 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask); 308 else { 309 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 310 RADEON_CRTC_DISP_REQ_EN_B)); 311 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 312 } 313 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 314 radeon_crtc_load_lut(crtc); 315 break; 316 case DRM_MODE_DPMS_STANDBY: 317 case DRM_MODE_DPMS_SUSPEND: 318 case DRM_MODE_DPMS_OFF: 319 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 320 if (radeon_crtc->crtc_id) 321 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); 322 else { 323 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 324 RADEON_CRTC_DISP_REQ_EN_B)); 325 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 326 } 327 break; 328 } 329 } 330 331 /* properly set crtc bpp when using atombios */ 332 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) 333 { 334 struct drm_device *dev = crtc->dev; 335 struct radeon_device *rdev = dev->dev_private; 336 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 337 int format; 338 uint32_t crtc_gen_cntl; 339 uint32_t disp_merge_cntl; 340 uint32_t crtc_pitch; 341 342 switch (crtc->fb->bits_per_pixel) { 343 case 15: /* 555 */ 344 format = 3; 345 break; 346 case 16: /* 565 */ 347 format = 4; 348 break; 349 case 24: /* RGB */ 350 format = 5; 351 break; 352 case 32: /* xRGB */ 353 format = 6; 354 break; 355 default: 356 return; 357 } 358 359 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) + 360 ((crtc->fb->bits_per_pixel * 8) - 1)) / 361 (crtc->fb->bits_per_pixel * 8)); 362 crtc_pitch |= crtc_pitch << 16; 363 364 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 365 366 switch (radeon_crtc->crtc_id) { 367 case 0: 368 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 369 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 370 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 371 372 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; 373 crtc_gen_cntl |= (format << 8); 374 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN; 375 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 376 break; 377 case 1: 378 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 379 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 380 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 381 382 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; 383 crtc_gen_cntl |= (format << 8); 384 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl); 385 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 386 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 387 break; 388 } 389 } 390 391 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 392 struct drm_framebuffer *old_fb) 393 { 394 struct drm_device *dev = crtc->dev; 395 struct radeon_device *rdev = dev->dev_private; 396 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 397 struct radeon_framebuffer *radeon_fb; 398 struct drm_gem_object *obj; 399 uint64_t base; 400 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 401 uint32_t crtc_pitch, pitch_pixels; 402 uint32_t tiling_flags; 403 404 DRM_DEBUG("\n"); 405 406 radeon_fb = to_radeon_framebuffer(crtc->fb); 407 408 obj = radeon_fb->obj; 409 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { 410 return -EINVAL; 411 } 412 /* if scanout was in GTT this really wouldn't work */ 413 /* crtc offset is from display base addr not FB location */ 414 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; 415 416 base -= radeon_crtc->legacy_display_base_addr; 417 418 crtc_offset_cntl = 0; 419 420 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 421 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) + 422 ((crtc->fb->bits_per_pixel * 8) - 1)) / 423 (crtc->fb->bits_per_pixel * 8)); 424 crtc_pitch |= crtc_pitch << 16; 425 426 radeon_object_get_tiling_flags(obj->driver_private, 427 &tiling_flags, NULL); 428 if (tiling_flags & RADEON_TILING_MICRO) 429 DRM_ERROR("trying to scanout microtiled buffer\n"); 430 431 if (tiling_flags & RADEON_TILING_MACRO) { 432 if (ASIC_IS_R300(rdev)) 433 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 434 R300_CRTC_MICRO_TILE_BUFFER_DIS | 435 R300_CRTC_MACRO_TILE_EN); 436 else 437 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 438 } else { 439 if (ASIC_IS_R300(rdev)) 440 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 441 R300_CRTC_MICRO_TILE_BUFFER_DIS | 442 R300_CRTC_MACRO_TILE_EN); 443 else 444 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 445 } 446 447 if (tiling_flags & RADEON_TILING_MACRO) { 448 if (ASIC_IS_R300(rdev)) { 449 crtc_tile_x0_y0 = x | (y << 16); 450 base &= ~0x7ff; 451 } else { 452 int byteshift = crtc->fb->bits_per_pixel >> 4; 453 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 454 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 455 crtc_offset_cntl |= (y % 16); 456 } 457 } else { 458 int offset = y * pitch_pixels + x; 459 switch (crtc->fb->bits_per_pixel) { 460 case 15: 461 case 16: 462 offset *= 2; 463 break; 464 case 24: 465 offset *= 3; 466 break; 467 case 32: 468 offset *= 4; 469 break; 470 default: 471 return false; 472 } 473 base += offset; 474 } 475 476 base &= ~7; 477 478 crtc_offset = (u32)base; 479 480 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 481 482 if (ASIC_IS_R300(rdev)) { 483 if (radeon_crtc->crtc_id) 484 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 485 else 486 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 487 } 488 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 489 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 490 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 491 492 if (old_fb && old_fb != crtc->fb) { 493 radeon_fb = to_radeon_framebuffer(old_fb); 494 radeon_gem_object_unpin(radeon_fb->obj); 495 } 496 return 0; 497 } 498 499 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 500 { 501 struct drm_device *dev = crtc->dev; 502 struct radeon_device *rdev = dev->dev_private; 503 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 504 int format; 505 int hsync_start; 506 int hsync_wid; 507 int vsync_wid; 508 uint32_t crtc_h_total_disp; 509 uint32_t crtc_h_sync_strt_wid; 510 uint32_t crtc_v_total_disp; 511 uint32_t crtc_v_sync_strt_wid; 512 513 DRM_DEBUG("\n"); 514 515 switch (crtc->fb->bits_per_pixel) { 516 case 15: /* 555 */ 517 format = 3; 518 break; 519 case 16: /* 565 */ 520 format = 4; 521 break; 522 case 24: /* RGB */ 523 format = 5; 524 break; 525 case 32: /* xRGB */ 526 format = 6; 527 break; 528 default: 529 return false; 530 } 531 532 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 533 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 534 535 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 536 if (!hsync_wid) 537 hsync_wid = 1; 538 hsync_start = mode->crtc_hsync_start - 8; 539 540 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 541 | ((hsync_wid & 0x3f) << 16) 542 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 543 ? RADEON_CRTC_H_SYNC_POL 544 : 0)); 545 546 /* This works for double scan mode. */ 547 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 548 | ((mode->crtc_vdisplay - 1) << 16)); 549 550 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 551 if (!vsync_wid) 552 vsync_wid = 1; 553 554 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 555 | ((vsync_wid & 0x1f) << 16) 556 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 557 ? RADEON_CRTC_V_SYNC_POL 558 : 0)); 559 560 /* TODO -> Dell Server */ 561 if (0) { 562 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 563 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 564 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2); 565 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 566 567 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 568 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 569 570 /* For CRT on DAC2, don't turn it on if BIOS didn't 571 enable it, even it's detected. 572 */ 573 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 574 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); 575 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); 576 577 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 578 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 579 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 580 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 581 } 582 583 if (radeon_crtc->crtc_id) { 584 uint32_t crtc2_gen_cntl; 585 uint32_t disp2_merge_cntl; 586 587 /* check to see if TV DAC is enabled for another crtc and keep it enabled */ 588 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON) 589 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; 590 else 591 crtc2_gen_cntl = 0; 592 593 crtc2_gen_cntl |= ((format << 8) 594 | RADEON_CRTC2_VSYNC_DIS 595 | RADEON_CRTC2_HSYNC_DIS 596 | RADEON_CRTC2_DISP_DIS 597 | RADEON_CRTC2_DISP_REQ_EN_B 598 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 599 ? RADEON_CRTC2_DBL_SCAN_EN 600 : 0) 601 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 602 ? RADEON_CRTC2_CSYNC_EN 603 : 0) 604 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 605 ? RADEON_CRTC2_INTERLACE_EN 606 : 0)); 607 608 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 609 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 610 611 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 612 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 613 } else { 614 uint32_t crtc_gen_cntl; 615 uint32_t crtc_ext_cntl; 616 uint32_t disp_merge_cntl; 617 618 crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN 619 | (format << 8) 620 | RADEON_CRTC_DISP_REQ_EN_B 621 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 622 ? RADEON_CRTC_DBL_SCAN_EN 623 : 0) 624 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 625 ? RADEON_CRTC_CSYNC_EN 626 : 0) 627 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 628 ? RADEON_CRTC_INTERLACE_EN 629 : 0)); 630 631 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 632 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 633 RADEON_CRTC_VSYNC_DIS | 634 RADEON_CRTC_HSYNC_DIS | 635 RADEON_CRTC_DISPLAY_DIS); 636 637 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 638 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 639 640 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 641 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 642 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 643 } 644 645 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 646 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 647 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 648 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 649 650 return true; 651 } 652 653 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 654 { 655 struct drm_device *dev = crtc->dev; 656 struct radeon_device *rdev = dev->dev_private; 657 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 658 struct drm_encoder *encoder; 659 uint32_t feedback_div = 0; 660 uint32_t frac_fb_div = 0; 661 uint32_t reference_div = 0; 662 uint32_t post_divider = 0; 663 uint32_t freq = 0; 664 uint8_t pll_gain; 665 int pll_flags = RADEON_PLL_LEGACY; 666 bool use_bios_divs = false; 667 /* PLL registers */ 668 uint32_t pll_ref_div = 0; 669 uint32_t pll_fb_post_div = 0; 670 uint32_t htotal_cntl = 0; 671 672 struct radeon_pll *pll; 673 674 struct { 675 int divider; 676 int bitvalue; 677 } *post_div, post_divs[] = { 678 /* From RAGE 128 VR/RAGE 128 GL Register 679 * Reference Manual (Technical Reference 680 * Manual P/N RRG-G04100-C Rev. 0.04), page 681 * 3-17 (PLL_DIV_[3:0]). 682 */ 683 { 1, 0 }, /* VCLK_SRC */ 684 { 2, 1 }, /* VCLK_SRC/2 */ 685 { 4, 2 }, /* VCLK_SRC/4 */ 686 { 8, 3 }, /* VCLK_SRC/8 */ 687 { 3, 4 }, /* VCLK_SRC/3 */ 688 { 16, 5 }, /* VCLK_SRC/16 */ 689 { 6, 6 }, /* VCLK_SRC/6 */ 690 { 12, 7 }, /* VCLK_SRC/12 */ 691 { 0, 0 } 692 }; 693 694 if (radeon_crtc->crtc_id) 695 pll = &rdev->clock.p2pll; 696 else 697 pll = &rdev->clock.p1pll; 698 699 if (mode->clock > 200000) /* range limits??? */ 700 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 701 else 702 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 703 704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 705 if (encoder->crtc == crtc) { 706 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 707 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 708 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 709 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 710 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 711 if (lvds) { 712 if (lvds->use_bios_dividers) { 713 pll_ref_div = lvds->panel_ref_divider; 714 pll_fb_post_div = (lvds->panel_fb_divider | 715 (lvds->panel_post_divider << 16)); 716 htotal_cntl = 0; 717 use_bios_divs = true; 718 } 719 } 720 pll_flags |= RADEON_PLL_USE_REF_DIV; 721 } 722 } 723 } 724 725 DRM_DEBUG("\n"); 726 727 if (!use_bios_divs) { 728 radeon_compute_pll(pll, mode->clock, 729 &freq, &feedback_div, &frac_fb_div, 730 &reference_div, &post_divider, 731 pll_flags); 732 733 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 734 if (post_div->divider == post_divider) 735 break; 736 } 737 738 if (!post_div->divider) 739 post_div = &post_divs[0]; 740 741 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", 742 (unsigned)freq, 743 feedback_div, 744 reference_div, 745 post_divider); 746 747 pll_ref_div = reference_div; 748 #if defined(__powerpc__) && (0) /* TODO */ 749 /* apparently programming this otherwise causes a hang??? */ 750 if (info->MacModel == RADEON_MAC_IBOOK) 751 pll_fb_post_div = 0x000600ad; 752 else 753 #endif 754 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 755 756 htotal_cntl = mode->htotal & 0x7; 757 758 } 759 760 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 761 pll_ref_div & 0x3ff, 762 pll_fb_post_div & 0x7ff); 763 764 if (radeon_crtc->crtc_id) { 765 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 766 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 767 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 768 769 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 770 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 771 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 772 773 WREG32_PLL_P(RADEON_P2PLL_CNTL, 774 RADEON_P2PLL_RESET 775 | RADEON_P2PLL_ATOMIC_UPDATE_EN 776 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 777 ~(RADEON_P2PLL_RESET 778 | RADEON_P2PLL_ATOMIC_UPDATE_EN 779 | RADEON_P2PLL_PVG_MASK)); 780 781 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 782 pll_ref_div, 783 ~RADEON_P2PLL_REF_DIV_MASK); 784 785 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 786 pll_fb_post_div, 787 ~RADEON_P2PLL_FB0_DIV_MASK); 788 789 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 790 pll_fb_post_div, 791 ~RADEON_P2PLL_POST0_DIV_MASK); 792 793 radeon_pll2_write_update(dev); 794 radeon_pll2_wait_for_read_update_complete(dev); 795 796 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 797 798 WREG32_PLL_P(RADEON_P2PLL_CNTL, 799 0, 800 ~(RADEON_P2PLL_RESET 801 | RADEON_P2PLL_SLEEP 802 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 803 804 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 805 (unsigned)pll_ref_div, 806 (unsigned)pll_fb_post_div, 807 (unsigned)htotal_cntl, 808 RREG32_PLL(RADEON_P2PLL_CNTL)); 809 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", 810 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 811 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 812 (unsigned)((pll_fb_post_div & 813 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 814 815 mdelay(50); /* Let the clock to lock */ 816 817 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 818 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 819 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 820 821 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 822 } else { 823 if (rdev->flags & RADEON_IS_MOBILITY) { 824 /* A temporal workaround for the occational blanking on certain laptop panels. 825 This appears to related to the PLL divider registers (fail to lock?). 826 It occurs even when all dividers are the same with their old settings. 827 In this case we really don't need to fiddle with PLL registers. 828 By doing this we can avoid the blanking problem with some panels. 829 */ 830 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 831 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 832 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 833 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 834 RADEON_PLL_DIV_SEL, 835 ~(RADEON_PLL_DIV_SEL)); 836 r100_pll_errata_after_index(rdev); 837 return; 838 } 839 } 840 841 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 842 RADEON_VCLK_SRC_SEL_CPUCLK, 843 ~(RADEON_VCLK_SRC_SEL_MASK)); 844 WREG32_PLL_P(RADEON_PPLL_CNTL, 845 RADEON_PPLL_RESET 846 | RADEON_PPLL_ATOMIC_UPDATE_EN 847 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 848 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 849 ~(RADEON_PPLL_RESET 850 | RADEON_PPLL_ATOMIC_UPDATE_EN 851 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 852 | RADEON_PPLL_PVG_MASK)); 853 854 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 855 RADEON_PLL_DIV_SEL, 856 ~(RADEON_PLL_DIV_SEL)); 857 r100_pll_errata_after_index(rdev); 858 859 if (ASIC_IS_R300(rdev) || 860 (rdev->family == CHIP_RS300) || 861 (rdev->family == CHIP_RS400) || 862 (rdev->family == CHIP_RS480)) { 863 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 864 /* When restoring console mode, use saved PPLL_REF_DIV 865 * setting. 866 */ 867 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 868 pll_ref_div, 869 0); 870 } else { 871 /* R300 uses ref_div_acc field as real ref divider */ 872 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 873 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 874 ~R300_PPLL_REF_DIV_ACC_MASK); 875 } 876 } else 877 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 878 pll_ref_div, 879 ~RADEON_PPLL_REF_DIV_MASK); 880 881 WREG32_PLL_P(RADEON_PPLL_DIV_3, 882 pll_fb_post_div, 883 ~RADEON_PPLL_FB3_DIV_MASK); 884 885 WREG32_PLL_P(RADEON_PPLL_DIV_3, 886 pll_fb_post_div, 887 ~RADEON_PPLL_POST3_DIV_MASK); 888 889 radeon_pll_write_update(dev); 890 radeon_pll_wait_for_read_update_complete(dev); 891 892 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 893 894 WREG32_PLL_P(RADEON_PPLL_CNTL, 895 0, 896 ~(RADEON_PPLL_RESET 897 | RADEON_PPLL_SLEEP 898 | RADEON_PPLL_ATOMIC_UPDATE_EN 899 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 900 901 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 902 pll_ref_div, 903 pll_fb_post_div, 904 (unsigned)htotal_cntl, 905 RREG32_PLL(RADEON_PPLL_CNTL)); 906 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", 907 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 908 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 909 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 910 911 mdelay(50); /* Let the clock to lock */ 912 913 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 914 RADEON_VCLK_SRC_SEL_PPLLCLK, 915 ~(RADEON_VCLK_SRC_SEL_MASK)); 916 917 } 918 } 919 920 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 921 struct drm_display_mode *mode, 922 struct drm_display_mode *adjusted_mode) 923 { 924 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 925 return false; 926 return true; 927 } 928 929 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 930 struct drm_display_mode *mode, 931 struct drm_display_mode *adjusted_mode, 932 int x, int y, struct drm_framebuffer *old_fb) 933 { 934 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 935 struct drm_device *dev = crtc->dev; 936 struct radeon_device *rdev = dev->dev_private; 937 938 /* TODO TV */ 939 radeon_crtc_set_base(crtc, x, y, old_fb); 940 radeon_set_crtc_timing(crtc, adjusted_mode); 941 radeon_set_pll(crtc, adjusted_mode); 942 radeon_bandwidth_update(rdev); 943 if (radeon_crtc->crtc_id == 0) { 944 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); 945 } else { 946 if (radeon_crtc->rmx_type != RMX_OFF) { 947 /* FIXME: only first crtc has rmx what should we 948 * do ? 949 */ 950 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 951 } 952 } 953 return 0; 954 } 955 956 static void radeon_crtc_prepare(struct drm_crtc *crtc) 957 { 958 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 959 } 960 961 static void radeon_crtc_commit(struct drm_crtc *crtc) 962 { 963 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 964 } 965 966 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 967 .dpms = radeon_crtc_dpms, 968 .mode_fixup = radeon_crtc_mode_fixup, 969 .mode_set = radeon_crtc_mode_set, 970 .mode_set_base = radeon_crtc_set_base, 971 .prepare = radeon_crtc_prepare, 972 .commit = radeon_crtc_commit, 973 }; 974 975 976 void radeon_legacy_init_crtc(struct drm_device *dev, 977 struct radeon_crtc *radeon_crtc) 978 { 979 if (radeon_crtc->crtc_id == 1) 980 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 981 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 982 } 983