1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include <drm/drm_fixed.h> 30 #include "radeon.h" 31 #include "atom.h" 32 33 static void radeon_overscan_setup(struct drm_crtc *crtc, 34 struct drm_display_mode *mode) 35 { 36 struct drm_device *dev = crtc->dev; 37 struct radeon_device *rdev = dev->dev_private; 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 43 } 44 45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 46 struct drm_display_mode *mode) 47 { 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 51 int xres = mode->hdisplay; 52 int yres = mode->vdisplay; 53 bool hscale = true, vscale = true; 54 int hsync_wid; 55 int vsync_wid; 56 int hsync_start; 57 int blank_width; 58 u32 scale, inc, crtc_more_cntl; 59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 63 64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 65 (RADEON_VERT_STRETCH_RESERVED | 66 RADEON_VERT_AUTO_RATIO_INC); 67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 68 (RADEON_HORZ_FP_LOOP_STRETCH | 69 RADEON_HORZ_AUTO_RATIO_INC); 70 71 crtc_more_cntl = 0; 72 if ((rdev->family == CHIP_RS100) || 73 (rdev->family == CHIP_RS200)) { 74 /* This is to workaround the asic bug for RMX, some versions 75 of BIOS dosen't have this register initialized correctly. */ 76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 77 } 78 79 80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 82 83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 84 if (!hsync_wid) 85 hsync_wid = 1; 86 hsync_start = mode->crtc_hsync_start - 8; 87 88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 89 | ((hsync_wid & 0x3f) << 16) 90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 91 ? RADEON_CRTC_H_SYNC_POL 92 : 0)); 93 94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 95 | ((mode->crtc_vdisplay - 1) << 16)); 96 97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 98 if (!vsync_wid) 99 vsync_wid = 1; 100 101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 102 | ((vsync_wid & 0x1f) << 16) 103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 104 ? RADEON_CRTC_V_SYNC_POL 105 : 0)); 106 107 fp_horz_vert_active = 0; 108 109 if (native_mode->hdisplay == 0 || 110 native_mode->vdisplay == 0) { 111 hscale = false; 112 vscale = false; 113 } else { 114 if (xres > native_mode->hdisplay) 115 xres = native_mode->hdisplay; 116 if (yres > native_mode->vdisplay) 117 yres = native_mode->vdisplay; 118 119 if (xres == native_mode->hdisplay) 120 hscale = false; 121 if (yres == native_mode->vdisplay) 122 vscale = false; 123 } 124 125 switch (radeon_crtc->rmx_type) { 126 case RMX_FULL: 127 case RMX_ASPECT: 128 if (!hscale) 129 fp_horz_stretch |= ((xres/8-1) << 16); 130 else { 131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 133 / native_mode->hdisplay + 1; 134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 135 RADEON_HORZ_STRETCH_BLEND | 136 RADEON_HORZ_STRETCH_ENABLE | 137 ((native_mode->hdisplay/8-1) << 16)); 138 } 139 140 if (!vscale) 141 fp_vert_stretch |= ((yres-1) << 12); 142 else { 143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 145 / native_mode->vdisplay + 1; 146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 147 RADEON_VERT_STRETCH_ENABLE | 148 RADEON_VERT_STRETCH_BLEND | 149 ((native_mode->vdisplay-1) << 12)); 150 } 151 break; 152 case RMX_CENTER: 153 fp_horz_stretch |= ((xres/8-1) << 16); 154 fp_vert_stretch |= ((yres-1) << 12); 155 156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 157 RADEON_CRTC_AUTO_VERT_CENTER_EN); 158 159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 160 if (blank_width > 110) 161 blank_width = 110; 162 163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 165 166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 167 if (!hsync_wid) 168 hsync_wid = 1; 169 170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 171 | ((hsync_wid & 0x3f) << 16) 172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 173 ? RADEON_CRTC_H_SYNC_POL 174 : 0)); 175 176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 177 | ((mode->crtc_vdisplay - 1) << 16)); 178 179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 180 if (!vsync_wid) 181 vsync_wid = 1; 182 183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 184 | ((vsync_wid & 0x1f) << 16) 185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 186 ? RADEON_CRTC_V_SYNC_POL 187 : 0))); 188 189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 190 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 191 break; 192 case RMX_OFF: 193 default: 194 fp_horz_stretch |= ((xres/8-1) << 16); 195 fp_vert_stretch |= ((yres-1) << 12); 196 break; 197 } 198 199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 207 } 208 209 void radeon_restore_common_regs(struct drm_device *dev) 210 { 211 /* don't need this yet */ 212 } 213 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 215 { 216 struct radeon_device *rdev = dev->dev_private; 217 int i = 0; 218 219 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 220 the cause yet, but this workaround will mask the problem for now. 221 Other chips usually will pass at the very first test, so the 222 workaround shouldn't have any effect on them. */ 223 for (i = 0; 224 (i < 10000 && 225 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 226 i++); 227 } 228 229 static void radeon_pll_write_update(struct drm_device *dev) 230 { 231 struct radeon_device *rdev = dev->dev_private; 232 233 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 234 235 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 236 RADEON_PPLL_ATOMIC_UPDATE_W, 237 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 238 } 239 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 241 { 242 struct radeon_device *rdev = dev->dev_private; 243 int i = 0; 244 245 246 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 247 the cause yet, but this workaround will mask the problem for now. 248 Other chips usually will pass at the very first test, so the 249 workaround shouldn't have any effect on them. */ 250 for (i = 0; 251 (i < 10000 && 252 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 253 i++); 254 } 255 256 static void radeon_pll2_write_update(struct drm_device *dev) 257 { 258 struct radeon_device *rdev = dev->dev_private; 259 260 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 261 262 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 263 RADEON_P2PLL_ATOMIC_UPDATE_W, 264 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 265 } 266 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 268 uint16_t fb_div) 269 { 270 unsigned int vcoFreq; 271 272 if (!ref_div) 273 return 1; 274 275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 276 277 /* 278 * This is horribly crude: the VCO frequency range is divided into 279 * 3 parts, each part having a fixed PLL gain value. 280 */ 281 if (vcoFreq >= 30000) 282 /* 283 * [300..max] MHz : 7 284 */ 285 return 7; 286 else if (vcoFreq >= 18000) 287 /* 288 * [180..300) MHz : 4 289 */ 290 return 4; 291 else 292 /* 293 * [0..180) MHz : 1 294 */ 295 return 1; 296 } 297 298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 299 { 300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 301 struct drm_device *dev = crtc->dev; 302 struct radeon_device *rdev = dev->dev_private; 303 uint32_t mask; 304 305 if (radeon_crtc->crtc_id) 306 mask = (RADEON_CRTC2_DISP_DIS | 307 RADEON_CRTC2_VSYNC_DIS | 308 RADEON_CRTC2_HSYNC_DIS | 309 RADEON_CRTC2_DISP_REQ_EN_B); 310 else 311 mask = (RADEON_CRTC_DISPLAY_DIS | 312 RADEON_CRTC_VSYNC_DIS | 313 RADEON_CRTC_HSYNC_DIS); 314 315 switch (mode) { 316 case DRM_MODE_DPMS_ON: 317 radeon_crtc->enabled = true; 318 /* adjust pm to dpms changes BEFORE enabling crtcs */ 319 radeon_pm_compute_clocks(rdev); 320 if (radeon_crtc->crtc_id) 321 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 322 else { 323 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 324 RADEON_CRTC_DISP_REQ_EN_B)); 325 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 326 } 327 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 328 radeon_crtc_load_lut(crtc); 329 break; 330 case DRM_MODE_DPMS_STANDBY: 331 case DRM_MODE_DPMS_SUSPEND: 332 case DRM_MODE_DPMS_OFF: 333 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 334 if (radeon_crtc->crtc_id) 335 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 336 else { 337 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 338 RADEON_CRTC_DISP_REQ_EN_B)); 339 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 340 } 341 radeon_crtc->enabled = false; 342 /* adjust pm to dpms changes AFTER disabling crtcs */ 343 radeon_pm_compute_clocks(rdev); 344 break; 345 } 346 } 347 348 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 349 struct drm_framebuffer *old_fb) 350 { 351 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 352 } 353 354 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 355 struct drm_framebuffer *fb, 356 int x, int y, enum mode_set_atomic state) 357 { 358 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 359 } 360 361 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 362 struct drm_framebuffer *fb, 363 int x, int y, int atomic) 364 { 365 struct drm_device *dev = crtc->dev; 366 struct radeon_device *rdev = dev->dev_private; 367 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 368 struct radeon_framebuffer *radeon_fb; 369 struct drm_framebuffer *target_fb; 370 struct drm_gem_object *obj; 371 struct radeon_bo *rbo; 372 uint64_t base; 373 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 374 uint32_t crtc_pitch, pitch_pixels; 375 uint32_t tiling_flags; 376 int format; 377 uint32_t gen_cntl_reg, gen_cntl_val; 378 int r; 379 380 DRM_DEBUG_KMS("\n"); 381 /* no fb bound */ 382 if (!atomic && !crtc->fb) { 383 DRM_DEBUG_KMS("No FB bound\n"); 384 return 0; 385 } 386 387 if (atomic) { 388 radeon_fb = to_radeon_framebuffer(fb); 389 target_fb = fb; 390 } 391 else { 392 radeon_fb = to_radeon_framebuffer(crtc->fb); 393 target_fb = crtc->fb; 394 } 395 396 switch (target_fb->bits_per_pixel) { 397 case 8: 398 format = 2; 399 break; 400 case 15: /* 555 */ 401 format = 3; 402 break; 403 case 16: /* 565 */ 404 format = 4; 405 break; 406 case 24: /* RGB */ 407 format = 5; 408 break; 409 case 32: /* xRGB */ 410 format = 6; 411 break; 412 default: 413 return false; 414 } 415 416 /* Pin framebuffer & get tilling informations */ 417 obj = radeon_fb->obj; 418 rbo = obj->driver_private; 419 r = radeon_bo_reserve(rbo, false); 420 if (unlikely(r != 0)) 421 return r; 422 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base); 423 if (unlikely(r != 0)) { 424 radeon_bo_unreserve(rbo); 425 return -EINVAL; 426 } 427 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 428 radeon_bo_unreserve(rbo); 429 if (tiling_flags & RADEON_TILING_MICRO) 430 DRM_ERROR("trying to scanout microtiled buffer\n"); 431 432 /* if scanout was in GTT this really wouldn't work */ 433 /* crtc offset is from display base addr not FB location */ 434 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 435 436 base -= radeon_crtc->legacy_display_base_addr; 437 438 crtc_offset_cntl = 0; 439 440 pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); 441 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + 442 ((target_fb->bits_per_pixel * 8) - 1)) / 443 (target_fb->bits_per_pixel * 8)); 444 crtc_pitch |= crtc_pitch << 16; 445 446 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 447 if (tiling_flags & RADEON_TILING_MACRO) { 448 if (ASIC_IS_R300(rdev)) 449 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 450 R300_CRTC_MICRO_TILE_BUFFER_DIS | 451 R300_CRTC_MACRO_TILE_EN); 452 else 453 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 454 } else { 455 if (ASIC_IS_R300(rdev)) 456 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 457 R300_CRTC_MICRO_TILE_BUFFER_DIS | 458 R300_CRTC_MACRO_TILE_EN); 459 else 460 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 461 } 462 463 if (tiling_flags & RADEON_TILING_MACRO) { 464 if (ASIC_IS_R300(rdev)) { 465 crtc_tile_x0_y0 = x | (y << 16); 466 base &= ~0x7ff; 467 } else { 468 int byteshift = target_fb->bits_per_pixel >> 4; 469 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 470 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 471 crtc_offset_cntl |= (y % 16); 472 } 473 } else { 474 int offset = y * pitch_pixels + x; 475 switch (target_fb->bits_per_pixel) { 476 case 8: 477 offset *= 1; 478 break; 479 case 15: 480 case 16: 481 offset *= 2; 482 break; 483 case 24: 484 offset *= 3; 485 break; 486 case 32: 487 offset *= 4; 488 break; 489 default: 490 return false; 491 } 492 base += offset; 493 } 494 495 base &= ~7; 496 497 if (radeon_crtc->crtc_id == 1) 498 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 499 else 500 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 501 502 gen_cntl_val = RREG32(gen_cntl_reg); 503 gen_cntl_val &= ~(0xf << 8); 504 gen_cntl_val |= (format << 8); 505 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 506 WREG32(gen_cntl_reg, gen_cntl_val); 507 508 crtc_offset = (u32)base; 509 510 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 511 512 if (ASIC_IS_R300(rdev)) { 513 if (radeon_crtc->crtc_id) 514 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 515 else 516 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 517 } 518 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 519 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 520 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 521 522 if (!atomic && fb && fb != crtc->fb) { 523 radeon_fb = to_radeon_framebuffer(fb); 524 rbo = radeon_fb->obj->driver_private; 525 r = radeon_bo_reserve(rbo, false); 526 if (unlikely(r != 0)) 527 return r; 528 radeon_bo_unpin(rbo); 529 radeon_bo_unreserve(rbo); 530 } 531 532 /* Bytes per pixel may have changed */ 533 radeon_bandwidth_update(rdev); 534 535 return 0; 536 } 537 538 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 539 { 540 struct drm_device *dev = crtc->dev; 541 struct radeon_device *rdev = dev->dev_private; 542 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 543 struct drm_encoder *encoder; 544 int format; 545 int hsync_start; 546 int hsync_wid; 547 int vsync_wid; 548 uint32_t crtc_h_total_disp; 549 uint32_t crtc_h_sync_strt_wid; 550 uint32_t crtc_v_total_disp; 551 uint32_t crtc_v_sync_strt_wid; 552 bool is_tv = false; 553 554 DRM_DEBUG_KMS("\n"); 555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 556 if (encoder->crtc == crtc) { 557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 558 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 559 is_tv = true; 560 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 561 break; 562 } 563 } 564 } 565 566 switch (crtc->fb->bits_per_pixel) { 567 case 8: 568 format = 2; 569 break; 570 case 15: /* 555 */ 571 format = 3; 572 break; 573 case 16: /* 565 */ 574 format = 4; 575 break; 576 case 24: /* RGB */ 577 format = 5; 578 break; 579 case 32: /* xRGB */ 580 format = 6; 581 break; 582 default: 583 return false; 584 } 585 586 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 587 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 588 589 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 590 if (!hsync_wid) 591 hsync_wid = 1; 592 hsync_start = mode->crtc_hsync_start - 8; 593 594 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 595 | ((hsync_wid & 0x3f) << 16) 596 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 597 ? RADEON_CRTC_H_SYNC_POL 598 : 0)); 599 600 /* This works for double scan mode. */ 601 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 602 | ((mode->crtc_vdisplay - 1) << 16)); 603 604 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 605 if (!vsync_wid) 606 vsync_wid = 1; 607 608 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 609 | ((vsync_wid & 0x1f) << 16) 610 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 611 ? RADEON_CRTC_V_SYNC_POL 612 : 0)); 613 614 if (radeon_crtc->crtc_id) { 615 uint32_t crtc2_gen_cntl; 616 uint32_t disp2_merge_cntl; 617 618 /* if TV DAC is enabled for another crtc and keep it enabled */ 619 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 620 crtc2_gen_cntl |= ((format << 8) 621 | RADEON_CRTC2_VSYNC_DIS 622 | RADEON_CRTC2_HSYNC_DIS 623 | RADEON_CRTC2_DISP_DIS 624 | RADEON_CRTC2_DISP_REQ_EN_B 625 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 626 ? RADEON_CRTC2_DBL_SCAN_EN 627 : 0) 628 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 629 ? RADEON_CRTC2_CSYNC_EN 630 : 0) 631 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 632 ? RADEON_CRTC2_INTERLACE_EN 633 : 0)); 634 635 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 636 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 637 crtc2_gen_cntl |= RADEON_CRTC2_EN; 638 639 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 640 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 641 642 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 643 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 644 645 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 646 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 647 } else { 648 uint32_t crtc_gen_cntl; 649 uint32_t crtc_ext_cntl; 650 uint32_t disp_merge_cntl; 651 652 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 653 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 654 | (format << 8) 655 | RADEON_CRTC_DISP_REQ_EN_B 656 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 657 ? RADEON_CRTC_DBL_SCAN_EN 658 : 0) 659 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 660 ? RADEON_CRTC_CSYNC_EN 661 : 0) 662 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 663 ? RADEON_CRTC_INTERLACE_EN 664 : 0)); 665 666 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 667 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 668 crtc_gen_cntl |= RADEON_CRTC_EN; 669 670 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 671 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 672 RADEON_CRTC_VSYNC_DIS | 673 RADEON_CRTC_HSYNC_DIS | 674 RADEON_CRTC_DISPLAY_DIS); 675 676 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 677 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 678 679 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 680 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 681 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 682 } 683 684 if (is_tv) 685 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 686 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 687 &crtc_v_sync_strt_wid); 688 689 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 690 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 691 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 692 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 693 694 return true; 695 } 696 697 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 698 { 699 struct drm_device *dev = crtc->dev; 700 struct radeon_device *rdev = dev->dev_private; 701 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 702 struct drm_encoder *encoder; 703 uint32_t feedback_div = 0; 704 uint32_t frac_fb_div = 0; 705 uint32_t reference_div = 0; 706 uint32_t post_divider = 0; 707 uint32_t freq = 0; 708 uint8_t pll_gain; 709 bool use_bios_divs = false; 710 /* PLL registers */ 711 uint32_t pll_ref_div = 0; 712 uint32_t pll_fb_post_div = 0; 713 uint32_t htotal_cntl = 0; 714 bool is_tv = false; 715 struct radeon_pll *pll; 716 717 struct { 718 int divider; 719 int bitvalue; 720 } *post_div, post_divs[] = { 721 /* From RAGE 128 VR/RAGE 128 GL Register 722 * Reference Manual (Technical Reference 723 * Manual P/N RRG-G04100-C Rev. 0.04), page 724 * 3-17 (PLL_DIV_[3:0]). 725 */ 726 { 1, 0 }, /* VCLK_SRC */ 727 { 2, 1 }, /* VCLK_SRC/2 */ 728 { 4, 2 }, /* VCLK_SRC/4 */ 729 { 8, 3 }, /* VCLK_SRC/8 */ 730 { 3, 4 }, /* VCLK_SRC/3 */ 731 { 16, 5 }, /* VCLK_SRC/16 */ 732 { 6, 6 }, /* VCLK_SRC/6 */ 733 { 12, 7 }, /* VCLK_SRC/12 */ 734 { 0, 0 } 735 }; 736 737 if (radeon_crtc->crtc_id) 738 pll = &rdev->clock.p2pll; 739 else 740 pll = &rdev->clock.p1pll; 741 742 pll->flags = RADEON_PLL_LEGACY; 743 744 if (mode->clock > 200000) /* range limits??? */ 745 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 746 else 747 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 748 749 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 750 if (encoder->crtc == crtc) { 751 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 752 753 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 754 is_tv = true; 755 break; 756 } 757 758 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 759 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 760 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 761 if (!rdev->is_atom_bios) { 762 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 763 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 764 if (lvds) { 765 if (lvds->use_bios_dividers) { 766 pll_ref_div = lvds->panel_ref_divider; 767 pll_fb_post_div = (lvds->panel_fb_divider | 768 (lvds->panel_post_divider << 16)); 769 htotal_cntl = 0; 770 use_bios_divs = true; 771 } 772 } 773 } 774 pll->flags |= RADEON_PLL_USE_REF_DIV; 775 } 776 } 777 } 778 779 DRM_DEBUG_KMS("\n"); 780 781 if (!use_bios_divs) { 782 radeon_compute_pll_legacy(pll, mode->clock, 783 &freq, &feedback_div, &frac_fb_div, 784 &reference_div, &post_divider); 785 786 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 787 if (post_div->divider == post_divider) 788 break; 789 } 790 791 if (!post_div->divider) 792 post_div = &post_divs[0]; 793 794 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 795 (unsigned)freq, 796 feedback_div, 797 reference_div, 798 post_divider); 799 800 pll_ref_div = reference_div; 801 #if defined(__powerpc__) && (0) /* TODO */ 802 /* apparently programming this otherwise causes a hang??? */ 803 if (info->MacModel == RADEON_MAC_IBOOK) 804 pll_fb_post_div = 0x000600ad; 805 else 806 #endif 807 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 808 809 htotal_cntl = mode->htotal & 0x7; 810 811 } 812 813 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 814 pll_ref_div & 0x3ff, 815 pll_fb_post_div & 0x7ff); 816 817 if (radeon_crtc->crtc_id) { 818 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 819 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 820 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 821 822 if (is_tv) { 823 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 824 &pll_ref_div, &pll_fb_post_div, 825 &pixclks_cntl); 826 } 827 828 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 829 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 830 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 831 832 WREG32_PLL_P(RADEON_P2PLL_CNTL, 833 RADEON_P2PLL_RESET 834 | RADEON_P2PLL_ATOMIC_UPDATE_EN 835 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 836 ~(RADEON_P2PLL_RESET 837 | RADEON_P2PLL_ATOMIC_UPDATE_EN 838 | RADEON_P2PLL_PVG_MASK)); 839 840 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 841 pll_ref_div, 842 ~RADEON_P2PLL_REF_DIV_MASK); 843 844 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 845 pll_fb_post_div, 846 ~RADEON_P2PLL_FB0_DIV_MASK); 847 848 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 849 pll_fb_post_div, 850 ~RADEON_P2PLL_POST0_DIV_MASK); 851 852 radeon_pll2_write_update(dev); 853 radeon_pll2_wait_for_read_update_complete(dev); 854 855 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 856 857 WREG32_PLL_P(RADEON_P2PLL_CNTL, 858 0, 859 ~(RADEON_P2PLL_RESET 860 | RADEON_P2PLL_SLEEP 861 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 862 863 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 864 (unsigned)pll_ref_div, 865 (unsigned)pll_fb_post_div, 866 (unsigned)htotal_cntl, 867 RREG32_PLL(RADEON_P2PLL_CNTL)); 868 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 869 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 870 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 871 (unsigned)((pll_fb_post_div & 872 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 873 874 mdelay(50); /* Let the clock to lock */ 875 876 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 877 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 878 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 879 880 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 881 } else { 882 uint32_t pixclks_cntl; 883 884 885 if (is_tv) { 886 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 887 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 888 &pll_fb_post_div, &pixclks_cntl); 889 } 890 891 if (rdev->flags & RADEON_IS_MOBILITY) { 892 /* A temporal workaround for the occational blanking on certain laptop panels. 893 This appears to related to the PLL divider registers (fail to lock?). 894 It occurs even when all dividers are the same with their old settings. 895 In this case we really don't need to fiddle with PLL registers. 896 By doing this we can avoid the blanking problem with some panels. 897 */ 898 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 899 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 900 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 901 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 902 RADEON_PLL_DIV_SEL, 903 ~(RADEON_PLL_DIV_SEL)); 904 r100_pll_errata_after_index(rdev); 905 return; 906 } 907 } 908 909 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 910 RADEON_VCLK_SRC_SEL_CPUCLK, 911 ~(RADEON_VCLK_SRC_SEL_MASK)); 912 WREG32_PLL_P(RADEON_PPLL_CNTL, 913 RADEON_PPLL_RESET 914 | RADEON_PPLL_ATOMIC_UPDATE_EN 915 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 916 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 917 ~(RADEON_PPLL_RESET 918 | RADEON_PPLL_ATOMIC_UPDATE_EN 919 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 920 | RADEON_PPLL_PVG_MASK)); 921 922 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 923 RADEON_PLL_DIV_SEL, 924 ~(RADEON_PLL_DIV_SEL)); 925 r100_pll_errata_after_index(rdev); 926 927 if (ASIC_IS_R300(rdev) || 928 (rdev->family == CHIP_RS300) || 929 (rdev->family == CHIP_RS400) || 930 (rdev->family == CHIP_RS480)) { 931 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 932 /* When restoring console mode, use saved PPLL_REF_DIV 933 * setting. 934 */ 935 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 936 pll_ref_div, 937 0); 938 } else { 939 /* R300 uses ref_div_acc field as real ref divider */ 940 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 941 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 942 ~R300_PPLL_REF_DIV_ACC_MASK); 943 } 944 } else 945 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 946 pll_ref_div, 947 ~RADEON_PPLL_REF_DIV_MASK); 948 949 WREG32_PLL_P(RADEON_PPLL_DIV_3, 950 pll_fb_post_div, 951 ~RADEON_PPLL_FB3_DIV_MASK); 952 953 WREG32_PLL_P(RADEON_PPLL_DIV_3, 954 pll_fb_post_div, 955 ~RADEON_PPLL_POST3_DIV_MASK); 956 957 radeon_pll_write_update(dev); 958 radeon_pll_wait_for_read_update_complete(dev); 959 960 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 961 962 WREG32_PLL_P(RADEON_PPLL_CNTL, 963 0, 964 ~(RADEON_PPLL_RESET 965 | RADEON_PPLL_SLEEP 966 | RADEON_PPLL_ATOMIC_UPDATE_EN 967 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 968 969 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 970 pll_ref_div, 971 pll_fb_post_div, 972 (unsigned)htotal_cntl, 973 RREG32_PLL(RADEON_PPLL_CNTL)); 974 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 975 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 976 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 977 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 978 979 mdelay(50); /* Let the clock to lock */ 980 981 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 982 RADEON_VCLK_SRC_SEL_PPLLCLK, 983 ~(RADEON_VCLK_SRC_SEL_MASK)); 984 985 if (is_tv) 986 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 987 } 988 } 989 990 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 991 struct drm_display_mode *mode, 992 struct drm_display_mode *adjusted_mode) 993 { 994 struct drm_device *dev = crtc->dev; 995 struct radeon_device *rdev = dev->dev_private; 996 997 /* adjust pm to upcoming mode change */ 998 radeon_pm_compute_clocks(rdev); 999 1000 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1001 return false; 1002 return true; 1003 } 1004 1005 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1006 struct drm_display_mode *mode, 1007 struct drm_display_mode *adjusted_mode, 1008 int x, int y, struct drm_framebuffer *old_fb) 1009 { 1010 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1011 1012 /* TODO TV */ 1013 radeon_crtc_set_base(crtc, x, y, old_fb); 1014 radeon_set_crtc_timing(crtc, adjusted_mode); 1015 radeon_set_pll(crtc, adjusted_mode); 1016 radeon_overscan_setup(crtc, adjusted_mode); 1017 if (radeon_crtc->crtc_id == 0) { 1018 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1019 } else { 1020 if (radeon_crtc->rmx_type != RMX_OFF) { 1021 /* FIXME: only first crtc has rmx what should we 1022 * do ? 1023 */ 1024 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1025 } 1026 } 1027 return 0; 1028 } 1029 1030 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1031 { 1032 struct drm_device *dev = crtc->dev; 1033 struct drm_crtc *crtci; 1034 1035 /* 1036 * The hardware wedges sometimes if you reconfigure one CRTC 1037 * whilst another is running (see fdo bug #24611). 1038 */ 1039 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1040 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1041 } 1042 1043 static void radeon_crtc_commit(struct drm_crtc *crtc) 1044 { 1045 struct drm_device *dev = crtc->dev; 1046 struct drm_crtc *crtci; 1047 1048 /* 1049 * Reenable the CRTCs that should be running. 1050 */ 1051 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1052 if (crtci->enabled) 1053 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1054 } 1055 } 1056 1057 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1058 .dpms = radeon_crtc_dpms, 1059 .mode_fixup = radeon_crtc_mode_fixup, 1060 .mode_set = radeon_crtc_mode_set, 1061 .mode_set_base = radeon_crtc_set_base, 1062 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1063 .prepare = radeon_crtc_prepare, 1064 .commit = radeon_crtc_commit, 1065 .load_lut = radeon_crtc_load_lut, 1066 }; 1067 1068 1069 void radeon_legacy_init_crtc(struct drm_device *dev, 1070 struct radeon_crtc *radeon_crtc) 1071 { 1072 if (radeon_crtc->crtc_id == 1) 1073 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1074 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1075 } 1076