1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 #include <linux/pm_runtime.h> 36 37 #if defined(CONFIG_VGA_SWITCHEROO) 38 bool radeon_is_px(void); 39 #else 40 static inline bool radeon_is_px(void) { return false; } 41 #endif 42 43 /** 44 * radeon_driver_unload_kms - Main unload function for KMS. 45 * 46 * @dev: drm dev pointer 47 * 48 * This is the main unload function for KMS (all asics). 49 * It calls radeon_modeset_fini() to tear down the 50 * displays, and radeon_device_fini() to tear down 51 * the rest of the device (CP, writeback, etc.). 52 * Returns 0 on success. 53 */ 54 int radeon_driver_unload_kms(struct drm_device *dev) 55 { 56 struct radeon_device *rdev = dev->dev_private; 57 58 if (rdev == NULL) 59 return 0; 60 61 if (rdev->rmmio == NULL) 62 goto done_free; 63 64 pm_runtime_get_sync(dev->dev); 65 66 radeon_acpi_fini(rdev); 67 68 radeon_modeset_fini(rdev); 69 radeon_device_fini(rdev); 70 71 done_free: 72 kfree(rdev); 73 dev->dev_private = NULL; 74 return 0; 75 } 76 77 /** 78 * radeon_driver_load_kms - Main load function for KMS. 79 * 80 * @dev: drm dev pointer 81 * @flags: device flags 82 * 83 * This is the main load function for KMS (all asics). 84 * It calls radeon_device_init() to set up the non-display 85 * parts of the chip (asic init, CP, writeback, etc.), and 86 * radeon_modeset_init() to set up the display parts 87 * (crtcs, encoders, hotplug detect, etc.). 88 * Returns 0 on success, error on failure. 89 */ 90 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 91 { 92 struct radeon_device *rdev; 93 int r, acpi_status; 94 95 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 96 if (rdev == NULL) { 97 return -ENOMEM; 98 } 99 dev->dev_private = (void *)rdev; 100 101 /* update BUS flag */ 102 if (drm_pci_device_is_agp(dev)) { 103 flags |= RADEON_IS_AGP; 104 } else if (pci_is_pcie(dev->pdev)) { 105 flags |= RADEON_IS_PCIE; 106 } else { 107 flags |= RADEON_IS_PCI; 108 } 109 110 /* radeon_device_init should report only fatal error 111 * like memory allocation failure or iomapping failure, 112 * or memory manager initialization failure, it must 113 * properly initialize the GPU MC controller and permit 114 * VRAM allocation 115 */ 116 r = radeon_device_init(rdev, dev, dev->pdev, flags); 117 if (r) { 118 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 119 goto out; 120 } 121 122 /* Again modeset_init should fail only on fatal error 123 * otherwise it should provide enough functionalities 124 * for shadowfb to run 125 */ 126 r = radeon_modeset_init(rdev); 127 if (r) 128 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 129 130 /* Call ACPI methods: require modeset init 131 * but failure is not fatal 132 */ 133 if (!r) { 134 acpi_status = radeon_acpi_init(rdev); 135 if (acpi_status) 136 dev_dbg(&dev->pdev->dev, 137 "Error during ACPI methods call\n"); 138 } 139 140 if ((radeon_runtime_pm == 1) || 141 ((radeon_runtime_pm == -1) && radeon_is_px())) { 142 pm_runtime_use_autosuspend(dev->dev); 143 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 144 pm_runtime_set_active(dev->dev); 145 pm_runtime_allow(dev->dev); 146 pm_runtime_mark_last_busy(dev->dev); 147 pm_runtime_put_autosuspend(dev->dev); 148 } 149 150 out: 151 if (r) 152 radeon_driver_unload_kms(dev); 153 154 155 return r; 156 } 157 158 /** 159 * radeon_set_filp_rights - Set filp right. 160 * 161 * @dev: drm dev pointer 162 * @owner: drm file 163 * @applier: drm file 164 * @value: value 165 * 166 * Sets the filp rights for the device (all asics). 167 */ 168 static void radeon_set_filp_rights(struct drm_device *dev, 169 struct drm_file **owner, 170 struct drm_file *applier, 171 uint32_t *value) 172 { 173 mutex_lock(&dev->struct_mutex); 174 if (*value == 1) { 175 /* wants rights */ 176 if (!*owner) 177 *owner = applier; 178 } else if (*value == 0) { 179 /* revokes rights */ 180 if (*owner == applier) 181 *owner = NULL; 182 } 183 *value = *owner == applier ? 1 : 0; 184 mutex_unlock(&dev->struct_mutex); 185 } 186 187 /* 188 * Userspace get information ioctl 189 */ 190 /** 191 * radeon_info_ioctl - answer a device specific request. 192 * 193 * @rdev: radeon device pointer 194 * @data: request object 195 * @filp: drm filp 196 * 197 * This function is used to pass device specific parameters to the userspace 198 * drivers. Examples include: pci device id, pipeline parms, tiling params, 199 * etc. (all asics). 200 * Returns 0 on success, -EINVAL on failure. 201 */ 202 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 203 { 204 struct radeon_device *rdev = dev->dev_private; 205 struct drm_radeon_info *info = data; 206 struct radeon_mode_info *minfo = &rdev->mode_info; 207 uint32_t *value, value_tmp, *value_ptr, value_size; 208 uint64_t value64; 209 struct drm_crtc *crtc; 210 int i, found; 211 212 value_ptr = (uint32_t *)((unsigned long)info->value); 213 value = &value_tmp; 214 value_size = sizeof(uint32_t); 215 216 switch (info->request) { 217 case RADEON_INFO_DEVICE_ID: 218 *value = dev->pdev->device; 219 break; 220 case RADEON_INFO_NUM_GB_PIPES: 221 *value = rdev->num_gb_pipes; 222 break; 223 case RADEON_INFO_NUM_Z_PIPES: 224 *value = rdev->num_z_pipes; 225 break; 226 case RADEON_INFO_ACCEL_WORKING: 227 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 228 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 229 *value = false; 230 else 231 *value = rdev->accel_working; 232 break; 233 case RADEON_INFO_CRTC_FROM_ID: 234 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 235 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 236 return -EFAULT; 237 } 238 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 239 crtc = (struct drm_crtc *)minfo->crtcs[i]; 240 if (crtc && crtc->base.id == *value) { 241 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 242 *value = radeon_crtc->crtc_id; 243 found = 1; 244 break; 245 } 246 } 247 if (!found) { 248 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 249 return -EINVAL; 250 } 251 break; 252 case RADEON_INFO_ACCEL_WORKING2: 253 *value = rdev->accel_working; 254 break; 255 case RADEON_INFO_TILING_CONFIG: 256 if (rdev->family >= CHIP_BONAIRE) 257 *value = rdev->config.cik.tile_config; 258 else if (rdev->family >= CHIP_TAHITI) 259 *value = rdev->config.si.tile_config; 260 else if (rdev->family >= CHIP_CAYMAN) 261 *value = rdev->config.cayman.tile_config; 262 else if (rdev->family >= CHIP_CEDAR) 263 *value = rdev->config.evergreen.tile_config; 264 else if (rdev->family >= CHIP_RV770) 265 *value = rdev->config.rv770.tile_config; 266 else if (rdev->family >= CHIP_R600) 267 *value = rdev->config.r600.tile_config; 268 else { 269 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 270 return -EINVAL; 271 } 272 break; 273 case RADEON_INFO_WANT_HYPERZ: 274 /* The "value" here is both an input and output parameter. 275 * If the input value is 1, filp requests hyper-z access. 276 * If the input value is 0, filp revokes its hyper-z access. 277 * 278 * When returning, the value is 1 if filp owns hyper-z access, 279 * 0 otherwise. */ 280 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 281 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 282 return -EFAULT; 283 } 284 if (*value >= 2) { 285 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 286 return -EINVAL; 287 } 288 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 289 break; 290 case RADEON_INFO_WANT_CMASK: 291 /* The same logic as Hyper-Z. */ 292 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 293 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 294 return -EFAULT; 295 } 296 if (*value >= 2) { 297 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 298 return -EINVAL; 299 } 300 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 301 break; 302 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 303 /* return clock value in KHz */ 304 if (rdev->asic->get_xclk) 305 *value = radeon_get_xclk(rdev) * 10; 306 else 307 *value = rdev->clock.spll.reference_freq * 10; 308 break; 309 case RADEON_INFO_NUM_BACKENDS: 310 if (rdev->family >= CHIP_BONAIRE) 311 *value = rdev->config.cik.max_backends_per_se * 312 rdev->config.cik.max_shader_engines; 313 else if (rdev->family >= CHIP_TAHITI) 314 *value = rdev->config.si.max_backends_per_se * 315 rdev->config.si.max_shader_engines; 316 else if (rdev->family >= CHIP_CAYMAN) 317 *value = rdev->config.cayman.max_backends_per_se * 318 rdev->config.cayman.max_shader_engines; 319 else if (rdev->family >= CHIP_CEDAR) 320 *value = rdev->config.evergreen.max_backends; 321 else if (rdev->family >= CHIP_RV770) 322 *value = rdev->config.rv770.max_backends; 323 else if (rdev->family >= CHIP_R600) 324 *value = rdev->config.r600.max_backends; 325 else { 326 return -EINVAL; 327 } 328 break; 329 case RADEON_INFO_NUM_TILE_PIPES: 330 if (rdev->family >= CHIP_BONAIRE) 331 *value = rdev->config.cik.max_tile_pipes; 332 else if (rdev->family >= CHIP_TAHITI) 333 *value = rdev->config.si.max_tile_pipes; 334 else if (rdev->family >= CHIP_CAYMAN) 335 *value = rdev->config.cayman.max_tile_pipes; 336 else if (rdev->family >= CHIP_CEDAR) 337 *value = rdev->config.evergreen.max_tile_pipes; 338 else if (rdev->family >= CHIP_RV770) 339 *value = rdev->config.rv770.max_tile_pipes; 340 else if (rdev->family >= CHIP_R600) 341 *value = rdev->config.r600.max_tile_pipes; 342 else { 343 return -EINVAL; 344 } 345 break; 346 case RADEON_INFO_FUSION_GART_WORKING: 347 *value = 1; 348 break; 349 case RADEON_INFO_BACKEND_MAP: 350 if (rdev->family >= CHIP_BONAIRE) 351 *value = rdev->config.cik.backend_map; 352 else if (rdev->family >= CHIP_TAHITI) 353 *value = rdev->config.si.backend_map; 354 else if (rdev->family >= CHIP_CAYMAN) 355 *value = rdev->config.cayman.backend_map; 356 else if (rdev->family >= CHIP_CEDAR) 357 *value = rdev->config.evergreen.backend_map; 358 else if (rdev->family >= CHIP_RV770) 359 *value = rdev->config.rv770.backend_map; 360 else if (rdev->family >= CHIP_R600) 361 *value = rdev->config.r600.backend_map; 362 else { 363 return -EINVAL; 364 } 365 break; 366 case RADEON_INFO_VA_START: 367 /* this is where we report if vm is supported or not */ 368 if (rdev->family < CHIP_CAYMAN) 369 return -EINVAL; 370 *value = RADEON_VA_RESERVED_SIZE; 371 break; 372 case RADEON_INFO_IB_VM_MAX_SIZE: 373 /* this is where we report if vm is supported or not */ 374 if (rdev->family < CHIP_CAYMAN) 375 return -EINVAL; 376 *value = RADEON_IB_VM_MAX_SIZE; 377 break; 378 case RADEON_INFO_MAX_PIPES: 379 if (rdev->family >= CHIP_BONAIRE) 380 *value = rdev->config.cik.max_cu_per_sh; 381 else if (rdev->family >= CHIP_TAHITI) 382 *value = rdev->config.si.max_cu_per_sh; 383 else if (rdev->family >= CHIP_CAYMAN) 384 *value = rdev->config.cayman.max_pipes_per_simd; 385 else if (rdev->family >= CHIP_CEDAR) 386 *value = rdev->config.evergreen.max_pipes; 387 else if (rdev->family >= CHIP_RV770) 388 *value = rdev->config.rv770.max_pipes; 389 else if (rdev->family >= CHIP_R600) 390 *value = rdev->config.r600.max_pipes; 391 else { 392 return -EINVAL; 393 } 394 break; 395 case RADEON_INFO_TIMESTAMP: 396 if (rdev->family < CHIP_R600) { 397 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 398 return -EINVAL; 399 } 400 value = (uint32_t*)&value64; 401 value_size = sizeof(uint64_t); 402 value64 = radeon_get_gpu_clock_counter(rdev); 403 break; 404 case RADEON_INFO_MAX_SE: 405 if (rdev->family >= CHIP_BONAIRE) 406 *value = rdev->config.cik.max_shader_engines; 407 else if (rdev->family >= CHIP_TAHITI) 408 *value = rdev->config.si.max_shader_engines; 409 else if (rdev->family >= CHIP_CAYMAN) 410 *value = rdev->config.cayman.max_shader_engines; 411 else if (rdev->family >= CHIP_CEDAR) 412 *value = rdev->config.evergreen.num_ses; 413 else 414 *value = 1; 415 break; 416 case RADEON_INFO_MAX_SH_PER_SE: 417 if (rdev->family >= CHIP_BONAIRE) 418 *value = rdev->config.cik.max_sh_per_se; 419 else if (rdev->family >= CHIP_TAHITI) 420 *value = rdev->config.si.max_sh_per_se; 421 else 422 return -EINVAL; 423 break; 424 case RADEON_INFO_FASTFB_WORKING: 425 *value = rdev->fastfb_working; 426 break; 427 case RADEON_INFO_RING_WORKING: 428 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 429 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 430 return -EFAULT; 431 } 432 switch (*value) { 433 case RADEON_CS_RING_GFX: 434 case RADEON_CS_RING_COMPUTE: 435 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 436 break; 437 case RADEON_CS_RING_DMA: 438 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 439 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 440 break; 441 case RADEON_CS_RING_UVD: 442 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 443 break; 444 case RADEON_CS_RING_VCE: 445 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 446 break; 447 default: 448 return -EINVAL; 449 } 450 break; 451 case RADEON_INFO_SI_TILE_MODE_ARRAY: 452 if (rdev->family >= CHIP_BONAIRE) { 453 value = rdev->config.cik.tile_mode_array; 454 value_size = sizeof(uint32_t)*32; 455 } else if (rdev->family >= CHIP_TAHITI) { 456 value = rdev->config.si.tile_mode_array; 457 value_size = sizeof(uint32_t)*32; 458 } else { 459 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 460 return -EINVAL; 461 } 462 break; 463 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 464 if (rdev->family >= CHIP_BONAIRE) { 465 value = rdev->config.cik.macrotile_mode_array; 466 value_size = sizeof(uint32_t)*16; 467 } else { 468 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 469 return -EINVAL; 470 } 471 break; 472 case RADEON_INFO_SI_CP_DMA_COMPUTE: 473 *value = 1; 474 break; 475 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 476 if (rdev->family >= CHIP_BONAIRE) { 477 *value = rdev->config.cik.backend_enable_mask; 478 } else if (rdev->family >= CHIP_TAHITI) { 479 *value = rdev->config.si.backend_enable_mask; 480 } else { 481 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 482 } 483 break; 484 case RADEON_INFO_MAX_SCLK: 485 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 486 rdev->pm.dpm_enabled) 487 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 488 else 489 *value = rdev->pm.default_sclk * 10; 490 break; 491 case RADEON_INFO_VCE_FW_VERSION: 492 *value = rdev->vce.fw_version; 493 break; 494 case RADEON_INFO_VCE_FB_VERSION: 495 *value = rdev->vce.fb_version; 496 break; 497 case RADEON_INFO_NUM_BYTES_MOVED: 498 value = (uint32_t*)&value64; 499 value_size = sizeof(uint64_t); 500 value64 = atomic64_read(&rdev->num_bytes_moved); 501 break; 502 case RADEON_INFO_VRAM_USAGE: 503 value = (uint32_t*)&value64; 504 value_size = sizeof(uint64_t); 505 value64 = atomic64_read(&rdev->vram_usage); 506 break; 507 case RADEON_INFO_GTT_USAGE: 508 value = (uint32_t*)&value64; 509 value_size = sizeof(uint64_t); 510 value64 = atomic64_read(&rdev->gtt_usage); 511 break; 512 default: 513 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 514 return -EINVAL; 515 } 516 if (copy_to_user(value_ptr, (char*)value, value_size)) { 517 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 518 return -EFAULT; 519 } 520 return 0; 521 } 522 523 524 /* 525 * Outdated mess for old drm with Xorg being in charge (void function now). 526 */ 527 /** 528 * radeon_driver_firstopen_kms - drm callback for last close 529 * 530 * @dev: drm dev pointer 531 * 532 * Switch vga switcheroo state after last close (all asics). 533 */ 534 void radeon_driver_lastclose_kms(struct drm_device *dev) 535 { 536 vga_switcheroo_process_delayed_switch(); 537 } 538 539 /** 540 * radeon_driver_open_kms - drm callback for open 541 * 542 * @dev: drm dev pointer 543 * @file_priv: drm file 544 * 545 * On device open, init vm on cayman+ (all asics). 546 * Returns 0 on success, error on failure. 547 */ 548 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 549 { 550 struct radeon_device *rdev = dev->dev_private; 551 int r; 552 553 file_priv->driver_priv = NULL; 554 555 r = pm_runtime_get_sync(dev->dev); 556 if (r < 0) 557 return r; 558 559 /* new gpu have virtual address space support */ 560 if (rdev->family >= CHIP_CAYMAN) { 561 struct radeon_fpriv *fpriv; 562 struct radeon_bo_va *bo_va; 563 int r; 564 565 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 566 if (unlikely(!fpriv)) { 567 return -ENOMEM; 568 } 569 570 r = radeon_vm_init(rdev, &fpriv->vm); 571 if (r) 572 return r; 573 574 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 575 if (r) 576 return r; 577 578 /* map the ib pool buffer read only into 579 * virtual address space */ 580 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 581 rdev->ring_tmp_bo.bo); 582 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 583 RADEON_VM_PAGE_READABLE | 584 RADEON_VM_PAGE_SNOOPED); 585 586 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 587 if (r) { 588 radeon_vm_fini(rdev, &fpriv->vm); 589 kfree(fpriv); 590 return r; 591 } 592 593 file_priv->driver_priv = fpriv; 594 } 595 596 pm_runtime_mark_last_busy(dev->dev); 597 pm_runtime_put_autosuspend(dev->dev); 598 return 0; 599 } 600 601 /** 602 * radeon_driver_postclose_kms - drm callback for post close 603 * 604 * @dev: drm dev pointer 605 * @file_priv: drm file 606 * 607 * On device post close, tear down vm on cayman+ (all asics). 608 */ 609 void radeon_driver_postclose_kms(struct drm_device *dev, 610 struct drm_file *file_priv) 611 { 612 struct radeon_device *rdev = dev->dev_private; 613 614 /* new gpu have virtual address space support */ 615 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 616 struct radeon_fpriv *fpriv = file_priv->driver_priv; 617 struct radeon_bo_va *bo_va; 618 int r; 619 620 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 621 if (!r) { 622 bo_va = radeon_vm_bo_find(&fpriv->vm, 623 rdev->ring_tmp_bo.bo); 624 if (bo_va) 625 radeon_vm_bo_rmv(rdev, bo_va); 626 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 627 } 628 629 radeon_vm_fini(rdev, &fpriv->vm); 630 kfree(fpriv); 631 file_priv->driver_priv = NULL; 632 } 633 } 634 635 /** 636 * radeon_driver_preclose_kms - drm callback for pre close 637 * 638 * @dev: drm dev pointer 639 * @file_priv: drm file 640 * 641 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 642 * (all asics). 643 */ 644 void radeon_driver_preclose_kms(struct drm_device *dev, 645 struct drm_file *file_priv) 646 { 647 struct radeon_device *rdev = dev->dev_private; 648 if (rdev->hyperz_filp == file_priv) 649 rdev->hyperz_filp = NULL; 650 if (rdev->cmask_filp == file_priv) 651 rdev->cmask_filp = NULL; 652 radeon_uvd_free_handles(rdev, file_priv); 653 radeon_vce_free_handles(rdev, file_priv); 654 } 655 656 /* 657 * VBlank related functions. 658 */ 659 /** 660 * radeon_get_vblank_counter_kms - get frame count 661 * 662 * @dev: drm dev pointer 663 * @crtc: crtc to get the frame count from 664 * 665 * Gets the frame count on the requested crtc (all asics). 666 * Returns frame count on success, -EINVAL on failure. 667 */ 668 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 669 { 670 struct radeon_device *rdev = dev->dev_private; 671 672 if (crtc < 0 || crtc >= rdev->num_crtc) { 673 DRM_ERROR("Invalid crtc %d\n", crtc); 674 return -EINVAL; 675 } 676 677 return radeon_get_vblank_counter(rdev, crtc); 678 } 679 680 /** 681 * radeon_enable_vblank_kms - enable vblank interrupt 682 * 683 * @dev: drm dev pointer 684 * @crtc: crtc to enable vblank interrupt for 685 * 686 * Enable the interrupt on the requested crtc (all asics). 687 * Returns 0 on success, -EINVAL on failure. 688 */ 689 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 690 { 691 struct radeon_device *rdev = dev->dev_private; 692 unsigned long irqflags; 693 int r; 694 695 if (crtc < 0 || crtc >= rdev->num_crtc) { 696 DRM_ERROR("Invalid crtc %d\n", crtc); 697 return -EINVAL; 698 } 699 700 spin_lock_irqsave(&rdev->irq.lock, irqflags); 701 rdev->irq.crtc_vblank_int[crtc] = true; 702 r = radeon_irq_set(rdev); 703 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 704 return r; 705 } 706 707 /** 708 * radeon_disable_vblank_kms - disable vblank interrupt 709 * 710 * @dev: drm dev pointer 711 * @crtc: crtc to disable vblank interrupt for 712 * 713 * Disable the interrupt on the requested crtc (all asics). 714 */ 715 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 716 { 717 struct radeon_device *rdev = dev->dev_private; 718 unsigned long irqflags; 719 720 if (crtc < 0 || crtc >= rdev->num_crtc) { 721 DRM_ERROR("Invalid crtc %d\n", crtc); 722 return; 723 } 724 725 spin_lock_irqsave(&rdev->irq.lock, irqflags); 726 rdev->irq.crtc_vblank_int[crtc] = false; 727 radeon_irq_set(rdev); 728 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 729 } 730 731 /** 732 * radeon_get_vblank_timestamp_kms - get vblank timestamp 733 * 734 * @dev: drm dev pointer 735 * @crtc: crtc to get the timestamp for 736 * @max_error: max error 737 * @vblank_time: time value 738 * @flags: flags passed to the driver 739 * 740 * Gets the timestamp on the requested crtc based on the 741 * scanout position. (all asics). 742 * Returns postive status flags on success, negative error on failure. 743 */ 744 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 745 int *max_error, 746 struct timeval *vblank_time, 747 unsigned flags) 748 { 749 struct drm_crtc *drmcrtc; 750 struct radeon_device *rdev = dev->dev_private; 751 752 if (crtc < 0 || crtc >= dev->num_crtcs) { 753 DRM_ERROR("Invalid crtc %d\n", crtc); 754 return -EINVAL; 755 } 756 757 /* Get associated drm_crtc: */ 758 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 759 760 /* Helper routine in DRM core does all the work: */ 761 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 762 vblank_time, flags, 763 drmcrtc, &drmcrtc->hwmode); 764 } 765 766 #define KMS_INVALID_IOCTL(name) \ 767 static int name(struct drm_device *dev, void *data, struct drm_file \ 768 *file_priv) \ 769 { \ 770 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 771 return -EINVAL; \ 772 } 773 774 /* 775 * All these ioctls are invalid in kms world. 776 */ 777 KMS_INVALID_IOCTL(radeon_cp_init_kms) 778 KMS_INVALID_IOCTL(radeon_cp_start_kms) 779 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 780 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 781 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 782 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 783 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 784 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 785 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 786 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 787 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 788 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 789 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 790 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 791 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 792 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 793 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 794 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 795 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 796 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 797 KMS_INVALID_IOCTL(radeon_mem_free_kms) 798 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 799 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 800 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 801 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 802 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 803 KMS_INVALID_IOCTL(radeon_surface_free_kms) 804 805 806 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 807 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 808 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 809 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 810 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 811 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 812 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 813 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 814 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 815 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 816 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 817 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 818 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 819 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 820 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 821 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 822 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 823 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 824 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 825 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 826 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 827 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 828 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 829 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 830 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 831 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 832 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 833 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 834 /* KMS */ 835 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 836 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 837 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 838 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 839 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 840 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 841 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 842 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 843 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 844 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 845 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 846 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 847 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 848 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 849 }; 850 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 851