1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 36 /** 37 * radeon_driver_unload_kms - Main unload function for KMS. 38 * 39 * @dev: drm dev pointer 40 * 41 * This is the main unload function for KMS (all asics). 42 * It calls radeon_modeset_fini() to tear down the 43 * displays, and radeon_device_fini() to tear down 44 * the rest of the device (CP, writeback, etc.). 45 * Returns 0 on success. 46 */ 47 int radeon_driver_unload_kms(struct drm_device *dev) 48 { 49 struct radeon_device *rdev = dev->dev_private; 50 51 if (rdev == NULL) 52 return 0; 53 if (rdev->rmmio == NULL) 54 goto done_free; 55 radeon_acpi_fini(rdev); 56 radeon_modeset_fini(rdev); 57 radeon_device_fini(rdev); 58 59 done_free: 60 kfree(rdev); 61 dev->dev_private = NULL; 62 return 0; 63 } 64 65 /** 66 * radeon_driver_load_kms - Main load function for KMS. 67 * 68 * @dev: drm dev pointer 69 * @flags: device flags 70 * 71 * This is the main load function for KMS (all asics). 72 * It calls radeon_device_init() to set up the non-display 73 * parts of the chip (asic init, CP, writeback, etc.), and 74 * radeon_modeset_init() to set up the display parts 75 * (crtcs, encoders, hotplug detect, etc.). 76 * Returns 0 on success, error on failure. 77 */ 78 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 79 { 80 struct radeon_device *rdev; 81 int r, acpi_status; 82 83 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 84 if (rdev == NULL) { 85 return -ENOMEM; 86 } 87 dev->dev_private = (void *)rdev; 88 89 /* update BUS flag */ 90 if (drm_pci_device_is_agp(dev)) { 91 flags |= RADEON_IS_AGP; 92 } else if (pci_is_pcie(dev->pdev)) { 93 flags |= RADEON_IS_PCIE; 94 } else { 95 flags |= RADEON_IS_PCI; 96 } 97 98 /* radeon_device_init should report only fatal error 99 * like memory allocation failure or iomapping failure, 100 * or memory manager initialization failure, it must 101 * properly initialize the GPU MC controller and permit 102 * VRAM allocation 103 */ 104 r = radeon_device_init(rdev, dev, dev->pdev, flags); 105 if (r) { 106 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 107 goto out; 108 } 109 110 /* Again modeset_init should fail only on fatal error 111 * otherwise it should provide enough functionalities 112 * for shadowfb to run 113 */ 114 r = radeon_modeset_init(rdev); 115 if (r) 116 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 117 118 /* Call ACPI methods: require modeset init 119 * but failure is not fatal 120 */ 121 if (!r) { 122 acpi_status = radeon_acpi_init(rdev); 123 if (acpi_status) 124 dev_dbg(&dev->pdev->dev, 125 "Error during ACPI methods call\n"); 126 } 127 128 out: 129 if (r) 130 radeon_driver_unload_kms(dev); 131 return r; 132 } 133 134 /** 135 * radeon_set_filp_rights - Set filp right. 136 * 137 * @dev: drm dev pointer 138 * @owner: drm file 139 * @applier: drm file 140 * @value: value 141 * 142 * Sets the filp rights for the device (all asics). 143 */ 144 static void radeon_set_filp_rights(struct drm_device *dev, 145 struct drm_file **owner, 146 struct drm_file *applier, 147 uint32_t *value) 148 { 149 mutex_lock(&dev->struct_mutex); 150 if (*value == 1) { 151 /* wants rights */ 152 if (!*owner) 153 *owner = applier; 154 } else if (*value == 0) { 155 /* revokes rights */ 156 if (*owner == applier) 157 *owner = NULL; 158 } 159 *value = *owner == applier ? 1 : 0; 160 mutex_unlock(&dev->struct_mutex); 161 } 162 163 /* 164 * Userspace get information ioctl 165 */ 166 /** 167 * radeon_info_ioctl - answer a device specific request. 168 * 169 * @rdev: radeon device pointer 170 * @data: request object 171 * @filp: drm filp 172 * 173 * This function is used to pass device specific parameters to the userspace 174 * drivers. Examples include: pci device id, pipeline parms, tiling params, 175 * etc. (all asics). 176 * Returns 0 on success, -EINVAL on failure. 177 */ 178 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 179 { 180 struct radeon_device *rdev = dev->dev_private; 181 struct drm_radeon_info *info = data; 182 struct radeon_mode_info *minfo = &rdev->mode_info; 183 uint32_t *value, value_tmp, *value_ptr, value_size; 184 uint64_t value64; 185 struct drm_crtc *crtc; 186 int i, found; 187 188 value_ptr = (uint32_t *)((unsigned long)info->value); 189 value = &value_tmp; 190 value_size = sizeof(uint32_t); 191 192 switch (info->request) { 193 case RADEON_INFO_DEVICE_ID: 194 *value = dev->pci_device; 195 break; 196 case RADEON_INFO_NUM_GB_PIPES: 197 *value = rdev->num_gb_pipes; 198 break; 199 case RADEON_INFO_NUM_Z_PIPES: 200 *value = rdev->num_z_pipes; 201 break; 202 case RADEON_INFO_ACCEL_WORKING: 203 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 204 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 205 *value = false; 206 else 207 *value = rdev->accel_working; 208 break; 209 case RADEON_INFO_CRTC_FROM_ID: 210 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 211 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 212 return -EFAULT; 213 } 214 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 215 crtc = (struct drm_crtc *)minfo->crtcs[i]; 216 if (crtc && crtc->base.id == *value) { 217 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 218 *value = radeon_crtc->crtc_id; 219 found = 1; 220 break; 221 } 222 } 223 if (!found) { 224 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 225 return -EINVAL; 226 } 227 break; 228 case RADEON_INFO_ACCEL_WORKING2: 229 *value = rdev->accel_working; 230 break; 231 case RADEON_INFO_TILING_CONFIG: 232 if (rdev->family >= CHIP_BONAIRE) 233 *value = rdev->config.cik.tile_config; 234 else if (rdev->family >= CHIP_TAHITI) 235 *value = rdev->config.si.tile_config; 236 else if (rdev->family >= CHIP_CAYMAN) 237 *value = rdev->config.cayman.tile_config; 238 else if (rdev->family >= CHIP_CEDAR) 239 *value = rdev->config.evergreen.tile_config; 240 else if (rdev->family >= CHIP_RV770) 241 *value = rdev->config.rv770.tile_config; 242 else if (rdev->family >= CHIP_R600) 243 *value = rdev->config.r600.tile_config; 244 else { 245 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 246 return -EINVAL; 247 } 248 break; 249 case RADEON_INFO_WANT_HYPERZ: 250 /* The "value" here is both an input and output parameter. 251 * If the input value is 1, filp requests hyper-z access. 252 * If the input value is 0, filp revokes its hyper-z access. 253 * 254 * When returning, the value is 1 if filp owns hyper-z access, 255 * 0 otherwise. */ 256 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 257 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 258 return -EFAULT; 259 } 260 if (*value >= 2) { 261 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 262 return -EINVAL; 263 } 264 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 265 break; 266 case RADEON_INFO_WANT_CMASK: 267 /* The same logic as Hyper-Z. */ 268 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 269 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 270 return -EFAULT; 271 } 272 if (*value >= 2) { 273 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 274 return -EINVAL; 275 } 276 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 277 break; 278 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 279 /* return clock value in KHz */ 280 if (rdev->asic->get_xclk) 281 *value = radeon_get_xclk(rdev) * 10; 282 else 283 *value = rdev->clock.spll.reference_freq * 10; 284 break; 285 case RADEON_INFO_NUM_BACKENDS: 286 if (rdev->family >= CHIP_BONAIRE) 287 *value = rdev->config.cik.max_backends_per_se * 288 rdev->config.cik.max_shader_engines; 289 else if (rdev->family >= CHIP_TAHITI) 290 *value = rdev->config.si.max_backends_per_se * 291 rdev->config.si.max_shader_engines; 292 else if (rdev->family >= CHIP_CAYMAN) 293 *value = rdev->config.cayman.max_backends_per_se * 294 rdev->config.cayman.max_shader_engines; 295 else if (rdev->family >= CHIP_CEDAR) 296 *value = rdev->config.evergreen.max_backends; 297 else if (rdev->family >= CHIP_RV770) 298 *value = rdev->config.rv770.max_backends; 299 else if (rdev->family >= CHIP_R600) 300 *value = rdev->config.r600.max_backends; 301 else { 302 return -EINVAL; 303 } 304 break; 305 case RADEON_INFO_NUM_TILE_PIPES: 306 if (rdev->family >= CHIP_BONAIRE) 307 *value = rdev->config.cik.max_tile_pipes; 308 else if (rdev->family >= CHIP_TAHITI) 309 *value = rdev->config.si.max_tile_pipes; 310 else if (rdev->family >= CHIP_CAYMAN) 311 *value = rdev->config.cayman.max_tile_pipes; 312 else if (rdev->family >= CHIP_CEDAR) 313 *value = rdev->config.evergreen.max_tile_pipes; 314 else if (rdev->family >= CHIP_RV770) 315 *value = rdev->config.rv770.max_tile_pipes; 316 else if (rdev->family >= CHIP_R600) 317 *value = rdev->config.r600.max_tile_pipes; 318 else { 319 return -EINVAL; 320 } 321 break; 322 case RADEON_INFO_FUSION_GART_WORKING: 323 *value = 1; 324 break; 325 case RADEON_INFO_BACKEND_MAP: 326 if (rdev->family >= CHIP_BONAIRE) 327 return -EINVAL; 328 else if (rdev->family >= CHIP_TAHITI) 329 *value = rdev->config.si.backend_map; 330 else if (rdev->family >= CHIP_CAYMAN) 331 *value = rdev->config.cayman.backend_map; 332 else if (rdev->family >= CHIP_CEDAR) 333 *value = rdev->config.evergreen.backend_map; 334 else if (rdev->family >= CHIP_RV770) 335 *value = rdev->config.rv770.backend_map; 336 else if (rdev->family >= CHIP_R600) 337 *value = rdev->config.r600.backend_map; 338 else { 339 return -EINVAL; 340 } 341 break; 342 case RADEON_INFO_VA_START: 343 /* this is where we report if vm is supported or not */ 344 if (rdev->family < CHIP_CAYMAN) 345 return -EINVAL; 346 *value = RADEON_VA_RESERVED_SIZE; 347 break; 348 case RADEON_INFO_IB_VM_MAX_SIZE: 349 /* this is where we report if vm is supported or not */ 350 if (rdev->family < CHIP_CAYMAN) 351 return -EINVAL; 352 *value = RADEON_IB_VM_MAX_SIZE; 353 break; 354 case RADEON_INFO_MAX_PIPES: 355 if (rdev->family >= CHIP_BONAIRE) 356 *value = rdev->config.cik.max_cu_per_sh; 357 else if (rdev->family >= CHIP_TAHITI) 358 *value = rdev->config.si.max_cu_per_sh; 359 else if (rdev->family >= CHIP_CAYMAN) 360 *value = rdev->config.cayman.max_pipes_per_simd; 361 else if (rdev->family >= CHIP_CEDAR) 362 *value = rdev->config.evergreen.max_pipes; 363 else if (rdev->family >= CHIP_RV770) 364 *value = rdev->config.rv770.max_pipes; 365 else if (rdev->family >= CHIP_R600) 366 *value = rdev->config.r600.max_pipes; 367 else { 368 return -EINVAL; 369 } 370 break; 371 case RADEON_INFO_TIMESTAMP: 372 if (rdev->family < CHIP_R600) { 373 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 374 return -EINVAL; 375 } 376 value = (uint32_t*)&value64; 377 value_size = sizeof(uint64_t); 378 value64 = radeon_get_gpu_clock_counter(rdev); 379 break; 380 case RADEON_INFO_MAX_SE: 381 if (rdev->family >= CHIP_BONAIRE) 382 *value = rdev->config.cik.max_shader_engines; 383 else if (rdev->family >= CHIP_TAHITI) 384 *value = rdev->config.si.max_shader_engines; 385 else if (rdev->family >= CHIP_CAYMAN) 386 *value = rdev->config.cayman.max_shader_engines; 387 else if (rdev->family >= CHIP_CEDAR) 388 *value = rdev->config.evergreen.num_ses; 389 else 390 *value = 1; 391 break; 392 case RADEON_INFO_MAX_SH_PER_SE: 393 if (rdev->family >= CHIP_BONAIRE) 394 *value = rdev->config.cik.max_sh_per_se; 395 else if (rdev->family >= CHIP_TAHITI) 396 *value = rdev->config.si.max_sh_per_se; 397 else 398 return -EINVAL; 399 break; 400 case RADEON_INFO_FASTFB_WORKING: 401 *value = rdev->fastfb_working; 402 break; 403 case RADEON_INFO_RING_WORKING: 404 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) { 405 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 406 return -EFAULT; 407 } 408 switch (*value) { 409 case RADEON_CS_RING_GFX: 410 case RADEON_CS_RING_COMPUTE: 411 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 412 break; 413 case RADEON_CS_RING_DMA: 414 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 415 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 416 break; 417 case RADEON_CS_RING_UVD: 418 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 419 break; 420 default: 421 return -EINVAL; 422 } 423 break; 424 case RADEON_INFO_SI_TILE_MODE_ARRAY: 425 if (rdev->family >= CHIP_BONAIRE) { 426 value = rdev->config.cik.tile_mode_array; 427 value_size = sizeof(uint32_t)*32; 428 } else if (rdev->family >= CHIP_TAHITI) { 429 value = rdev->config.si.tile_mode_array; 430 value_size = sizeof(uint32_t)*32; 431 } else { 432 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 433 return -EINVAL; 434 } 435 break; 436 default: 437 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 438 return -EINVAL; 439 } 440 if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) { 441 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 442 return -EFAULT; 443 } 444 return 0; 445 } 446 447 448 /* 449 * Outdated mess for old drm with Xorg being in charge (void function now). 450 */ 451 /** 452 * radeon_driver_firstopen_kms - drm callback for first open 453 * 454 * @dev: drm dev pointer 455 * 456 * Nothing to be done for KMS (all asics). 457 * Returns 0 on success. 458 */ 459 int radeon_driver_firstopen_kms(struct drm_device *dev) 460 { 461 return 0; 462 } 463 464 /** 465 * radeon_driver_firstopen_kms - drm callback for last close 466 * 467 * @dev: drm dev pointer 468 * 469 * Switch vga switcheroo state after last close (all asics). 470 */ 471 void radeon_driver_lastclose_kms(struct drm_device *dev) 472 { 473 vga_switcheroo_process_delayed_switch(); 474 } 475 476 /** 477 * radeon_driver_open_kms - drm callback for open 478 * 479 * @dev: drm dev pointer 480 * @file_priv: drm file 481 * 482 * On device open, init vm on cayman+ (all asics). 483 * Returns 0 on success, error on failure. 484 */ 485 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 486 { 487 struct radeon_device *rdev = dev->dev_private; 488 489 file_priv->driver_priv = NULL; 490 491 /* new gpu have virtual address space support */ 492 if (rdev->family >= CHIP_CAYMAN) { 493 struct radeon_fpriv *fpriv; 494 struct radeon_bo_va *bo_va; 495 int r; 496 497 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 498 if (unlikely(!fpriv)) { 499 return -ENOMEM; 500 } 501 502 radeon_vm_init(rdev, &fpriv->vm); 503 504 /* map the ib pool buffer read only into 505 * virtual address space */ 506 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 507 rdev->ring_tmp_bo.bo); 508 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 509 RADEON_VM_PAGE_READABLE | 510 RADEON_VM_PAGE_SNOOPED); 511 if (r) { 512 radeon_vm_fini(rdev, &fpriv->vm); 513 kfree(fpriv); 514 return r; 515 } 516 517 file_priv->driver_priv = fpriv; 518 } 519 return 0; 520 } 521 522 /** 523 * radeon_driver_postclose_kms - drm callback for post close 524 * 525 * @dev: drm dev pointer 526 * @file_priv: drm file 527 * 528 * On device post close, tear down vm on cayman+ (all asics). 529 */ 530 void radeon_driver_postclose_kms(struct drm_device *dev, 531 struct drm_file *file_priv) 532 { 533 struct radeon_device *rdev = dev->dev_private; 534 535 /* new gpu have virtual address space support */ 536 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 537 struct radeon_fpriv *fpriv = file_priv->driver_priv; 538 struct radeon_bo_va *bo_va; 539 int r; 540 541 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 542 if (!r) { 543 bo_va = radeon_vm_bo_find(&fpriv->vm, 544 rdev->ring_tmp_bo.bo); 545 if (bo_va) 546 radeon_vm_bo_rmv(rdev, bo_va); 547 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 548 } 549 550 radeon_vm_fini(rdev, &fpriv->vm); 551 kfree(fpriv); 552 file_priv->driver_priv = NULL; 553 } 554 } 555 556 /** 557 * radeon_driver_preclose_kms - drm callback for pre close 558 * 559 * @dev: drm dev pointer 560 * @file_priv: drm file 561 * 562 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 563 * (all asics). 564 */ 565 void radeon_driver_preclose_kms(struct drm_device *dev, 566 struct drm_file *file_priv) 567 { 568 struct radeon_device *rdev = dev->dev_private; 569 if (rdev->hyperz_filp == file_priv) 570 rdev->hyperz_filp = NULL; 571 if (rdev->cmask_filp == file_priv) 572 rdev->cmask_filp = NULL; 573 radeon_uvd_free_handles(rdev, file_priv); 574 } 575 576 /* 577 * VBlank related functions. 578 */ 579 /** 580 * radeon_get_vblank_counter_kms - get frame count 581 * 582 * @dev: drm dev pointer 583 * @crtc: crtc to get the frame count from 584 * 585 * Gets the frame count on the requested crtc (all asics). 586 * Returns frame count on success, -EINVAL on failure. 587 */ 588 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 589 { 590 struct radeon_device *rdev = dev->dev_private; 591 592 if (crtc < 0 || crtc >= rdev->num_crtc) { 593 DRM_ERROR("Invalid crtc %d\n", crtc); 594 return -EINVAL; 595 } 596 597 return radeon_get_vblank_counter(rdev, crtc); 598 } 599 600 /** 601 * radeon_enable_vblank_kms - enable vblank interrupt 602 * 603 * @dev: drm dev pointer 604 * @crtc: crtc to enable vblank interrupt for 605 * 606 * Enable the interrupt on the requested crtc (all asics). 607 * Returns 0 on success, -EINVAL on failure. 608 */ 609 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 610 { 611 struct radeon_device *rdev = dev->dev_private; 612 unsigned long irqflags; 613 int r; 614 615 if (crtc < 0 || crtc >= rdev->num_crtc) { 616 DRM_ERROR("Invalid crtc %d\n", crtc); 617 return -EINVAL; 618 } 619 620 spin_lock_irqsave(&rdev->irq.lock, irqflags); 621 rdev->irq.crtc_vblank_int[crtc] = true; 622 r = radeon_irq_set(rdev); 623 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 624 return r; 625 } 626 627 /** 628 * radeon_disable_vblank_kms - disable vblank interrupt 629 * 630 * @dev: drm dev pointer 631 * @crtc: crtc to disable vblank interrupt for 632 * 633 * Disable the interrupt on the requested crtc (all asics). 634 */ 635 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 636 { 637 struct radeon_device *rdev = dev->dev_private; 638 unsigned long irqflags; 639 640 if (crtc < 0 || crtc >= rdev->num_crtc) { 641 DRM_ERROR("Invalid crtc %d\n", crtc); 642 return; 643 } 644 645 spin_lock_irqsave(&rdev->irq.lock, irqflags); 646 rdev->irq.crtc_vblank_int[crtc] = false; 647 radeon_irq_set(rdev); 648 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 649 } 650 651 /** 652 * radeon_get_vblank_timestamp_kms - get vblank timestamp 653 * 654 * @dev: drm dev pointer 655 * @crtc: crtc to get the timestamp for 656 * @max_error: max error 657 * @vblank_time: time value 658 * @flags: flags passed to the driver 659 * 660 * Gets the timestamp on the requested crtc based on the 661 * scanout position. (all asics). 662 * Returns postive status flags on success, negative error on failure. 663 */ 664 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 665 int *max_error, 666 struct timeval *vblank_time, 667 unsigned flags) 668 { 669 struct drm_crtc *drmcrtc; 670 struct radeon_device *rdev = dev->dev_private; 671 672 if (crtc < 0 || crtc >= dev->num_crtcs) { 673 DRM_ERROR("Invalid crtc %d\n", crtc); 674 return -EINVAL; 675 } 676 677 /* Get associated drm_crtc: */ 678 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 679 680 /* Helper routine in DRM core does all the work: */ 681 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 682 vblank_time, flags, 683 drmcrtc); 684 } 685 686 /* 687 * IOCTL. 688 */ 689 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, 690 struct drm_file *file_priv) 691 { 692 /* Not valid in KMS. */ 693 return -EINVAL; 694 } 695 696 #define KMS_INVALID_IOCTL(name) \ 697 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ 698 { \ 699 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 700 return -EINVAL; \ 701 } 702 703 /* 704 * All these ioctls are invalid in kms world. 705 */ 706 KMS_INVALID_IOCTL(radeon_cp_init_kms) 707 KMS_INVALID_IOCTL(radeon_cp_start_kms) 708 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 709 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 710 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 711 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 712 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 713 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 714 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 715 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 716 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 717 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 718 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 719 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 720 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 721 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 722 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 723 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 724 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 725 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 726 KMS_INVALID_IOCTL(radeon_mem_free_kms) 727 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 728 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 729 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 730 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 731 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 732 KMS_INVALID_IOCTL(radeon_surface_free_kms) 733 734 735 struct drm_ioctl_desc radeon_ioctls_kms[] = { 736 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 737 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 738 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 739 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 740 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 741 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 742 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 743 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 744 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 745 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 746 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 747 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 748 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 749 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 750 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 751 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 752 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 753 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 754 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 755 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 756 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 757 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 758 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 759 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 760 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 761 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 762 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 763 /* KMS */ 764 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 765 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED), 766 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED), 767 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED), 768 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 769 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 770 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED), 771 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED), 772 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED), 773 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 774 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), 775 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 776 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED), 777 }; 778 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 779