1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/slab.h> 32 #include <linux/uaccess.h> 33 #include <linux/vga_switcheroo.h> 34 35 #include <drm/drm_fb_helper.h> 36 #include <drm/drm_file.h> 37 #include <drm/drm_ioctl.h> 38 #include <drm/radeon_drm.h> 39 40 #include "radeon.h" 41 #include "radeon_asic.h" 42 #include "radeon_drv.h" 43 #include "radeon_kms.h" 44 45 #if defined(CONFIG_VGA_SWITCHEROO) 46 bool radeon_has_atpx(void); 47 #else 48 static inline bool radeon_has_atpx(void) { return false; } 49 #endif 50 51 /** 52 * radeon_driver_unload_kms - Main unload function for KMS. 53 * 54 * @dev: drm dev pointer 55 * 56 * This is the main unload function for KMS (all asics). 57 * It calls radeon_modeset_fini() to tear down the 58 * displays, and radeon_device_fini() to tear down 59 * the rest of the device (CP, writeback, etc.). 60 * Returns 0 on success. 61 */ 62 void radeon_driver_unload_kms(struct drm_device *dev) 63 { 64 struct radeon_device *rdev = dev->dev_private; 65 66 if (rdev == NULL) 67 return; 68 69 if (rdev->rmmio == NULL) 70 goto done_free; 71 72 if (radeon_is_px(dev)) { 73 pm_runtime_get_sync(dev->dev); 74 pm_runtime_forbid(dev->dev); 75 } 76 77 radeon_acpi_fini(rdev); 78 79 radeon_modeset_fini(rdev); 80 radeon_device_fini(rdev); 81 82 if (rdev->agp) 83 arch_phys_wc_del(rdev->agp->agp_mtrr); 84 kfree(rdev->agp); 85 rdev->agp = NULL; 86 87 done_free: 88 kfree(rdev); 89 dev->dev_private = NULL; 90 } 91 92 /** 93 * radeon_driver_load_kms - Main load function for KMS. 94 * 95 * @dev: drm dev pointer 96 * @flags: device flags 97 * 98 * This is the main load function for KMS (all asics). 99 * It calls radeon_device_init() to set up the non-display 100 * parts of the chip (asic init, CP, writeback, etc.), and 101 * radeon_modeset_init() to set up the display parts 102 * (crtcs, encoders, hotplug detect, etc.). 103 * Returns 0 on success, error on failure. 104 */ 105 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 106 { 107 struct pci_dev *pdev = to_pci_dev(dev->dev); 108 struct radeon_device *rdev; 109 int r, acpi_status; 110 111 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 112 if (rdev == NULL) { 113 return -ENOMEM; 114 } 115 dev->dev_private = (void *)rdev; 116 117 #ifdef __alpha__ 118 rdev->hose = pdev->sysdata; 119 #endif 120 121 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) 122 rdev->agp = radeon_agp_head_init(dev); 123 if (rdev->agp) { 124 rdev->agp->agp_mtrr = arch_phys_wc_add( 125 rdev->agp->agp_info.aper_base, 126 rdev->agp->agp_info.aper_size * 127 1024 * 1024); 128 } 129 130 /* update BUS flag */ 131 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) { 132 flags |= RADEON_IS_AGP; 133 } else if (pci_is_pcie(pdev)) { 134 flags |= RADEON_IS_PCIE; 135 } else { 136 flags |= RADEON_IS_PCI; 137 } 138 139 if ((radeon_runtime_pm != 0) && 140 radeon_has_atpx() && 141 ((flags & RADEON_IS_IGP) == 0) && 142 !pci_is_thunderbolt_attached(pdev)) 143 flags |= RADEON_IS_PX; 144 145 /* radeon_device_init should report only fatal error 146 * like memory allocation failure or iomapping failure, 147 * or memory manager initialization failure, it must 148 * properly initialize the GPU MC controller and permit 149 * VRAM allocation 150 */ 151 r = radeon_device_init(rdev, dev, pdev, flags); 152 if (r) { 153 dev_err(dev->dev, "Fatal error during GPU init\n"); 154 goto out; 155 } 156 157 /* Again modeset_init should fail only on fatal error 158 * otherwise it should provide enough functionalities 159 * for shadowfb to run 160 */ 161 r = radeon_modeset_init(rdev); 162 if (r) 163 dev_err(dev->dev, "Fatal error during modeset init\n"); 164 165 /* Call ACPI methods: require modeset init 166 * but failure is not fatal 167 */ 168 if (!r) { 169 acpi_status = radeon_acpi_init(rdev); 170 if (acpi_status) 171 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 172 } 173 174 if (radeon_is_px(dev)) { 175 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 176 pm_runtime_use_autosuspend(dev->dev); 177 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 178 pm_runtime_set_active(dev->dev); 179 pm_runtime_allow(dev->dev); 180 pm_runtime_mark_last_busy(dev->dev); 181 pm_runtime_put_autosuspend(dev->dev); 182 } 183 184 out: 185 if (r) 186 radeon_driver_unload_kms(dev); 187 188 189 return r; 190 } 191 192 /** 193 * radeon_set_filp_rights - Set filp right. 194 * 195 * @dev: drm dev pointer 196 * @owner: drm file 197 * @applier: drm file 198 * @value: value 199 * 200 * Sets the filp rights for the device (all asics). 201 */ 202 static void radeon_set_filp_rights(struct drm_device *dev, 203 struct drm_file **owner, 204 struct drm_file *applier, 205 uint32_t *value) 206 { 207 struct radeon_device *rdev = dev->dev_private; 208 209 mutex_lock(&rdev->gem.mutex); 210 if (*value == 1) { 211 /* wants rights */ 212 if (!*owner) 213 *owner = applier; 214 } else if (*value == 0) { 215 /* revokes rights */ 216 if (*owner == applier) 217 *owner = NULL; 218 } 219 *value = *owner == applier ? 1 : 0; 220 mutex_unlock(&rdev->gem.mutex); 221 } 222 223 /* 224 * Userspace get information ioctl 225 */ 226 /** 227 * radeon_info_ioctl - answer a device specific request. 228 * 229 * @dev: drm device pointer 230 * @data: request object 231 * @filp: drm filp 232 * 233 * This function is used to pass device specific parameters to the userspace 234 * drivers. Examples include: pci device id, pipeline parms, tiling params, 235 * etc. (all asics). 236 * Returns 0 on success, -EINVAL on failure. 237 */ 238 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 239 { 240 struct radeon_device *rdev = dev->dev_private; 241 struct drm_radeon_info *info = data; 242 struct radeon_mode_info *minfo = &rdev->mode_info; 243 uint32_t *value, value_tmp, *value_ptr, value_size; 244 uint64_t value64; 245 struct drm_crtc *crtc; 246 int i, found; 247 248 value_ptr = (uint32_t *)((unsigned long)info->value); 249 value = &value_tmp; 250 value_size = sizeof(uint32_t); 251 252 switch (info->request) { 253 case RADEON_INFO_DEVICE_ID: 254 *value = to_pci_dev(dev->dev)->device; 255 break; 256 case RADEON_INFO_NUM_GB_PIPES: 257 *value = rdev->num_gb_pipes; 258 break; 259 case RADEON_INFO_NUM_Z_PIPES: 260 *value = rdev->num_z_pipes; 261 break; 262 case RADEON_INFO_ACCEL_WORKING: 263 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 264 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 265 *value = false; 266 else 267 *value = rdev->accel_working; 268 break; 269 case RADEON_INFO_CRTC_FROM_ID: 270 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 271 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 272 return -EFAULT; 273 } 274 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 275 crtc = (struct drm_crtc *)minfo->crtcs[i]; 276 if (crtc && crtc->base.id == *value) { 277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 278 *value = radeon_crtc->crtc_id; 279 found = 1; 280 break; 281 } 282 } 283 if (!found) { 284 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 285 return -EINVAL; 286 } 287 break; 288 case RADEON_INFO_ACCEL_WORKING2: 289 if (rdev->family == CHIP_HAWAII) { 290 if (rdev->accel_working) { 291 if (rdev->new_fw) 292 *value = 3; 293 else 294 *value = 2; 295 } else { 296 *value = 0; 297 } 298 } else { 299 *value = rdev->accel_working; 300 } 301 break; 302 case RADEON_INFO_TILING_CONFIG: 303 if (rdev->family >= CHIP_BONAIRE) 304 *value = rdev->config.cik.tile_config; 305 else if (rdev->family >= CHIP_TAHITI) 306 *value = rdev->config.si.tile_config; 307 else if (rdev->family >= CHIP_CAYMAN) 308 *value = rdev->config.cayman.tile_config; 309 else if (rdev->family >= CHIP_CEDAR) 310 *value = rdev->config.evergreen.tile_config; 311 else if (rdev->family >= CHIP_RV770) 312 *value = rdev->config.rv770.tile_config; 313 else if (rdev->family >= CHIP_R600) 314 *value = rdev->config.r600.tile_config; 315 else { 316 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 317 return -EINVAL; 318 } 319 break; 320 case RADEON_INFO_WANT_HYPERZ: 321 /* The "value" here is both an input and output parameter. 322 * If the input value is 1, filp requests hyper-z access. 323 * If the input value is 0, filp revokes its hyper-z access. 324 * 325 * When returning, the value is 1 if filp owns hyper-z access, 326 * 0 otherwise. */ 327 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 328 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 329 return -EFAULT; 330 } 331 if (*value >= 2) { 332 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 333 return -EINVAL; 334 } 335 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 336 break; 337 case RADEON_INFO_WANT_CMASK: 338 /* The same logic as Hyper-Z. */ 339 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 340 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 341 return -EFAULT; 342 } 343 if (*value >= 2) { 344 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 345 return -EINVAL; 346 } 347 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 348 break; 349 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 350 /* return clock value in KHz */ 351 if (rdev->asic->get_xclk) 352 *value = radeon_get_xclk(rdev) * 10; 353 else 354 *value = rdev->clock.spll.reference_freq * 10; 355 break; 356 case RADEON_INFO_NUM_BACKENDS: 357 if (rdev->family >= CHIP_BONAIRE) 358 *value = rdev->config.cik.max_backends_per_se * 359 rdev->config.cik.max_shader_engines; 360 else if (rdev->family >= CHIP_TAHITI) 361 *value = rdev->config.si.max_backends_per_se * 362 rdev->config.si.max_shader_engines; 363 else if (rdev->family >= CHIP_CAYMAN) 364 *value = rdev->config.cayman.max_backends_per_se * 365 rdev->config.cayman.max_shader_engines; 366 else if (rdev->family >= CHIP_CEDAR) 367 *value = rdev->config.evergreen.max_backends; 368 else if (rdev->family >= CHIP_RV770) 369 *value = rdev->config.rv770.max_backends; 370 else if (rdev->family >= CHIP_R600) 371 *value = rdev->config.r600.max_backends; 372 else { 373 return -EINVAL; 374 } 375 break; 376 case RADEON_INFO_NUM_TILE_PIPES: 377 if (rdev->family >= CHIP_BONAIRE) 378 *value = rdev->config.cik.max_tile_pipes; 379 else if (rdev->family >= CHIP_TAHITI) 380 *value = rdev->config.si.max_tile_pipes; 381 else if (rdev->family >= CHIP_CAYMAN) 382 *value = rdev->config.cayman.max_tile_pipes; 383 else if (rdev->family >= CHIP_CEDAR) 384 *value = rdev->config.evergreen.max_tile_pipes; 385 else if (rdev->family >= CHIP_RV770) 386 *value = rdev->config.rv770.max_tile_pipes; 387 else if (rdev->family >= CHIP_R600) 388 *value = rdev->config.r600.max_tile_pipes; 389 else { 390 return -EINVAL; 391 } 392 break; 393 case RADEON_INFO_FUSION_GART_WORKING: 394 *value = 1; 395 break; 396 case RADEON_INFO_BACKEND_MAP: 397 if (rdev->family >= CHIP_BONAIRE) 398 *value = rdev->config.cik.backend_map; 399 else if (rdev->family >= CHIP_TAHITI) 400 *value = rdev->config.si.backend_map; 401 else if (rdev->family >= CHIP_CAYMAN) 402 *value = rdev->config.cayman.backend_map; 403 else if (rdev->family >= CHIP_CEDAR) 404 *value = rdev->config.evergreen.backend_map; 405 else if (rdev->family >= CHIP_RV770) 406 *value = rdev->config.rv770.backend_map; 407 else if (rdev->family >= CHIP_R600) 408 *value = rdev->config.r600.backend_map; 409 else { 410 return -EINVAL; 411 } 412 break; 413 case RADEON_INFO_VA_START: 414 /* this is where we report if vm is supported or not */ 415 if (rdev->family < CHIP_CAYMAN) 416 return -EINVAL; 417 *value = RADEON_VA_RESERVED_SIZE; 418 break; 419 case RADEON_INFO_IB_VM_MAX_SIZE: 420 /* this is where we report if vm is supported or not */ 421 if (rdev->family < CHIP_CAYMAN) 422 return -EINVAL; 423 *value = RADEON_IB_VM_MAX_SIZE; 424 break; 425 case RADEON_INFO_MAX_PIPES: 426 if (rdev->family >= CHIP_BONAIRE) 427 *value = rdev->config.cik.max_cu_per_sh; 428 else if (rdev->family >= CHIP_TAHITI) 429 *value = rdev->config.si.max_cu_per_sh; 430 else if (rdev->family >= CHIP_CAYMAN) 431 *value = rdev->config.cayman.max_pipes_per_simd; 432 else if (rdev->family >= CHIP_CEDAR) 433 *value = rdev->config.evergreen.max_pipes; 434 else if (rdev->family >= CHIP_RV770) 435 *value = rdev->config.rv770.max_pipes; 436 else if (rdev->family >= CHIP_R600) 437 *value = rdev->config.r600.max_pipes; 438 else { 439 return -EINVAL; 440 } 441 break; 442 case RADEON_INFO_TIMESTAMP: 443 if (rdev->family < CHIP_R600) { 444 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 445 return -EINVAL; 446 } 447 value = (uint32_t*)&value64; 448 value_size = sizeof(uint64_t); 449 value64 = radeon_get_gpu_clock_counter(rdev); 450 break; 451 case RADEON_INFO_MAX_SE: 452 if (rdev->family >= CHIP_BONAIRE) 453 *value = rdev->config.cik.max_shader_engines; 454 else if (rdev->family >= CHIP_TAHITI) 455 *value = rdev->config.si.max_shader_engines; 456 else if (rdev->family >= CHIP_CAYMAN) 457 *value = rdev->config.cayman.max_shader_engines; 458 else if (rdev->family >= CHIP_CEDAR) 459 *value = rdev->config.evergreen.num_ses; 460 else 461 *value = 1; 462 break; 463 case RADEON_INFO_MAX_SH_PER_SE: 464 if (rdev->family >= CHIP_BONAIRE) 465 *value = rdev->config.cik.max_sh_per_se; 466 else if (rdev->family >= CHIP_TAHITI) 467 *value = rdev->config.si.max_sh_per_se; 468 else 469 return -EINVAL; 470 break; 471 case RADEON_INFO_FASTFB_WORKING: 472 *value = rdev->fastfb_working; 473 break; 474 case RADEON_INFO_RING_WORKING: 475 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 476 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 477 return -EFAULT; 478 } 479 switch (*value) { 480 case RADEON_CS_RING_GFX: 481 case RADEON_CS_RING_COMPUTE: 482 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 483 break; 484 case RADEON_CS_RING_DMA: 485 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 486 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 487 break; 488 case RADEON_CS_RING_UVD: 489 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 490 break; 491 case RADEON_CS_RING_VCE: 492 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 493 break; 494 default: 495 return -EINVAL; 496 } 497 break; 498 case RADEON_INFO_SI_TILE_MODE_ARRAY: 499 if (rdev->family >= CHIP_BONAIRE) { 500 value = rdev->config.cik.tile_mode_array; 501 value_size = sizeof(uint32_t)*32; 502 } else if (rdev->family >= CHIP_TAHITI) { 503 value = rdev->config.si.tile_mode_array; 504 value_size = sizeof(uint32_t)*32; 505 } else { 506 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 507 return -EINVAL; 508 } 509 break; 510 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 511 if (rdev->family >= CHIP_BONAIRE) { 512 value = rdev->config.cik.macrotile_mode_array; 513 value_size = sizeof(uint32_t)*16; 514 } else { 515 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 516 return -EINVAL; 517 } 518 break; 519 case RADEON_INFO_SI_CP_DMA_COMPUTE: 520 *value = 1; 521 break; 522 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 523 if (rdev->family >= CHIP_BONAIRE) { 524 *value = rdev->config.cik.backend_enable_mask; 525 } else if (rdev->family >= CHIP_TAHITI) { 526 *value = rdev->config.si.backend_enable_mask; 527 } else { 528 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 529 return -EINVAL; 530 } 531 break; 532 case RADEON_INFO_MAX_SCLK: 533 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 534 rdev->pm.dpm_enabled) 535 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 536 else 537 *value = rdev->pm.default_sclk * 10; 538 break; 539 case RADEON_INFO_VCE_FW_VERSION: 540 *value = rdev->vce.fw_version; 541 break; 542 case RADEON_INFO_VCE_FB_VERSION: 543 *value = rdev->vce.fb_version; 544 break; 545 case RADEON_INFO_NUM_BYTES_MOVED: 546 value = (uint32_t*)&value64; 547 value_size = sizeof(uint64_t); 548 value64 = atomic64_read(&rdev->num_bytes_moved); 549 break; 550 case RADEON_INFO_VRAM_USAGE: 551 value = (uint32_t*)&value64; 552 value_size = sizeof(uint64_t); 553 value64 = atomic64_read(&rdev->vram_usage); 554 break; 555 case RADEON_INFO_GTT_USAGE: 556 value = (uint32_t*)&value64; 557 value_size = sizeof(uint64_t); 558 value64 = atomic64_read(&rdev->gtt_usage); 559 break; 560 case RADEON_INFO_ACTIVE_CU_COUNT: 561 if (rdev->family >= CHIP_BONAIRE) 562 *value = rdev->config.cik.active_cus; 563 else if (rdev->family >= CHIP_TAHITI) 564 *value = rdev->config.si.active_cus; 565 else if (rdev->family >= CHIP_CAYMAN) 566 *value = rdev->config.cayman.active_simds; 567 else if (rdev->family >= CHIP_CEDAR) 568 *value = rdev->config.evergreen.active_simds; 569 else if (rdev->family >= CHIP_RV770) 570 *value = rdev->config.rv770.active_simds; 571 else if (rdev->family >= CHIP_R600) 572 *value = rdev->config.r600.active_simds; 573 else 574 *value = 1; 575 break; 576 case RADEON_INFO_CURRENT_GPU_TEMP: 577 /* get temperature in millidegrees C */ 578 if (rdev->asic->pm.get_temperature) 579 *value = radeon_get_temperature(rdev); 580 else 581 *value = 0; 582 break; 583 case RADEON_INFO_CURRENT_GPU_SCLK: 584 /* get sclk in Mhz */ 585 if (rdev->pm.dpm_enabled) 586 *value = radeon_dpm_get_current_sclk(rdev) / 100; 587 else 588 *value = rdev->pm.current_sclk / 100; 589 break; 590 case RADEON_INFO_CURRENT_GPU_MCLK: 591 /* get mclk in Mhz */ 592 if (rdev->pm.dpm_enabled) 593 *value = radeon_dpm_get_current_mclk(rdev) / 100; 594 else 595 *value = rdev->pm.current_mclk / 100; 596 break; 597 case RADEON_INFO_READ_REG: 598 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 599 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 600 return -EFAULT; 601 } 602 if (radeon_get_allowed_info_register(rdev, *value, value)) 603 return -EINVAL; 604 break; 605 case RADEON_INFO_VA_UNMAP_WORKING: 606 *value = true; 607 break; 608 case RADEON_INFO_GPU_RESET_COUNTER: 609 *value = atomic_read(&rdev->gpu_reset_counter); 610 break; 611 default: 612 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 613 return -EINVAL; 614 } 615 if (copy_to_user(value_ptr, (char*)value, value_size)) { 616 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 617 return -EFAULT; 618 } 619 return 0; 620 } 621 622 623 /* 624 * Outdated mess for old drm with Xorg being in charge (void function now). 625 */ 626 /** 627 * radeon_driver_lastclose_kms - drm callback for last close 628 * 629 * @dev: drm dev pointer 630 * 631 * Switch vga_switcheroo state after last close (all asics). 632 */ 633 void radeon_driver_lastclose_kms(struct drm_device *dev) 634 { 635 drm_fb_helper_lastclose(dev); 636 vga_switcheroo_process_delayed_switch(); 637 } 638 639 /** 640 * radeon_driver_open_kms - drm callback for open 641 * 642 * @dev: drm dev pointer 643 * @file_priv: drm file 644 * 645 * On device open, init vm on cayman+ (all asics). 646 * Returns 0 on success, error on failure. 647 */ 648 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 649 { 650 struct radeon_device *rdev = dev->dev_private; 651 struct radeon_fpriv *fpriv; 652 struct radeon_vm *vm; 653 int r; 654 655 file_priv->driver_priv = NULL; 656 657 r = pm_runtime_get_sync(dev->dev); 658 if (r < 0) { 659 pm_runtime_put_autosuspend(dev->dev); 660 return r; 661 } 662 663 /* new gpu have virtual address space support */ 664 if (rdev->family >= CHIP_CAYMAN) { 665 666 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 667 if (unlikely(!fpriv)) { 668 r = -ENOMEM; 669 goto err_suspend; 670 } 671 672 if (rdev->accel_working) { 673 vm = &fpriv->vm; 674 r = radeon_vm_init(rdev, vm); 675 if (r) 676 goto err_fpriv; 677 678 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 679 if (r) 680 goto err_vm_fini; 681 682 /* map the ib pool buffer read only into 683 * virtual address space */ 684 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 685 rdev->ring_tmp_bo.bo); 686 if (!vm->ib_bo_va) { 687 r = -ENOMEM; 688 goto err_vm_fini; 689 } 690 691 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 692 RADEON_VA_IB_OFFSET, 693 RADEON_VM_PAGE_READABLE | 694 RADEON_VM_PAGE_SNOOPED); 695 if (r) 696 goto err_vm_fini; 697 } 698 file_priv->driver_priv = fpriv; 699 } 700 701 pm_runtime_mark_last_busy(dev->dev); 702 pm_runtime_put_autosuspend(dev->dev); 703 return 0; 704 705 err_vm_fini: 706 radeon_vm_fini(rdev, vm); 707 err_fpriv: 708 kfree(fpriv); 709 710 err_suspend: 711 pm_runtime_mark_last_busy(dev->dev); 712 pm_runtime_put_autosuspend(dev->dev); 713 return r; 714 } 715 716 /** 717 * radeon_driver_postclose_kms - drm callback for post close 718 * 719 * @dev: drm dev pointer 720 * @file_priv: drm file 721 * 722 * On device close, tear down hyperz and cmask filps on r1xx-r5xx 723 * (all asics). And tear down vm on cayman+ (all asics). 724 */ 725 void radeon_driver_postclose_kms(struct drm_device *dev, 726 struct drm_file *file_priv) 727 { 728 struct radeon_device *rdev = dev->dev_private; 729 730 pm_runtime_get_sync(dev->dev); 731 732 mutex_lock(&rdev->gem.mutex); 733 if (rdev->hyperz_filp == file_priv) 734 rdev->hyperz_filp = NULL; 735 if (rdev->cmask_filp == file_priv) 736 rdev->cmask_filp = NULL; 737 mutex_unlock(&rdev->gem.mutex); 738 739 radeon_uvd_free_handles(rdev, file_priv); 740 radeon_vce_free_handles(rdev, file_priv); 741 742 /* new gpu have virtual address space support */ 743 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 744 struct radeon_fpriv *fpriv = file_priv->driver_priv; 745 struct radeon_vm *vm = &fpriv->vm; 746 int r; 747 748 if (rdev->accel_working) { 749 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 750 if (!r) { 751 if (vm->ib_bo_va) 752 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 753 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 754 } 755 radeon_vm_fini(rdev, vm); 756 } 757 758 kfree(fpriv); 759 file_priv->driver_priv = NULL; 760 } 761 pm_runtime_mark_last_busy(dev->dev); 762 pm_runtime_put_autosuspend(dev->dev); 763 } 764 765 /* 766 * VBlank related functions. 767 */ 768 /** 769 * radeon_get_vblank_counter_kms - get frame count 770 * 771 * @crtc: crtc to get the frame count from 772 * 773 * Gets the frame count on the requested crtc (all asics). 774 * Returns frame count on success, -EINVAL on failure. 775 */ 776 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc) 777 { 778 struct drm_device *dev = crtc->dev; 779 unsigned int pipe = crtc->index; 780 int vpos, hpos, stat; 781 u32 count; 782 struct radeon_device *rdev = dev->dev_private; 783 784 if (pipe >= rdev->num_crtc) { 785 DRM_ERROR("Invalid crtc %u\n", pipe); 786 return -EINVAL; 787 } 788 789 /* The hw increments its frame counter at start of vsync, not at start 790 * of vblank, as is required by DRM core vblank counter handling. 791 * Cook the hw count here to make it appear to the caller as if it 792 * incremented at start of vblank. We measure distance to start of 793 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 794 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 795 * result by 1 to give the proper appearance to caller. 796 */ 797 if (rdev->mode_info.crtcs[pipe]) { 798 /* Repeat readout if needed to provide stable result if 799 * we cross start of vsync during the queries. 800 */ 801 do { 802 count = radeon_get_vblank_counter(rdev, pipe); 803 /* Ask radeon_get_crtc_scanoutpos to return vpos as 804 * distance to start of vblank, instead of regular 805 * vertical scanout pos. 806 */ 807 stat = radeon_get_crtc_scanoutpos( 808 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 809 &vpos, &hpos, NULL, NULL, 810 &rdev->mode_info.crtcs[pipe]->base.hwmode); 811 } while (count != radeon_get_vblank_counter(rdev, pipe)); 812 813 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 814 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 815 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 816 } 817 else { 818 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", 819 pipe, vpos); 820 821 /* Bump counter if we are at >= leading edge of vblank, 822 * but before vsync where vpos would turn negative and 823 * the hw counter really increments. 824 */ 825 if (vpos >= 0) 826 count++; 827 } 828 } 829 else { 830 /* Fallback to use value as is. */ 831 count = radeon_get_vblank_counter(rdev, pipe); 832 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 833 } 834 835 return count; 836 } 837 838 /** 839 * radeon_enable_vblank_kms - enable vblank interrupt 840 * 841 * @crtc: crtc to enable vblank interrupt for 842 * 843 * Enable the interrupt on the requested crtc (all asics). 844 * Returns 0 on success, -EINVAL on failure. 845 */ 846 int radeon_enable_vblank_kms(struct drm_crtc *crtc) 847 { 848 struct drm_device *dev = crtc->dev; 849 unsigned int pipe = crtc->index; 850 struct radeon_device *rdev = dev->dev_private; 851 unsigned long irqflags; 852 int r; 853 854 if (pipe >= rdev->num_crtc) { 855 DRM_ERROR("Invalid crtc %d\n", pipe); 856 return -EINVAL; 857 } 858 859 spin_lock_irqsave(&rdev->irq.lock, irqflags); 860 rdev->irq.crtc_vblank_int[pipe] = true; 861 r = radeon_irq_set(rdev); 862 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 863 return r; 864 } 865 866 /** 867 * radeon_disable_vblank_kms - disable vblank interrupt 868 * 869 * @crtc: crtc to disable vblank interrupt for 870 * 871 * Disable the interrupt on the requested crtc (all asics). 872 */ 873 void radeon_disable_vblank_kms(struct drm_crtc *crtc) 874 { 875 struct drm_device *dev = crtc->dev; 876 unsigned int pipe = crtc->index; 877 struct radeon_device *rdev = dev->dev_private; 878 unsigned long irqflags; 879 880 if (pipe >= rdev->num_crtc) { 881 DRM_ERROR("Invalid crtc %d\n", pipe); 882 return; 883 } 884 885 spin_lock_irqsave(&rdev->irq.lock, irqflags); 886 rdev->irq.crtc_vblank_int[pipe] = false; 887 radeon_irq_set(rdev); 888 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 889 } 890