1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 30 #include <drm/drm_file.h> 31 32 #include "radeon.h" 33 34 /* 35 * IB 36 * IBs (Indirect Buffers) and areas of GPU accessible memory where 37 * commands are stored. You can put a pointer to the IB in the 38 * command ring and the hw will fetch the commands from the IB 39 * and execute them. Generally userspace acceleration drivers 40 * produce command buffers which are send to the kernel and 41 * put in IBs for execution by the requested ring. 42 */ 43 static void radeon_debugfs_sa_init(struct radeon_device *rdev); 44 45 /** 46 * radeon_ib_get - request an IB (Indirect Buffer) 47 * 48 * @rdev: radeon_device pointer 49 * @ring: ring index the IB is associated with 50 * @vm: requested vm 51 * @ib: IB object returned 52 * @size: requested IB size 53 * 54 * Request an IB (all asics). IBs are allocated using the 55 * suballocator. 56 * Returns 0 on success, error on failure. 57 */ 58 int radeon_ib_get(struct radeon_device *rdev, int ring, 59 struct radeon_ib *ib, struct radeon_vm *vm, 60 unsigned size) 61 { 62 int r; 63 64 r = radeon_sa_bo_new(&rdev->ring_tmp_bo, &ib->sa_bo, size, 256); 65 if (r) { 66 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); 67 return r; 68 } 69 70 radeon_sync_create(&ib->sync); 71 72 ib->ring = ring; 73 ib->fence = NULL; 74 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); 75 ib->vm = vm; 76 if (vm) { 77 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address 78 * space and soffset is the offset inside the pool bo 79 */ 80 ib->gpu_addr = drm_suballoc_soffset(ib->sa_bo) + RADEON_VA_IB_OFFSET; 81 } else { 82 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); 83 } 84 ib->is_const_ib = false; 85 86 return 0; 87 } 88 89 /** 90 * radeon_ib_free - free an IB (Indirect Buffer) 91 * 92 * @rdev: radeon_device pointer 93 * @ib: IB object to free 94 * 95 * Free an IB (all asics). 96 */ 97 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) 98 { 99 radeon_sync_free(rdev, &ib->sync, ib->fence); 100 radeon_sa_bo_free(&ib->sa_bo, ib->fence); 101 radeon_fence_unref(&ib->fence); 102 } 103 104 /** 105 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring 106 * 107 * @rdev: radeon_device pointer 108 * @ib: IB object to schedule 109 * @const_ib: Const IB to schedule (SI only) 110 * @hdp_flush: Whether or not to perform an HDP cache flush 111 * 112 * Schedule an IB on the associated ring (all asics). 113 * Returns 0 on success, error on failure. 114 * 115 * On SI, there are two parallel engines fed from the primary ring, 116 * the CE (Constant Engine) and the DE (Drawing Engine). Since 117 * resource descriptors have moved to memory, the CE allows you to 118 * prime the caches while the DE is updating register state so that 119 * the resource descriptors will be already in cache when the draw is 120 * processed. To accomplish this, the userspace driver submits two 121 * IBs, one for the CE and one for the DE. If there is a CE IB (called 122 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 123 * to SI there was just a DE IB. 124 */ 125 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 126 struct radeon_ib *const_ib, bool hdp_flush) 127 { 128 struct radeon_ring *ring = &rdev->ring[ib->ring]; 129 int r = 0; 130 131 if (!ib->length_dw || !ring->ready) { 132 /* TODO: Nothings in the ib we should report. */ 133 dev_err(rdev->dev, "couldn't schedule ib\n"); 134 return -EINVAL; 135 } 136 137 /* 64 dwords should be enough for fence too */ 138 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8); 139 if (r) { 140 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); 141 return r; 142 } 143 144 /* grab a vm id if necessary */ 145 if (ib->vm) { 146 struct radeon_fence *vm_id_fence; 147 vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring); 148 radeon_sync_fence(&ib->sync, vm_id_fence); 149 } 150 151 /* sync with other rings */ 152 r = radeon_sync_rings(rdev, &ib->sync, ib->ring); 153 if (r) { 154 dev_err(rdev->dev, "failed to sync rings (%d)\n", r); 155 radeon_ring_unlock_undo(rdev, ring); 156 return r; 157 } 158 159 if (ib->vm) 160 radeon_vm_flush(rdev, ib->vm, ib->ring, 161 ib->sync.last_vm_update); 162 163 if (const_ib) { 164 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); 165 radeon_sync_free(rdev, &const_ib->sync, NULL); 166 } 167 radeon_ring_ib_execute(rdev, ib->ring, ib); 168 r = radeon_fence_emit(rdev, &ib->fence, ib->ring); 169 if (r) { 170 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); 171 radeon_ring_unlock_undo(rdev, ring); 172 return r; 173 } 174 if (const_ib) { 175 const_ib->fence = radeon_fence_ref(ib->fence); 176 } 177 178 if (ib->vm) 179 radeon_vm_fence(rdev, ib->vm, ib->fence); 180 181 radeon_ring_unlock_commit(rdev, ring, hdp_flush); 182 return 0; 183 } 184 185 /** 186 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool 187 * 188 * @rdev: radeon_device pointer 189 * 190 * Initialize the suballocator to manage a pool of memory 191 * for use as IBs (all asics). 192 * Returns 0 on success, error on failure. 193 */ 194 int radeon_ib_pool_init(struct radeon_device *rdev) 195 { 196 int r; 197 198 if (rdev->ib_pool_ready) { 199 return 0; 200 } 201 202 if (rdev->family >= CHIP_BONAIRE) { 203 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 204 RADEON_IB_POOL_SIZE*64*1024, 256, 205 RADEON_GEM_DOMAIN_GTT, 206 RADEON_GEM_GTT_WC); 207 } else { 208 /* Before CIK, it's better to stick to cacheable GTT due 209 * to the command stream checking 210 */ 211 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 212 RADEON_IB_POOL_SIZE*64*1024, 256, 213 RADEON_GEM_DOMAIN_GTT, 0); 214 } 215 if (r) { 216 return r; 217 } 218 219 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); 220 if (r) { 221 return r; 222 } 223 224 rdev->ib_pool_ready = true; 225 radeon_debugfs_sa_init(rdev); 226 return 0; 227 } 228 229 /** 230 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool 231 * 232 * @rdev: radeon_device pointer 233 * 234 * Tear down the suballocator managing the pool of memory 235 * for use as IBs (all asics). 236 */ 237 void radeon_ib_pool_fini(struct radeon_device *rdev) 238 { 239 if (rdev->ib_pool_ready) { 240 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); 241 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); 242 rdev->ib_pool_ready = false; 243 } 244 } 245 246 /** 247 * radeon_ib_ring_tests - test IBs on the rings 248 * 249 * @rdev: radeon_device pointer 250 * 251 * Test an IB (Indirect Buffer) on each ring. 252 * If the test fails, disable the ring. 253 * Returns 0 on success, error if the primary GFX ring 254 * IB test fails. 255 */ 256 int radeon_ib_ring_tests(struct radeon_device *rdev) 257 { 258 unsigned i; 259 int r; 260 261 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 262 struct radeon_ring *ring = &rdev->ring[i]; 263 264 if (!ring->ready) 265 continue; 266 267 r = radeon_ib_test(rdev, i, ring); 268 if (r) { 269 radeon_fence_driver_force_completion(rdev, i); 270 ring->ready = false; 271 rdev->needs_reset = false; 272 273 if (i == RADEON_RING_TYPE_GFX_INDEX) { 274 /* oh, oh, that's really bad */ 275 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); 276 rdev->accel_working = false; 277 return r; 278 279 } else { 280 /* still not good, but we can live with it */ 281 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); 282 } 283 } 284 } 285 return 0; 286 } 287 288 /* 289 * Debugfs info 290 */ 291 #if defined(CONFIG_DEBUG_FS) 292 293 static int radeon_debugfs_sa_info_show(struct seq_file *m, void *unused) 294 { 295 struct radeon_device *rdev = m->private; 296 297 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); 298 299 return 0; 300 301 } 302 303 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_sa_info); 304 305 #endif 306 307 static void radeon_debugfs_sa_init(struct radeon_device *rdev) 308 { 309 #if defined(CONFIG_DEBUG_FS) 310 struct dentry *root = rdev->ddev->primary->debugfs_root; 311 312 debugfs_create_file("radeon_sa_info", 0444, root, rdev, 313 &radeon_debugfs_sa_info_fops); 314 #endif 315 } 316