1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <drm/drmP.h> 30 #include "radeon.h" 31 32 /* 33 * IB 34 * IBs (Indirect Buffers) and areas of GPU accessible memory where 35 * commands are stored. You can put a pointer to the IB in the 36 * command ring and the hw will fetch the commands from the IB 37 * and execute them. Generally userspace acceleration drivers 38 * produce command buffers which are send to the kernel and 39 * put in IBs for execution by the requested ring. 40 */ 41 static int radeon_debugfs_sa_init(struct radeon_device *rdev); 42 43 /** 44 * radeon_ib_get - request an IB (Indirect Buffer) 45 * 46 * @rdev: radeon_device pointer 47 * @ring: ring index the IB is associated with 48 * @ib: IB object returned 49 * @size: requested IB size 50 * 51 * Request an IB (all asics). IBs are allocated using the 52 * suballocator. 53 * Returns 0 on success, error on failure. 54 */ 55 int radeon_ib_get(struct radeon_device *rdev, int ring, 56 struct radeon_ib *ib, struct radeon_vm *vm, 57 unsigned size) 58 { 59 int r; 60 61 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256); 62 if (r) { 63 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); 64 return r; 65 } 66 67 r = radeon_semaphore_create(rdev, &ib->semaphore); 68 if (r) { 69 return r; 70 } 71 72 ib->ring = ring; 73 ib->fence = NULL; 74 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); 75 ib->vm = vm; 76 if (vm) { 77 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address 78 * space and soffset is the offset inside the pool bo 79 */ 80 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; 81 } else { 82 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); 83 } 84 ib->is_const_ib = false; 85 86 return 0; 87 } 88 89 /** 90 * radeon_ib_free - free an IB (Indirect Buffer) 91 * 92 * @rdev: radeon_device pointer 93 * @ib: IB object to free 94 * 95 * Free an IB (all asics). 96 */ 97 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) 98 { 99 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); 100 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); 101 radeon_fence_unref(&ib->fence); 102 } 103 104 /** 105 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring 106 * 107 * @rdev: radeon_device pointer 108 * @ib: IB object to schedule 109 * @const_ib: Const IB to schedule (SI only) 110 * 111 * Schedule an IB on the associated ring (all asics). 112 * Returns 0 on success, error on failure. 113 * 114 * On SI, there are two parallel engines fed from the primary ring, 115 * the CE (Constant Engine) and the DE (Drawing Engine). Since 116 * resource descriptors have moved to memory, the CE allows you to 117 * prime the caches while the DE is updating register state so that 118 * the resource descriptors will be already in cache when the draw is 119 * processed. To accomplish this, the userspace driver submits two 120 * IBs, one for the CE and one for the DE. If there is a CE IB (called 121 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior 122 * to SI there was just a DE IB. 123 */ 124 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 125 struct radeon_ib *const_ib) 126 { 127 struct radeon_ring *ring = &rdev->ring[ib->ring]; 128 int r = 0; 129 130 if (!ib->length_dw || !ring->ready) { 131 /* TODO: Nothings in the ib we should report. */ 132 dev_err(rdev->dev, "couldn't schedule ib\n"); 133 return -EINVAL; 134 } 135 136 /* 64 dwords should be enough for fence too */ 137 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8); 138 if (r) { 139 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); 140 return r; 141 } 142 143 /* grab a vm id if necessary */ 144 if (ib->vm) { 145 struct radeon_fence *vm_id_fence; 146 vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring); 147 radeon_semaphore_sync_to(ib->semaphore, vm_id_fence); 148 } 149 150 /* sync with other rings */ 151 r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring); 152 if (r) { 153 dev_err(rdev->dev, "failed to sync rings (%d)\n", r); 154 radeon_ring_unlock_undo(rdev, ring); 155 return r; 156 } 157 158 if (ib->vm) 159 radeon_vm_flush(rdev, ib->vm, ib->ring); 160 161 if (const_ib) { 162 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); 163 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); 164 } 165 radeon_ring_ib_execute(rdev, ib->ring, ib); 166 r = radeon_fence_emit(rdev, &ib->fence, ib->ring); 167 if (r) { 168 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); 169 radeon_ring_unlock_undo(rdev, ring); 170 return r; 171 } 172 if (const_ib) { 173 const_ib->fence = radeon_fence_ref(ib->fence); 174 } 175 176 if (ib->vm) 177 radeon_vm_fence(rdev, ib->vm, ib->fence); 178 179 radeon_ring_unlock_commit(rdev, ring); 180 return 0; 181 } 182 183 /** 184 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool 185 * 186 * @rdev: radeon_device pointer 187 * 188 * Initialize the suballocator to manage a pool of memory 189 * for use as IBs (all asics). 190 * Returns 0 on success, error on failure. 191 */ 192 int radeon_ib_pool_init(struct radeon_device *rdev) 193 { 194 int r; 195 196 if (rdev->ib_pool_ready) { 197 return 0; 198 } 199 200 if (rdev->family >= CHIP_BONAIRE) { 201 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 202 RADEON_IB_POOL_SIZE*64*1024, 203 RADEON_GPU_PAGE_SIZE, 204 RADEON_GEM_DOMAIN_GTT, 205 RADEON_GEM_GTT_WC); 206 } else { 207 /* Before CIK, it's better to stick to cacheable GTT due 208 * to the command stream checking 209 */ 210 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, 211 RADEON_IB_POOL_SIZE*64*1024, 212 RADEON_GPU_PAGE_SIZE, 213 RADEON_GEM_DOMAIN_GTT, 0); 214 } 215 if (r) { 216 return r; 217 } 218 219 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); 220 if (r) { 221 return r; 222 } 223 224 rdev->ib_pool_ready = true; 225 if (radeon_debugfs_sa_init(rdev)) { 226 dev_err(rdev->dev, "failed to register debugfs file for SA\n"); 227 } 228 return 0; 229 } 230 231 /** 232 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool 233 * 234 * @rdev: radeon_device pointer 235 * 236 * Tear down the suballocator managing the pool of memory 237 * for use as IBs (all asics). 238 */ 239 void radeon_ib_pool_fini(struct radeon_device *rdev) 240 { 241 if (rdev->ib_pool_ready) { 242 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); 243 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); 244 rdev->ib_pool_ready = false; 245 } 246 } 247 248 /** 249 * radeon_ib_ring_tests - test IBs on the rings 250 * 251 * @rdev: radeon_device pointer 252 * 253 * Test an IB (Indirect Buffer) on each ring. 254 * If the test fails, disable the ring. 255 * Returns 0 on success, error if the primary GFX ring 256 * IB test fails. 257 */ 258 int radeon_ib_ring_tests(struct radeon_device *rdev) 259 { 260 unsigned i; 261 int r; 262 263 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 264 struct radeon_ring *ring = &rdev->ring[i]; 265 266 if (!ring->ready) 267 continue; 268 269 r = radeon_ib_test(rdev, i, ring); 270 if (r) { 271 ring->ready = false; 272 rdev->needs_reset = false; 273 274 if (i == RADEON_RING_TYPE_GFX_INDEX) { 275 /* oh, oh, that's really bad */ 276 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); 277 rdev->accel_working = false; 278 return r; 279 280 } else { 281 /* still not good, but we can live with it */ 282 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); 283 } 284 } 285 } 286 return 0; 287 } 288 289 /* 290 * Debugfs info 291 */ 292 #if defined(CONFIG_DEBUG_FS) 293 294 static int radeon_debugfs_sa_info(struct seq_file *m, void *data) 295 { 296 struct drm_info_node *node = (struct drm_info_node *) m->private; 297 struct drm_device *dev = node->minor->dev; 298 struct radeon_device *rdev = dev->dev_private; 299 300 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); 301 302 return 0; 303 304 } 305 306 static struct drm_info_list radeon_debugfs_sa_list[] = { 307 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, 308 }; 309 310 #endif 311 312 static int radeon_debugfs_sa_init(struct radeon_device *rdev) 313 { 314 #if defined(CONFIG_DEBUG_FS) 315 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); 316 #else 317 return 0; 318 #endif 319 } 320