1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 #include "atom.h" 30 31 /** 32 * radeon_ddc_probe 33 * 34 */ 35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe) 36 { 37 u8 out = 0x0; 38 u8 buf[8]; 39 int ret; 40 struct i2c_msg msgs[] = { 41 { 42 .addr = 0x50, 43 .flags = 0, 44 .len = 1, 45 .buf = &out, 46 }, 47 { 48 .addr = 0x50, 49 .flags = I2C_M_RD, 50 .len = 1, 51 .buf = buf, 52 } 53 }; 54 55 /* Read 8 bytes from i2c for extended probe of EDID header */ 56 if (requires_extended_probe) 57 msgs[1].len = 8; 58 59 /* on hw with routers, select right port */ 60 if (radeon_connector->router.ddc_valid) 61 radeon_router_select_ddc_port(radeon_connector); 62 63 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 64 if (ret != 2) 65 /* Couldn't find an accessible DDC on this connector */ 66 return false; 67 if (requires_extended_probe) { 68 /* Probe also for valid EDID header 69 * EDID header starts with: 70 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 71 * Only the first 6 bytes must be valid as 72 * drm_edid_block_valid() can fix the last 2 bytes */ 73 if (drm_edid_header_is_valid(buf) < 6) { 74 /* Couldn't find an accessible EDID on this 75 * connector */ 76 return false; 77 } 78 } 79 return true; 80 } 81 82 /* bit banging i2c */ 83 84 static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) 85 { 86 struct radeon_device *rdev = i2c->dev->dev_private; 87 struct radeon_i2c_bus_rec *rec = &i2c->rec; 88 uint32_t temp; 89 90 /* RV410 appears to have a bug where the hw i2c in reset 91 * holds the i2c port in a bad state - switch hw i2c away before 92 * doing DDC - do this for all r200s/r300s/r400s for safety sake 93 */ 94 if (rec->hw_capable) { 95 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 96 u32 reg; 97 98 if (rdev->family >= CHIP_RV350) 99 reg = RADEON_GPIO_MONID; 100 else if ((rdev->family == CHIP_R300) || 101 (rdev->family == CHIP_R350)) 102 reg = RADEON_GPIO_DVI_DDC; 103 else 104 reg = RADEON_GPIO_CRT2_DDC; 105 106 mutex_lock(&rdev->dc_hw_i2c_mutex); 107 if (rec->a_clk_reg == reg) { 108 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 109 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 110 } else { 111 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 112 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 113 } 114 mutex_unlock(&rdev->dc_hw_i2c_mutex); 115 } 116 } 117 118 /* switch the pads to ddc mode */ 119 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 120 temp = RREG32(rec->mask_clk_reg); 121 temp &= ~(1 << 16); 122 WREG32(rec->mask_clk_reg, temp); 123 } 124 125 /* clear the output pin values */ 126 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 127 WREG32(rec->a_clk_reg, temp); 128 129 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 130 WREG32(rec->a_data_reg, temp); 131 132 /* set the pins to input */ 133 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 134 WREG32(rec->en_clk_reg, temp); 135 136 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 137 WREG32(rec->en_data_reg, temp); 138 139 /* mask the gpio pins for software use */ 140 temp = RREG32(rec->mask_clk_reg); 141 if (lock_state) 142 temp |= rec->mask_clk_mask; 143 else 144 temp &= ~rec->mask_clk_mask; 145 WREG32(rec->mask_clk_reg, temp); 146 temp = RREG32(rec->mask_clk_reg); 147 148 temp = RREG32(rec->mask_data_reg); 149 if (lock_state) 150 temp |= rec->mask_data_mask; 151 else 152 temp &= ~rec->mask_data_mask; 153 WREG32(rec->mask_data_reg, temp); 154 temp = RREG32(rec->mask_data_reg); 155 } 156 157 static int get_clock(void *i2c_priv) 158 { 159 struct radeon_i2c_chan *i2c = i2c_priv; 160 struct radeon_device *rdev = i2c->dev->dev_private; 161 struct radeon_i2c_bus_rec *rec = &i2c->rec; 162 uint32_t val; 163 164 /* read the value off the pin */ 165 val = RREG32(rec->y_clk_reg); 166 val &= rec->y_clk_mask; 167 168 return (val != 0); 169 } 170 171 172 static int get_data(void *i2c_priv) 173 { 174 struct radeon_i2c_chan *i2c = i2c_priv; 175 struct radeon_device *rdev = i2c->dev->dev_private; 176 struct radeon_i2c_bus_rec *rec = &i2c->rec; 177 uint32_t val; 178 179 /* read the value off the pin */ 180 val = RREG32(rec->y_data_reg); 181 val &= rec->y_data_mask; 182 183 return (val != 0); 184 } 185 186 static void set_clock(void *i2c_priv, int clock) 187 { 188 struct radeon_i2c_chan *i2c = i2c_priv; 189 struct radeon_device *rdev = i2c->dev->dev_private; 190 struct radeon_i2c_bus_rec *rec = &i2c->rec; 191 uint32_t val; 192 193 /* set pin direction */ 194 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 195 val |= clock ? 0 : rec->en_clk_mask; 196 WREG32(rec->en_clk_reg, val); 197 } 198 199 static void set_data(void *i2c_priv, int data) 200 { 201 struct radeon_i2c_chan *i2c = i2c_priv; 202 struct radeon_device *rdev = i2c->dev->dev_private; 203 struct radeon_i2c_bus_rec *rec = &i2c->rec; 204 uint32_t val; 205 206 /* set pin direction */ 207 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 208 val |= data ? 0 : rec->en_data_mask; 209 WREG32(rec->en_data_reg, val); 210 } 211 212 static int pre_xfer(struct i2c_adapter *i2c_adap) 213 { 214 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 215 216 radeon_i2c_do_lock(i2c, 1); 217 218 return 0; 219 } 220 221 static void post_xfer(struct i2c_adapter *i2c_adap) 222 { 223 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 224 225 radeon_i2c_do_lock(i2c, 0); 226 } 227 228 /* hw i2c */ 229 230 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 231 { 232 u32 sclk = rdev->pm.current_sclk; 233 u32 prescale = 0; 234 u32 nm; 235 u8 n, m, loop; 236 int i2c_clock; 237 238 switch (rdev->family) { 239 case CHIP_R100: 240 case CHIP_RV100: 241 case CHIP_RS100: 242 case CHIP_RV200: 243 case CHIP_RS200: 244 case CHIP_R200: 245 case CHIP_RV250: 246 case CHIP_RS300: 247 case CHIP_RV280: 248 case CHIP_R300: 249 case CHIP_R350: 250 case CHIP_RV350: 251 i2c_clock = 60; 252 nm = (sclk * 10) / (i2c_clock * 4); 253 for (loop = 1; loop < 255; loop++) { 254 if ((nm / loop) < loop) 255 break; 256 } 257 n = loop - 1; 258 m = loop - 2; 259 prescale = m | (n << 8); 260 break; 261 case CHIP_RV380: 262 case CHIP_RS400: 263 case CHIP_RS480: 264 case CHIP_R420: 265 case CHIP_R423: 266 case CHIP_RV410: 267 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 268 break; 269 case CHIP_RS600: 270 case CHIP_RS690: 271 case CHIP_RS740: 272 /* todo */ 273 break; 274 case CHIP_RV515: 275 case CHIP_R520: 276 case CHIP_RV530: 277 case CHIP_RV560: 278 case CHIP_RV570: 279 case CHIP_R580: 280 i2c_clock = 50; 281 if (rdev->family == CHIP_R520) 282 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 283 else 284 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 285 break; 286 case CHIP_R600: 287 case CHIP_RV610: 288 case CHIP_RV630: 289 case CHIP_RV670: 290 /* todo */ 291 break; 292 case CHIP_RV620: 293 case CHIP_RV635: 294 case CHIP_RS780: 295 case CHIP_RS880: 296 case CHIP_RV770: 297 case CHIP_RV730: 298 case CHIP_RV710: 299 case CHIP_RV740: 300 /* todo */ 301 break; 302 case CHIP_CEDAR: 303 case CHIP_REDWOOD: 304 case CHIP_JUNIPER: 305 case CHIP_CYPRESS: 306 case CHIP_HEMLOCK: 307 /* todo */ 308 break; 309 default: 310 DRM_ERROR("i2c: unhandled radeon chip\n"); 311 break; 312 } 313 return prescale; 314 } 315 316 317 /* hw i2c engine for r1xx-4xx hardware 318 * hw can buffer up to 15 bytes 319 */ 320 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 321 struct i2c_msg *msgs, int num) 322 { 323 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 324 struct radeon_device *rdev = i2c->dev->dev_private; 325 struct radeon_i2c_bus_rec *rec = &i2c->rec; 326 struct i2c_msg *p; 327 int i, j, k, ret = num; 328 u32 prescale; 329 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 330 u32 tmp, reg; 331 332 mutex_lock(&rdev->dc_hw_i2c_mutex); 333 /* take the pm lock since we need a constant sclk */ 334 mutex_lock(&rdev->pm.mutex); 335 336 prescale = radeon_get_i2c_prescale(rdev); 337 338 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 339 RADEON_I2C_DRIVE_EN | 340 RADEON_I2C_START | 341 RADEON_I2C_STOP | 342 RADEON_I2C_GO); 343 344 if (rdev->is_atom_bios) { 345 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 346 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 347 } 348 349 if (rec->mm_i2c) { 350 i2c_cntl_0 = RADEON_I2C_CNTL_0; 351 i2c_cntl_1 = RADEON_I2C_CNTL_1; 352 i2c_data = RADEON_I2C_DATA; 353 } else { 354 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 355 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 356 i2c_data = RADEON_DVI_I2C_DATA; 357 358 switch (rdev->family) { 359 case CHIP_R100: 360 case CHIP_RV100: 361 case CHIP_RS100: 362 case CHIP_RV200: 363 case CHIP_RS200: 364 case CHIP_RS300: 365 switch (rec->mask_clk_reg) { 366 case RADEON_GPIO_DVI_DDC: 367 /* no gpio select bit */ 368 break; 369 default: 370 DRM_ERROR("gpio not supported with hw i2c\n"); 371 ret = -EINVAL; 372 goto done; 373 } 374 break; 375 case CHIP_R200: 376 /* only bit 4 on r200 */ 377 switch (rec->mask_clk_reg) { 378 case RADEON_GPIO_DVI_DDC: 379 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 380 break; 381 case RADEON_GPIO_MONID: 382 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 383 break; 384 default: 385 DRM_ERROR("gpio not supported with hw i2c\n"); 386 ret = -EINVAL; 387 goto done; 388 } 389 break; 390 case CHIP_RV250: 391 case CHIP_RV280: 392 /* bits 3 and 4 */ 393 switch (rec->mask_clk_reg) { 394 case RADEON_GPIO_DVI_DDC: 395 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 396 break; 397 case RADEON_GPIO_VGA_DDC: 398 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 399 break; 400 case RADEON_GPIO_CRT2_DDC: 401 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 402 break; 403 default: 404 DRM_ERROR("gpio not supported with hw i2c\n"); 405 ret = -EINVAL; 406 goto done; 407 } 408 break; 409 case CHIP_R300: 410 case CHIP_R350: 411 /* only bit 4 on r300/r350 */ 412 switch (rec->mask_clk_reg) { 413 case RADEON_GPIO_VGA_DDC: 414 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 415 break; 416 case RADEON_GPIO_DVI_DDC: 417 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 418 break; 419 default: 420 DRM_ERROR("gpio not supported with hw i2c\n"); 421 ret = -EINVAL; 422 goto done; 423 } 424 break; 425 case CHIP_RV350: 426 case CHIP_RV380: 427 case CHIP_R420: 428 case CHIP_R423: 429 case CHIP_RV410: 430 case CHIP_RS400: 431 case CHIP_RS480: 432 /* bits 3 and 4 */ 433 switch (rec->mask_clk_reg) { 434 case RADEON_GPIO_VGA_DDC: 435 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 436 break; 437 case RADEON_GPIO_DVI_DDC: 438 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 439 break; 440 case RADEON_GPIO_MONID: 441 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 442 break; 443 default: 444 DRM_ERROR("gpio not supported with hw i2c\n"); 445 ret = -EINVAL; 446 goto done; 447 } 448 break; 449 default: 450 DRM_ERROR("unsupported asic\n"); 451 ret = -EINVAL; 452 goto done; 453 break; 454 } 455 } 456 457 /* check for bus probe */ 458 p = &msgs[0]; 459 if ((num == 1) && (p->len == 0)) { 460 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 461 RADEON_I2C_NACK | 462 RADEON_I2C_HALT | 463 RADEON_I2C_SOFT_RST)); 464 WREG32(i2c_data, (p->addr << 1) & 0xff); 465 WREG32(i2c_data, 0); 466 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 467 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 468 RADEON_I2C_EN | 469 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 470 WREG32(i2c_cntl_0, reg); 471 for (k = 0; k < 32; k++) { 472 udelay(10); 473 tmp = RREG32(i2c_cntl_0); 474 if (tmp & RADEON_I2C_GO) 475 continue; 476 tmp = RREG32(i2c_cntl_0); 477 if (tmp & RADEON_I2C_DONE) 478 break; 479 else { 480 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 481 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 482 ret = -EIO; 483 goto done; 484 } 485 } 486 goto done; 487 } 488 489 for (i = 0; i < num; i++) { 490 p = &msgs[i]; 491 for (j = 0; j < p->len; j++) { 492 if (p->flags & I2C_M_RD) { 493 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 494 RADEON_I2C_NACK | 495 RADEON_I2C_HALT | 496 RADEON_I2C_SOFT_RST)); 497 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 498 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 499 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 500 RADEON_I2C_EN | 501 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 502 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 503 for (k = 0; k < 32; k++) { 504 udelay(10); 505 tmp = RREG32(i2c_cntl_0); 506 if (tmp & RADEON_I2C_GO) 507 continue; 508 tmp = RREG32(i2c_cntl_0); 509 if (tmp & RADEON_I2C_DONE) 510 break; 511 else { 512 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 513 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 514 ret = -EIO; 515 goto done; 516 } 517 } 518 p->buf[j] = RREG32(i2c_data) & 0xff; 519 } else { 520 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 521 RADEON_I2C_NACK | 522 RADEON_I2C_HALT | 523 RADEON_I2C_SOFT_RST)); 524 WREG32(i2c_data, (p->addr << 1) & 0xff); 525 WREG32(i2c_data, p->buf[j]); 526 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 527 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 528 RADEON_I2C_EN | 529 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 530 WREG32(i2c_cntl_0, reg); 531 for (k = 0; k < 32; k++) { 532 udelay(10); 533 tmp = RREG32(i2c_cntl_0); 534 if (tmp & RADEON_I2C_GO) 535 continue; 536 tmp = RREG32(i2c_cntl_0); 537 if (tmp & RADEON_I2C_DONE) 538 break; 539 else { 540 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 541 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 542 ret = -EIO; 543 goto done; 544 } 545 } 546 } 547 } 548 } 549 550 done: 551 WREG32(i2c_cntl_0, 0); 552 WREG32(i2c_cntl_1, 0); 553 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 554 RADEON_I2C_NACK | 555 RADEON_I2C_HALT | 556 RADEON_I2C_SOFT_RST)); 557 558 if (rdev->is_atom_bios) { 559 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 560 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 561 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 562 } 563 564 mutex_unlock(&rdev->pm.mutex); 565 mutex_unlock(&rdev->dc_hw_i2c_mutex); 566 567 return ret; 568 } 569 570 /* hw i2c engine for r5xx hardware 571 * hw can buffer up to 15 bytes 572 */ 573 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 574 struct i2c_msg *msgs, int num) 575 { 576 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 577 struct radeon_device *rdev = i2c->dev->dev_private; 578 struct radeon_i2c_bus_rec *rec = &i2c->rec; 579 struct i2c_msg *p; 580 int i, j, remaining, current_count, buffer_offset, ret = num; 581 u32 prescale; 582 u32 tmp, reg; 583 u32 saved1, saved2; 584 585 mutex_lock(&rdev->dc_hw_i2c_mutex); 586 /* take the pm lock since we need a constant sclk */ 587 mutex_lock(&rdev->pm.mutex); 588 589 prescale = radeon_get_i2c_prescale(rdev); 590 591 /* clear gpio mask bits */ 592 tmp = RREG32(rec->mask_clk_reg); 593 tmp &= ~rec->mask_clk_mask; 594 WREG32(rec->mask_clk_reg, tmp); 595 tmp = RREG32(rec->mask_clk_reg); 596 597 tmp = RREG32(rec->mask_data_reg); 598 tmp &= ~rec->mask_data_mask; 599 WREG32(rec->mask_data_reg, tmp); 600 tmp = RREG32(rec->mask_data_reg); 601 602 /* clear pin values */ 603 tmp = RREG32(rec->a_clk_reg); 604 tmp &= ~rec->a_clk_mask; 605 WREG32(rec->a_clk_reg, tmp); 606 tmp = RREG32(rec->a_clk_reg); 607 608 tmp = RREG32(rec->a_data_reg); 609 tmp &= ~rec->a_data_mask; 610 WREG32(rec->a_data_reg, tmp); 611 tmp = RREG32(rec->a_data_reg); 612 613 /* set the pins to input */ 614 tmp = RREG32(rec->en_clk_reg); 615 tmp &= ~rec->en_clk_mask; 616 WREG32(rec->en_clk_reg, tmp); 617 tmp = RREG32(rec->en_clk_reg); 618 619 tmp = RREG32(rec->en_data_reg); 620 tmp &= ~rec->en_data_mask; 621 WREG32(rec->en_data_reg, tmp); 622 tmp = RREG32(rec->en_data_reg); 623 624 /* */ 625 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 626 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 627 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 628 saved2 = RREG32(0x494); 629 WREG32(0x494, saved2 | 0x1); 630 631 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 632 for (i = 0; i < 50; i++) { 633 udelay(1); 634 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 635 break; 636 } 637 if (i == 50) { 638 DRM_ERROR("failed to get i2c bus\n"); 639 ret = -EBUSY; 640 goto done; 641 } 642 643 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 644 switch (rec->mask_clk_reg) { 645 case AVIVO_DC_GPIO_DDC1_MASK: 646 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 647 break; 648 case AVIVO_DC_GPIO_DDC2_MASK: 649 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 650 break; 651 case AVIVO_DC_GPIO_DDC3_MASK: 652 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 653 break; 654 default: 655 DRM_ERROR("gpio not supported with hw i2c\n"); 656 ret = -EINVAL; 657 goto done; 658 } 659 660 /* check for bus probe */ 661 p = &msgs[0]; 662 if ((num == 1) && (p->len == 0)) { 663 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 664 AVIVO_DC_I2C_NACK | 665 AVIVO_DC_I2C_HALT)); 666 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 667 udelay(1); 668 WREG32(AVIVO_DC_I2C_RESET, 0); 669 670 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 671 WREG32(AVIVO_DC_I2C_DATA, 0); 672 673 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 674 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 675 AVIVO_DC_I2C_DATA_COUNT(1) | 676 (prescale << 16))); 677 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 678 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 679 for (j = 0; j < 200; j++) { 680 udelay(50); 681 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 682 if (tmp & AVIVO_DC_I2C_GO) 683 continue; 684 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 685 if (tmp & AVIVO_DC_I2C_DONE) 686 break; 687 else { 688 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 689 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 690 ret = -EIO; 691 goto done; 692 } 693 } 694 goto done; 695 } 696 697 for (i = 0; i < num; i++) { 698 p = &msgs[i]; 699 remaining = p->len; 700 buffer_offset = 0; 701 if (p->flags & I2C_M_RD) { 702 while (remaining) { 703 if (remaining > 15) 704 current_count = 15; 705 else 706 current_count = remaining; 707 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 708 AVIVO_DC_I2C_NACK | 709 AVIVO_DC_I2C_HALT)); 710 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 711 udelay(1); 712 WREG32(AVIVO_DC_I2C_RESET, 0); 713 714 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 715 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 716 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 717 AVIVO_DC_I2C_DATA_COUNT(current_count) | 718 (prescale << 16))); 719 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 720 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 721 for (j = 0; j < 200; j++) { 722 udelay(50); 723 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 724 if (tmp & AVIVO_DC_I2C_GO) 725 continue; 726 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 727 if (tmp & AVIVO_DC_I2C_DONE) 728 break; 729 else { 730 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 731 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 732 ret = -EIO; 733 goto done; 734 } 735 } 736 for (j = 0; j < current_count; j++) 737 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 738 remaining -= current_count; 739 buffer_offset += current_count; 740 } 741 } else { 742 while (remaining) { 743 if (remaining > 15) 744 current_count = 15; 745 else 746 current_count = remaining; 747 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 748 AVIVO_DC_I2C_NACK | 749 AVIVO_DC_I2C_HALT)); 750 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 751 udelay(1); 752 WREG32(AVIVO_DC_I2C_RESET, 0); 753 754 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 755 for (j = 0; j < current_count; j++) 756 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 757 758 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 759 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 760 AVIVO_DC_I2C_DATA_COUNT(current_count) | 761 (prescale << 16))); 762 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 763 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 764 for (j = 0; j < 200; j++) { 765 udelay(50); 766 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 767 if (tmp & AVIVO_DC_I2C_GO) 768 continue; 769 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 770 if (tmp & AVIVO_DC_I2C_DONE) 771 break; 772 else { 773 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 774 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 775 ret = -EIO; 776 goto done; 777 } 778 } 779 remaining -= current_count; 780 buffer_offset += current_count; 781 } 782 } 783 } 784 785 done: 786 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 787 AVIVO_DC_I2C_NACK | 788 AVIVO_DC_I2C_HALT)); 789 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 790 udelay(1); 791 WREG32(AVIVO_DC_I2C_RESET, 0); 792 793 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 794 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 795 WREG32(0x494, saved2); 796 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 797 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 798 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 799 800 mutex_unlock(&rdev->pm.mutex); 801 mutex_unlock(&rdev->dc_hw_i2c_mutex); 802 803 return ret; 804 } 805 806 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 807 struct i2c_msg *msgs, int num) 808 { 809 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 810 struct radeon_device *rdev = i2c->dev->dev_private; 811 struct radeon_i2c_bus_rec *rec = &i2c->rec; 812 int ret = 0; 813 814 switch (rdev->family) { 815 case CHIP_R100: 816 case CHIP_RV100: 817 case CHIP_RS100: 818 case CHIP_RV200: 819 case CHIP_RS200: 820 case CHIP_R200: 821 case CHIP_RV250: 822 case CHIP_RS300: 823 case CHIP_RV280: 824 case CHIP_R300: 825 case CHIP_R350: 826 case CHIP_RV350: 827 case CHIP_RV380: 828 case CHIP_R420: 829 case CHIP_R423: 830 case CHIP_RV410: 831 case CHIP_RS400: 832 case CHIP_RS480: 833 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 834 break; 835 case CHIP_RS600: 836 case CHIP_RS690: 837 case CHIP_RS740: 838 /* XXX fill in hw i2c implementation */ 839 break; 840 case CHIP_RV515: 841 case CHIP_R520: 842 case CHIP_RV530: 843 case CHIP_RV560: 844 case CHIP_RV570: 845 case CHIP_R580: 846 if (rec->mm_i2c) 847 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 848 else 849 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 850 break; 851 case CHIP_R600: 852 case CHIP_RV610: 853 case CHIP_RV630: 854 case CHIP_RV670: 855 /* XXX fill in hw i2c implementation */ 856 break; 857 case CHIP_RV620: 858 case CHIP_RV635: 859 case CHIP_RS780: 860 case CHIP_RS880: 861 case CHIP_RV770: 862 case CHIP_RV730: 863 case CHIP_RV710: 864 case CHIP_RV740: 865 /* XXX fill in hw i2c implementation */ 866 break; 867 case CHIP_CEDAR: 868 case CHIP_REDWOOD: 869 case CHIP_JUNIPER: 870 case CHIP_CYPRESS: 871 case CHIP_HEMLOCK: 872 /* XXX fill in hw i2c implementation */ 873 break; 874 default: 875 DRM_ERROR("i2c: unhandled radeon chip\n"); 876 ret = -EIO; 877 break; 878 } 879 880 return ret; 881 } 882 883 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 884 { 885 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 886 } 887 888 static const struct i2c_algorithm radeon_i2c_algo = { 889 .master_xfer = radeon_hw_i2c_xfer, 890 .functionality = radeon_hw_i2c_func, 891 }; 892 893 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 894 struct radeon_i2c_bus_rec *rec, 895 const char *name) 896 { 897 struct radeon_device *rdev = dev->dev_private; 898 struct radeon_i2c_chan *i2c; 899 int ret; 900 901 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 902 if (i2c == NULL) 903 return NULL; 904 905 i2c->rec = *rec; 906 i2c->adapter.owner = THIS_MODULE; 907 i2c->adapter.class = I2C_CLASS_DDC; 908 i2c->dev = dev; 909 i2c_set_adapdata(&i2c->adapter, i2c); 910 if (rec->mm_i2c || 911 (rec->hw_capable && 912 radeon_hw_i2c && 913 ((rdev->family <= CHIP_RS480) || 914 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 915 /* set the radeon hw i2c adapter */ 916 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 917 "Radeon i2c hw bus %s", name); 918 i2c->adapter.algo = &radeon_i2c_algo; 919 ret = i2c_add_adapter(&i2c->adapter); 920 if (ret) { 921 DRM_ERROR("Failed to register hw i2c %s\n", name); 922 goto out_free; 923 } 924 } else { 925 /* set the radeon bit adapter */ 926 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 927 "Radeon i2c bit bus %s", name); 928 i2c->adapter.algo_data = &i2c->algo.bit; 929 i2c->algo.bit.pre_xfer = pre_xfer; 930 i2c->algo.bit.post_xfer = post_xfer; 931 i2c->algo.bit.setsda = set_data; 932 i2c->algo.bit.setscl = set_clock; 933 i2c->algo.bit.getsda = get_data; 934 i2c->algo.bit.getscl = get_clock; 935 i2c->algo.bit.udelay = 20; 936 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always 937 * make this, 2 jiffies is a lot more reliable */ 938 i2c->algo.bit.timeout = 2; 939 i2c->algo.bit.data = i2c; 940 ret = i2c_bit_add_bus(&i2c->adapter); 941 if (ret) { 942 DRM_ERROR("Failed to register bit i2c %s\n", name); 943 goto out_free; 944 } 945 } 946 947 return i2c; 948 out_free: 949 kfree(i2c); 950 return NULL; 951 952 } 953 954 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 955 struct radeon_i2c_bus_rec *rec, 956 const char *name) 957 { 958 struct radeon_i2c_chan *i2c; 959 int ret; 960 961 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 962 if (i2c == NULL) 963 return NULL; 964 965 i2c->rec = *rec; 966 i2c->adapter.owner = THIS_MODULE; 967 i2c->adapter.class = I2C_CLASS_DDC; 968 i2c->dev = dev; 969 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 970 "Radeon aux bus %s", name); 971 i2c_set_adapdata(&i2c->adapter, i2c); 972 i2c->adapter.algo_data = &i2c->algo.dp; 973 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; 974 i2c->algo.dp.address = 0; 975 ret = i2c_dp_aux_add_bus(&i2c->adapter); 976 if (ret) { 977 DRM_INFO("Failed to register i2c %s\n", name); 978 goto out_free; 979 } 980 981 return i2c; 982 out_free: 983 kfree(i2c); 984 return NULL; 985 986 } 987 988 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 989 { 990 if (!i2c) 991 return; 992 i2c_del_adapter(&i2c->adapter); 993 kfree(i2c); 994 } 995 996 /* Add the default buses */ 997 void radeon_i2c_init(struct radeon_device *rdev) 998 { 999 if (rdev->is_atom_bios) 1000 radeon_atombios_i2c_init(rdev); 1001 else 1002 radeon_combios_i2c_init(rdev); 1003 } 1004 1005 /* remove all the buses */ 1006 void radeon_i2c_fini(struct radeon_device *rdev) 1007 { 1008 int i; 1009 1010 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1011 if (rdev->i2c_bus[i]) { 1012 radeon_i2c_destroy(rdev->i2c_bus[i]); 1013 rdev->i2c_bus[i] = NULL; 1014 } 1015 } 1016 } 1017 1018 /* Add additional buses */ 1019 void radeon_i2c_add(struct radeon_device *rdev, 1020 struct radeon_i2c_bus_rec *rec, 1021 const char *name) 1022 { 1023 struct drm_device *dev = rdev->ddev; 1024 int i; 1025 1026 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1027 if (!rdev->i2c_bus[i]) { 1028 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1029 return; 1030 } 1031 } 1032 } 1033 1034 /* looks up bus based on id */ 1035 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1036 struct radeon_i2c_bus_rec *i2c_bus) 1037 { 1038 int i; 1039 1040 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1041 if (rdev->i2c_bus[i] && 1042 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1043 return rdev->i2c_bus[i]; 1044 } 1045 } 1046 return NULL; 1047 } 1048 1049 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1050 { 1051 return NULL; 1052 } 1053 1054 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1055 u8 slave_addr, 1056 u8 addr, 1057 u8 *val) 1058 { 1059 u8 out_buf[2]; 1060 u8 in_buf[2]; 1061 struct i2c_msg msgs[] = { 1062 { 1063 .addr = slave_addr, 1064 .flags = 0, 1065 .len = 1, 1066 .buf = out_buf, 1067 }, 1068 { 1069 .addr = slave_addr, 1070 .flags = I2C_M_RD, 1071 .len = 1, 1072 .buf = in_buf, 1073 } 1074 }; 1075 1076 out_buf[0] = addr; 1077 out_buf[1] = 0; 1078 1079 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1080 *val = in_buf[0]; 1081 DRM_DEBUG("val = 0x%02x\n", *val); 1082 } else { 1083 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1084 addr, *val); 1085 } 1086 } 1087 1088 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1089 u8 slave_addr, 1090 u8 addr, 1091 u8 val) 1092 { 1093 uint8_t out_buf[2]; 1094 struct i2c_msg msg = { 1095 .addr = slave_addr, 1096 .flags = 0, 1097 .len = 2, 1098 .buf = out_buf, 1099 }; 1100 1101 out_buf[0] = addr; 1102 out_buf[1] = val; 1103 1104 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1105 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1106 addr, val); 1107 } 1108 1109 /* ddc router switching */ 1110 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1111 { 1112 u8 val; 1113 1114 if (!radeon_connector->router.ddc_valid) 1115 return; 1116 1117 if (!radeon_connector->router_bus) 1118 return; 1119 1120 radeon_i2c_get_byte(radeon_connector->router_bus, 1121 radeon_connector->router.i2c_addr, 1122 0x3, &val); 1123 val &= ~radeon_connector->router.ddc_mux_control_pin; 1124 radeon_i2c_put_byte(radeon_connector->router_bus, 1125 radeon_connector->router.i2c_addr, 1126 0x3, val); 1127 radeon_i2c_get_byte(radeon_connector->router_bus, 1128 radeon_connector->router.i2c_addr, 1129 0x1, &val); 1130 val &= ~radeon_connector->router.ddc_mux_control_pin; 1131 val |= radeon_connector->router.ddc_mux_state; 1132 radeon_i2c_put_byte(radeon_connector->router_bus, 1133 radeon_connector->router.i2c_addr, 1134 0x1, val); 1135 } 1136 1137 /* clock/data router switching */ 1138 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1139 { 1140 u8 val; 1141 1142 if (!radeon_connector->router.cd_valid) 1143 return; 1144 1145 if (!radeon_connector->router_bus) 1146 return; 1147 1148 radeon_i2c_get_byte(radeon_connector->router_bus, 1149 radeon_connector->router.i2c_addr, 1150 0x3, &val); 1151 val &= ~radeon_connector->router.cd_mux_control_pin; 1152 radeon_i2c_put_byte(radeon_connector->router_bus, 1153 radeon_connector->router.i2c_addr, 1154 0x3, val); 1155 radeon_i2c_get_byte(radeon_connector->router_bus, 1156 radeon_connector->router.i2c_addr, 1157 0x1, &val); 1158 val &= ~radeon_connector->router.cd_mux_control_pin; 1159 val |= radeon_connector->router.cd_mux_state; 1160 radeon_i2c_put_byte(radeon_connector->router_bus, 1161 radeon_connector->router.i2c_addr, 1162 0x1, val); 1163 } 1164 1165