1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 #include "atom.h" 30 31 /** 32 * radeon_ddc_probe 33 * 34 */ 35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool requires_extended_probe) 36 { 37 u8 out = 0x0; 38 u8 buf[8]; 39 int ret; 40 struct i2c_msg msgs[] = { 41 { 42 .addr = 0x50, 43 .flags = 0, 44 .len = 1, 45 .buf = &out, 46 }, 47 { 48 .addr = 0x50, 49 .flags = I2C_M_RD, 50 .len = 1, 51 .buf = buf, 52 } 53 }; 54 55 /* Read 8 bytes from i2c for extended probe of EDID header */ 56 if (requires_extended_probe) 57 msgs[1].len = 8; 58 59 /* on hw with routers, select right port */ 60 if (radeon_connector->router.ddc_valid) 61 radeon_router_select_ddc_port(radeon_connector); 62 63 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 64 if (ret != 2) 65 /* Couldn't find an accessible DDC on this connector */ 66 return false; 67 if (requires_extended_probe) { 68 /* Probe also for valid EDID header 69 * EDID header starts with: 70 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 71 * Only the first 6 bytes must be valid as 72 * drm_edid_block_valid() can fix the last 2 bytes */ 73 if (drm_edid_header_is_valid(buf) < 6) { 74 /* Couldn't find an accessible EDID on this 75 * connector */ 76 return false; 77 } 78 } 79 return true; 80 } 81 82 /* bit banging i2c */ 83 84 static int pre_xfer(struct i2c_adapter *i2c_adap) 85 { 86 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 87 struct radeon_device *rdev = i2c->dev->dev_private; 88 struct radeon_i2c_bus_rec *rec = &i2c->rec; 89 uint32_t temp; 90 91 /* RV410 appears to have a bug where the hw i2c in reset 92 * holds the i2c port in a bad state - switch hw i2c away before 93 * doing DDC - do this for all r200s/r300s/r400s for safety sake 94 */ 95 if (rec->hw_capable) { 96 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 97 u32 reg; 98 99 if (rdev->family >= CHIP_RV350) 100 reg = RADEON_GPIO_MONID; 101 else if ((rdev->family == CHIP_R300) || 102 (rdev->family == CHIP_R350)) 103 reg = RADEON_GPIO_DVI_DDC; 104 else 105 reg = RADEON_GPIO_CRT2_DDC; 106 107 mutex_lock(&rdev->dc_hw_i2c_mutex); 108 if (rec->a_clk_reg == reg) { 109 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 110 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 111 } else { 112 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 113 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 114 } 115 mutex_unlock(&rdev->dc_hw_i2c_mutex); 116 } 117 } 118 119 /* switch the pads to ddc mode */ 120 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 121 temp = RREG32(rec->mask_clk_reg); 122 temp &= ~(1 << 16); 123 WREG32(rec->mask_clk_reg, temp); 124 } 125 126 /* clear the output pin values */ 127 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 128 WREG32(rec->a_clk_reg, temp); 129 130 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 131 WREG32(rec->a_data_reg, temp); 132 133 /* set the pins to input */ 134 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 135 WREG32(rec->en_clk_reg, temp); 136 137 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 138 WREG32(rec->en_data_reg, temp); 139 140 /* mask the gpio pins for software use */ 141 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 142 WREG32(rec->mask_clk_reg, temp); 143 temp = RREG32(rec->mask_clk_reg); 144 145 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 146 WREG32(rec->mask_data_reg, temp); 147 temp = RREG32(rec->mask_data_reg); 148 149 return 0; 150 } 151 152 static void post_xfer(struct i2c_adapter *i2c_adap) 153 { 154 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 155 struct radeon_device *rdev = i2c->dev->dev_private; 156 struct radeon_i2c_bus_rec *rec = &i2c->rec; 157 uint32_t temp; 158 159 /* unmask the gpio pins for software use */ 160 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 161 WREG32(rec->mask_clk_reg, temp); 162 temp = RREG32(rec->mask_clk_reg); 163 164 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 165 WREG32(rec->mask_data_reg, temp); 166 temp = RREG32(rec->mask_data_reg); 167 } 168 169 static int get_clock(void *i2c_priv) 170 { 171 struct radeon_i2c_chan *i2c = i2c_priv; 172 struct radeon_device *rdev = i2c->dev->dev_private; 173 struct radeon_i2c_bus_rec *rec = &i2c->rec; 174 uint32_t val; 175 176 /* read the value off the pin */ 177 val = RREG32(rec->y_clk_reg); 178 val &= rec->y_clk_mask; 179 180 return (val != 0); 181 } 182 183 184 static int get_data(void *i2c_priv) 185 { 186 struct radeon_i2c_chan *i2c = i2c_priv; 187 struct radeon_device *rdev = i2c->dev->dev_private; 188 struct radeon_i2c_bus_rec *rec = &i2c->rec; 189 uint32_t val; 190 191 /* read the value off the pin */ 192 val = RREG32(rec->y_data_reg); 193 val &= rec->y_data_mask; 194 195 return (val != 0); 196 } 197 198 static void set_clock(void *i2c_priv, int clock) 199 { 200 struct radeon_i2c_chan *i2c = i2c_priv; 201 struct radeon_device *rdev = i2c->dev->dev_private; 202 struct radeon_i2c_bus_rec *rec = &i2c->rec; 203 uint32_t val; 204 205 /* set pin direction */ 206 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 207 val |= clock ? 0 : rec->en_clk_mask; 208 WREG32(rec->en_clk_reg, val); 209 } 210 211 static void set_data(void *i2c_priv, int data) 212 { 213 struct radeon_i2c_chan *i2c = i2c_priv; 214 struct radeon_device *rdev = i2c->dev->dev_private; 215 struct radeon_i2c_bus_rec *rec = &i2c->rec; 216 uint32_t val; 217 218 /* set pin direction */ 219 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 220 val |= data ? 0 : rec->en_data_mask; 221 WREG32(rec->en_data_reg, val); 222 } 223 224 /* hw i2c */ 225 226 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 227 { 228 u32 sclk = rdev->pm.current_sclk; 229 u32 prescale = 0; 230 u32 nm; 231 u8 n, m, loop; 232 int i2c_clock; 233 234 switch (rdev->family) { 235 case CHIP_R100: 236 case CHIP_RV100: 237 case CHIP_RS100: 238 case CHIP_RV200: 239 case CHIP_RS200: 240 case CHIP_R200: 241 case CHIP_RV250: 242 case CHIP_RS300: 243 case CHIP_RV280: 244 case CHIP_R300: 245 case CHIP_R350: 246 case CHIP_RV350: 247 i2c_clock = 60; 248 nm = (sclk * 10) / (i2c_clock * 4); 249 for (loop = 1; loop < 255; loop++) { 250 if ((nm / loop) < loop) 251 break; 252 } 253 n = loop - 1; 254 m = loop - 2; 255 prescale = m | (n << 8); 256 break; 257 case CHIP_RV380: 258 case CHIP_RS400: 259 case CHIP_RS480: 260 case CHIP_R420: 261 case CHIP_R423: 262 case CHIP_RV410: 263 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 264 break; 265 case CHIP_RS600: 266 case CHIP_RS690: 267 case CHIP_RS740: 268 /* todo */ 269 break; 270 case CHIP_RV515: 271 case CHIP_R520: 272 case CHIP_RV530: 273 case CHIP_RV560: 274 case CHIP_RV570: 275 case CHIP_R580: 276 i2c_clock = 50; 277 if (rdev->family == CHIP_R520) 278 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 279 else 280 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 281 break; 282 case CHIP_R600: 283 case CHIP_RV610: 284 case CHIP_RV630: 285 case CHIP_RV670: 286 /* todo */ 287 break; 288 case CHIP_RV620: 289 case CHIP_RV635: 290 case CHIP_RS780: 291 case CHIP_RS880: 292 case CHIP_RV770: 293 case CHIP_RV730: 294 case CHIP_RV710: 295 case CHIP_RV740: 296 /* todo */ 297 break; 298 case CHIP_CEDAR: 299 case CHIP_REDWOOD: 300 case CHIP_JUNIPER: 301 case CHIP_CYPRESS: 302 case CHIP_HEMLOCK: 303 /* todo */ 304 break; 305 default: 306 DRM_ERROR("i2c: unhandled radeon chip\n"); 307 break; 308 } 309 return prescale; 310 } 311 312 313 /* hw i2c engine for r1xx-4xx hardware 314 * hw can buffer up to 15 bytes 315 */ 316 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 317 struct i2c_msg *msgs, int num) 318 { 319 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 320 struct radeon_device *rdev = i2c->dev->dev_private; 321 struct radeon_i2c_bus_rec *rec = &i2c->rec; 322 struct i2c_msg *p; 323 int i, j, k, ret = num; 324 u32 prescale; 325 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 326 u32 tmp, reg; 327 328 mutex_lock(&rdev->dc_hw_i2c_mutex); 329 /* take the pm lock since we need a constant sclk */ 330 mutex_lock(&rdev->pm.mutex); 331 332 prescale = radeon_get_i2c_prescale(rdev); 333 334 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 335 RADEON_I2C_DRIVE_EN | 336 RADEON_I2C_START | 337 RADEON_I2C_STOP | 338 RADEON_I2C_GO); 339 340 if (rdev->is_atom_bios) { 341 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 342 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 343 } 344 345 if (rec->mm_i2c) { 346 i2c_cntl_0 = RADEON_I2C_CNTL_0; 347 i2c_cntl_1 = RADEON_I2C_CNTL_1; 348 i2c_data = RADEON_I2C_DATA; 349 } else { 350 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 351 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 352 i2c_data = RADEON_DVI_I2C_DATA; 353 354 switch (rdev->family) { 355 case CHIP_R100: 356 case CHIP_RV100: 357 case CHIP_RS100: 358 case CHIP_RV200: 359 case CHIP_RS200: 360 case CHIP_RS300: 361 switch (rec->mask_clk_reg) { 362 case RADEON_GPIO_DVI_DDC: 363 /* no gpio select bit */ 364 break; 365 default: 366 DRM_ERROR("gpio not supported with hw i2c\n"); 367 ret = -EINVAL; 368 goto done; 369 } 370 break; 371 case CHIP_R200: 372 /* only bit 4 on r200 */ 373 switch (rec->mask_clk_reg) { 374 case RADEON_GPIO_DVI_DDC: 375 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 376 break; 377 case RADEON_GPIO_MONID: 378 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 379 break; 380 default: 381 DRM_ERROR("gpio not supported with hw i2c\n"); 382 ret = -EINVAL; 383 goto done; 384 } 385 break; 386 case CHIP_RV250: 387 case CHIP_RV280: 388 /* bits 3 and 4 */ 389 switch (rec->mask_clk_reg) { 390 case RADEON_GPIO_DVI_DDC: 391 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 392 break; 393 case RADEON_GPIO_VGA_DDC: 394 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 395 break; 396 case RADEON_GPIO_CRT2_DDC: 397 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 398 break; 399 default: 400 DRM_ERROR("gpio not supported with hw i2c\n"); 401 ret = -EINVAL; 402 goto done; 403 } 404 break; 405 case CHIP_R300: 406 case CHIP_R350: 407 /* only bit 4 on r300/r350 */ 408 switch (rec->mask_clk_reg) { 409 case RADEON_GPIO_VGA_DDC: 410 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 411 break; 412 case RADEON_GPIO_DVI_DDC: 413 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 414 break; 415 default: 416 DRM_ERROR("gpio not supported with hw i2c\n"); 417 ret = -EINVAL; 418 goto done; 419 } 420 break; 421 case CHIP_RV350: 422 case CHIP_RV380: 423 case CHIP_R420: 424 case CHIP_R423: 425 case CHIP_RV410: 426 case CHIP_RS400: 427 case CHIP_RS480: 428 /* bits 3 and 4 */ 429 switch (rec->mask_clk_reg) { 430 case RADEON_GPIO_VGA_DDC: 431 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 432 break; 433 case RADEON_GPIO_DVI_DDC: 434 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 435 break; 436 case RADEON_GPIO_MONID: 437 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 438 break; 439 default: 440 DRM_ERROR("gpio not supported with hw i2c\n"); 441 ret = -EINVAL; 442 goto done; 443 } 444 break; 445 default: 446 DRM_ERROR("unsupported asic\n"); 447 ret = -EINVAL; 448 goto done; 449 break; 450 } 451 } 452 453 /* check for bus probe */ 454 p = &msgs[0]; 455 if ((num == 1) && (p->len == 0)) { 456 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 457 RADEON_I2C_NACK | 458 RADEON_I2C_HALT | 459 RADEON_I2C_SOFT_RST)); 460 WREG32(i2c_data, (p->addr << 1) & 0xff); 461 WREG32(i2c_data, 0); 462 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 463 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 464 RADEON_I2C_EN | 465 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 466 WREG32(i2c_cntl_0, reg); 467 for (k = 0; k < 32; k++) { 468 udelay(10); 469 tmp = RREG32(i2c_cntl_0); 470 if (tmp & RADEON_I2C_GO) 471 continue; 472 tmp = RREG32(i2c_cntl_0); 473 if (tmp & RADEON_I2C_DONE) 474 break; 475 else { 476 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 477 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 478 ret = -EIO; 479 goto done; 480 } 481 } 482 goto done; 483 } 484 485 for (i = 0; i < num; i++) { 486 p = &msgs[i]; 487 for (j = 0; j < p->len; j++) { 488 if (p->flags & I2C_M_RD) { 489 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 490 RADEON_I2C_NACK | 491 RADEON_I2C_HALT | 492 RADEON_I2C_SOFT_RST)); 493 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 494 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 495 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 496 RADEON_I2C_EN | 497 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 498 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 499 for (k = 0; k < 32; k++) { 500 udelay(10); 501 tmp = RREG32(i2c_cntl_0); 502 if (tmp & RADEON_I2C_GO) 503 continue; 504 tmp = RREG32(i2c_cntl_0); 505 if (tmp & RADEON_I2C_DONE) 506 break; 507 else { 508 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 509 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 510 ret = -EIO; 511 goto done; 512 } 513 } 514 p->buf[j] = RREG32(i2c_data) & 0xff; 515 } else { 516 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 517 RADEON_I2C_NACK | 518 RADEON_I2C_HALT | 519 RADEON_I2C_SOFT_RST)); 520 WREG32(i2c_data, (p->addr << 1) & 0xff); 521 WREG32(i2c_data, p->buf[j]); 522 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 523 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 524 RADEON_I2C_EN | 525 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 526 WREG32(i2c_cntl_0, reg); 527 for (k = 0; k < 32; k++) { 528 udelay(10); 529 tmp = RREG32(i2c_cntl_0); 530 if (tmp & RADEON_I2C_GO) 531 continue; 532 tmp = RREG32(i2c_cntl_0); 533 if (tmp & RADEON_I2C_DONE) 534 break; 535 else { 536 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 537 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 538 ret = -EIO; 539 goto done; 540 } 541 } 542 } 543 } 544 } 545 546 done: 547 WREG32(i2c_cntl_0, 0); 548 WREG32(i2c_cntl_1, 0); 549 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 550 RADEON_I2C_NACK | 551 RADEON_I2C_HALT | 552 RADEON_I2C_SOFT_RST)); 553 554 if (rdev->is_atom_bios) { 555 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 556 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 557 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 558 } 559 560 mutex_unlock(&rdev->pm.mutex); 561 mutex_unlock(&rdev->dc_hw_i2c_mutex); 562 563 return ret; 564 } 565 566 /* hw i2c engine for r5xx hardware 567 * hw can buffer up to 15 bytes 568 */ 569 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 570 struct i2c_msg *msgs, int num) 571 { 572 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 573 struct radeon_device *rdev = i2c->dev->dev_private; 574 struct radeon_i2c_bus_rec *rec = &i2c->rec; 575 struct i2c_msg *p; 576 int i, j, remaining, current_count, buffer_offset, ret = num; 577 u32 prescale; 578 u32 tmp, reg; 579 u32 saved1, saved2; 580 581 mutex_lock(&rdev->dc_hw_i2c_mutex); 582 /* take the pm lock since we need a constant sclk */ 583 mutex_lock(&rdev->pm.mutex); 584 585 prescale = radeon_get_i2c_prescale(rdev); 586 587 /* clear gpio mask bits */ 588 tmp = RREG32(rec->mask_clk_reg); 589 tmp &= ~rec->mask_clk_mask; 590 WREG32(rec->mask_clk_reg, tmp); 591 tmp = RREG32(rec->mask_clk_reg); 592 593 tmp = RREG32(rec->mask_data_reg); 594 tmp &= ~rec->mask_data_mask; 595 WREG32(rec->mask_data_reg, tmp); 596 tmp = RREG32(rec->mask_data_reg); 597 598 /* clear pin values */ 599 tmp = RREG32(rec->a_clk_reg); 600 tmp &= ~rec->a_clk_mask; 601 WREG32(rec->a_clk_reg, tmp); 602 tmp = RREG32(rec->a_clk_reg); 603 604 tmp = RREG32(rec->a_data_reg); 605 tmp &= ~rec->a_data_mask; 606 WREG32(rec->a_data_reg, tmp); 607 tmp = RREG32(rec->a_data_reg); 608 609 /* set the pins to input */ 610 tmp = RREG32(rec->en_clk_reg); 611 tmp &= ~rec->en_clk_mask; 612 WREG32(rec->en_clk_reg, tmp); 613 tmp = RREG32(rec->en_clk_reg); 614 615 tmp = RREG32(rec->en_data_reg); 616 tmp &= ~rec->en_data_mask; 617 WREG32(rec->en_data_reg, tmp); 618 tmp = RREG32(rec->en_data_reg); 619 620 /* */ 621 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 622 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 623 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 624 saved2 = RREG32(0x494); 625 WREG32(0x494, saved2 | 0x1); 626 627 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 628 for (i = 0; i < 50; i++) { 629 udelay(1); 630 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 631 break; 632 } 633 if (i == 50) { 634 DRM_ERROR("failed to get i2c bus\n"); 635 ret = -EBUSY; 636 goto done; 637 } 638 639 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 640 switch (rec->mask_clk_reg) { 641 case AVIVO_DC_GPIO_DDC1_MASK: 642 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 643 break; 644 case AVIVO_DC_GPIO_DDC2_MASK: 645 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 646 break; 647 case AVIVO_DC_GPIO_DDC3_MASK: 648 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 649 break; 650 default: 651 DRM_ERROR("gpio not supported with hw i2c\n"); 652 ret = -EINVAL; 653 goto done; 654 } 655 656 /* check for bus probe */ 657 p = &msgs[0]; 658 if ((num == 1) && (p->len == 0)) { 659 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 660 AVIVO_DC_I2C_NACK | 661 AVIVO_DC_I2C_HALT)); 662 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 663 udelay(1); 664 WREG32(AVIVO_DC_I2C_RESET, 0); 665 666 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 667 WREG32(AVIVO_DC_I2C_DATA, 0); 668 669 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 670 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 671 AVIVO_DC_I2C_DATA_COUNT(1) | 672 (prescale << 16))); 673 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 674 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 675 for (j = 0; j < 200; j++) { 676 udelay(50); 677 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 678 if (tmp & AVIVO_DC_I2C_GO) 679 continue; 680 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 681 if (tmp & AVIVO_DC_I2C_DONE) 682 break; 683 else { 684 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 685 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 686 ret = -EIO; 687 goto done; 688 } 689 } 690 goto done; 691 } 692 693 for (i = 0; i < num; i++) { 694 p = &msgs[i]; 695 remaining = p->len; 696 buffer_offset = 0; 697 if (p->flags & I2C_M_RD) { 698 while (remaining) { 699 if (remaining > 15) 700 current_count = 15; 701 else 702 current_count = remaining; 703 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 704 AVIVO_DC_I2C_NACK | 705 AVIVO_DC_I2C_HALT)); 706 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 707 udelay(1); 708 WREG32(AVIVO_DC_I2C_RESET, 0); 709 710 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 711 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 712 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 713 AVIVO_DC_I2C_DATA_COUNT(current_count) | 714 (prescale << 16))); 715 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 716 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 717 for (j = 0; j < 200; j++) { 718 udelay(50); 719 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 720 if (tmp & AVIVO_DC_I2C_GO) 721 continue; 722 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 723 if (tmp & AVIVO_DC_I2C_DONE) 724 break; 725 else { 726 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 727 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 728 ret = -EIO; 729 goto done; 730 } 731 } 732 for (j = 0; j < current_count; j++) 733 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 734 remaining -= current_count; 735 buffer_offset += current_count; 736 } 737 } else { 738 while (remaining) { 739 if (remaining > 15) 740 current_count = 15; 741 else 742 current_count = remaining; 743 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 744 AVIVO_DC_I2C_NACK | 745 AVIVO_DC_I2C_HALT)); 746 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 747 udelay(1); 748 WREG32(AVIVO_DC_I2C_RESET, 0); 749 750 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 751 for (j = 0; j < current_count; j++) 752 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 753 754 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 755 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 756 AVIVO_DC_I2C_DATA_COUNT(current_count) | 757 (prescale << 16))); 758 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 759 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 760 for (j = 0; j < 200; j++) { 761 udelay(50); 762 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 763 if (tmp & AVIVO_DC_I2C_GO) 764 continue; 765 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 766 if (tmp & AVIVO_DC_I2C_DONE) 767 break; 768 else { 769 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 770 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 771 ret = -EIO; 772 goto done; 773 } 774 } 775 remaining -= current_count; 776 buffer_offset += current_count; 777 } 778 } 779 } 780 781 done: 782 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 783 AVIVO_DC_I2C_NACK | 784 AVIVO_DC_I2C_HALT)); 785 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 786 udelay(1); 787 WREG32(AVIVO_DC_I2C_RESET, 0); 788 789 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 790 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 791 WREG32(0x494, saved2); 792 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 793 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 794 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 795 796 mutex_unlock(&rdev->pm.mutex); 797 mutex_unlock(&rdev->dc_hw_i2c_mutex); 798 799 return ret; 800 } 801 802 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 803 struct i2c_msg *msgs, int num) 804 { 805 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 806 struct radeon_device *rdev = i2c->dev->dev_private; 807 struct radeon_i2c_bus_rec *rec = &i2c->rec; 808 int ret = 0; 809 810 switch (rdev->family) { 811 case CHIP_R100: 812 case CHIP_RV100: 813 case CHIP_RS100: 814 case CHIP_RV200: 815 case CHIP_RS200: 816 case CHIP_R200: 817 case CHIP_RV250: 818 case CHIP_RS300: 819 case CHIP_RV280: 820 case CHIP_R300: 821 case CHIP_R350: 822 case CHIP_RV350: 823 case CHIP_RV380: 824 case CHIP_R420: 825 case CHIP_R423: 826 case CHIP_RV410: 827 case CHIP_RS400: 828 case CHIP_RS480: 829 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 830 break; 831 case CHIP_RS600: 832 case CHIP_RS690: 833 case CHIP_RS740: 834 /* XXX fill in hw i2c implementation */ 835 break; 836 case CHIP_RV515: 837 case CHIP_R520: 838 case CHIP_RV530: 839 case CHIP_RV560: 840 case CHIP_RV570: 841 case CHIP_R580: 842 if (rec->mm_i2c) 843 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 844 else 845 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 846 break; 847 case CHIP_R600: 848 case CHIP_RV610: 849 case CHIP_RV630: 850 case CHIP_RV670: 851 /* XXX fill in hw i2c implementation */ 852 break; 853 case CHIP_RV620: 854 case CHIP_RV635: 855 case CHIP_RS780: 856 case CHIP_RS880: 857 case CHIP_RV770: 858 case CHIP_RV730: 859 case CHIP_RV710: 860 case CHIP_RV740: 861 /* XXX fill in hw i2c implementation */ 862 break; 863 case CHIP_CEDAR: 864 case CHIP_REDWOOD: 865 case CHIP_JUNIPER: 866 case CHIP_CYPRESS: 867 case CHIP_HEMLOCK: 868 /* XXX fill in hw i2c implementation */ 869 break; 870 default: 871 DRM_ERROR("i2c: unhandled radeon chip\n"); 872 ret = -EIO; 873 break; 874 } 875 876 return ret; 877 } 878 879 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 880 { 881 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 882 } 883 884 static const struct i2c_algorithm radeon_i2c_algo = { 885 .master_xfer = radeon_hw_i2c_xfer, 886 .functionality = radeon_hw_i2c_func, 887 }; 888 889 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 890 struct radeon_i2c_bus_rec *rec, 891 const char *name) 892 { 893 struct radeon_device *rdev = dev->dev_private; 894 struct radeon_i2c_chan *i2c; 895 int ret; 896 897 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 898 if (i2c == NULL) 899 return NULL; 900 901 i2c->rec = *rec; 902 i2c->adapter.owner = THIS_MODULE; 903 i2c->adapter.class = I2C_CLASS_DDC; 904 i2c->dev = dev; 905 i2c_set_adapdata(&i2c->adapter, i2c); 906 if (rec->mm_i2c || 907 (rec->hw_capable && 908 radeon_hw_i2c && 909 ((rdev->family <= CHIP_RS480) || 910 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 911 /* set the radeon hw i2c adapter */ 912 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 913 "Radeon i2c hw bus %s", name); 914 i2c->adapter.algo = &radeon_i2c_algo; 915 ret = i2c_add_adapter(&i2c->adapter); 916 if (ret) { 917 DRM_ERROR("Failed to register hw i2c %s\n", name); 918 goto out_free; 919 } 920 } else { 921 /* set the radeon bit adapter */ 922 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 923 "Radeon i2c bit bus %s", name); 924 i2c->adapter.algo_data = &i2c->algo.bit; 925 i2c->algo.bit.pre_xfer = pre_xfer; 926 i2c->algo.bit.post_xfer = post_xfer; 927 i2c->algo.bit.setsda = set_data; 928 i2c->algo.bit.setscl = set_clock; 929 i2c->algo.bit.getsda = get_data; 930 i2c->algo.bit.getscl = get_clock; 931 i2c->algo.bit.udelay = 20; 932 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always 933 * make this, 2 jiffies is a lot more reliable */ 934 i2c->algo.bit.timeout = 2; 935 i2c->algo.bit.data = i2c; 936 ret = i2c_bit_add_bus(&i2c->adapter); 937 if (ret) { 938 DRM_ERROR("Failed to register bit i2c %s\n", name); 939 goto out_free; 940 } 941 } 942 943 return i2c; 944 out_free: 945 kfree(i2c); 946 return NULL; 947 948 } 949 950 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 951 struct radeon_i2c_bus_rec *rec, 952 const char *name) 953 { 954 struct radeon_i2c_chan *i2c; 955 int ret; 956 957 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 958 if (i2c == NULL) 959 return NULL; 960 961 i2c->rec = *rec; 962 i2c->adapter.owner = THIS_MODULE; 963 i2c->adapter.class = I2C_CLASS_DDC; 964 i2c->dev = dev; 965 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 966 "Radeon aux bus %s", name); 967 i2c_set_adapdata(&i2c->adapter, i2c); 968 i2c->adapter.algo_data = &i2c->algo.dp; 969 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; 970 i2c->algo.dp.address = 0; 971 ret = i2c_dp_aux_add_bus(&i2c->adapter); 972 if (ret) { 973 DRM_INFO("Failed to register i2c %s\n", name); 974 goto out_free; 975 } 976 977 return i2c; 978 out_free: 979 kfree(i2c); 980 return NULL; 981 982 } 983 984 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 985 { 986 if (!i2c) 987 return; 988 i2c_del_adapter(&i2c->adapter); 989 kfree(i2c); 990 } 991 992 /* Add the default buses */ 993 void radeon_i2c_init(struct radeon_device *rdev) 994 { 995 if (rdev->is_atom_bios) 996 radeon_atombios_i2c_init(rdev); 997 else 998 radeon_combios_i2c_init(rdev); 999 } 1000 1001 /* remove all the buses */ 1002 void radeon_i2c_fini(struct radeon_device *rdev) 1003 { 1004 int i; 1005 1006 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1007 if (rdev->i2c_bus[i]) { 1008 radeon_i2c_destroy(rdev->i2c_bus[i]); 1009 rdev->i2c_bus[i] = NULL; 1010 } 1011 } 1012 } 1013 1014 /* Add additional buses */ 1015 void radeon_i2c_add(struct radeon_device *rdev, 1016 struct radeon_i2c_bus_rec *rec, 1017 const char *name) 1018 { 1019 struct drm_device *dev = rdev->ddev; 1020 int i; 1021 1022 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1023 if (!rdev->i2c_bus[i]) { 1024 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1025 return; 1026 } 1027 } 1028 } 1029 1030 /* looks up bus based on id */ 1031 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1032 struct radeon_i2c_bus_rec *i2c_bus) 1033 { 1034 int i; 1035 1036 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1037 if (rdev->i2c_bus[i] && 1038 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1039 return rdev->i2c_bus[i]; 1040 } 1041 } 1042 return NULL; 1043 } 1044 1045 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1046 { 1047 return NULL; 1048 } 1049 1050 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1051 u8 slave_addr, 1052 u8 addr, 1053 u8 *val) 1054 { 1055 u8 out_buf[2]; 1056 u8 in_buf[2]; 1057 struct i2c_msg msgs[] = { 1058 { 1059 .addr = slave_addr, 1060 .flags = 0, 1061 .len = 1, 1062 .buf = out_buf, 1063 }, 1064 { 1065 .addr = slave_addr, 1066 .flags = I2C_M_RD, 1067 .len = 1, 1068 .buf = in_buf, 1069 } 1070 }; 1071 1072 out_buf[0] = addr; 1073 out_buf[1] = 0; 1074 1075 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1076 *val = in_buf[0]; 1077 DRM_DEBUG("val = 0x%02x\n", *val); 1078 } else { 1079 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1080 addr, *val); 1081 } 1082 } 1083 1084 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1085 u8 slave_addr, 1086 u8 addr, 1087 u8 val) 1088 { 1089 uint8_t out_buf[2]; 1090 struct i2c_msg msg = { 1091 .addr = slave_addr, 1092 .flags = 0, 1093 .len = 2, 1094 .buf = out_buf, 1095 }; 1096 1097 out_buf[0] = addr; 1098 out_buf[1] = val; 1099 1100 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1101 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1102 addr, val); 1103 } 1104 1105 /* ddc router switching */ 1106 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1107 { 1108 u8 val; 1109 1110 if (!radeon_connector->router.ddc_valid) 1111 return; 1112 1113 if (!radeon_connector->router_bus) 1114 return; 1115 1116 radeon_i2c_get_byte(radeon_connector->router_bus, 1117 radeon_connector->router.i2c_addr, 1118 0x3, &val); 1119 val &= ~radeon_connector->router.ddc_mux_control_pin; 1120 radeon_i2c_put_byte(radeon_connector->router_bus, 1121 radeon_connector->router.i2c_addr, 1122 0x3, val); 1123 radeon_i2c_get_byte(radeon_connector->router_bus, 1124 radeon_connector->router.i2c_addr, 1125 0x1, &val); 1126 val &= ~radeon_connector->router.ddc_mux_control_pin; 1127 val |= radeon_connector->router.ddc_mux_state; 1128 radeon_i2c_put_byte(radeon_connector->router_bus, 1129 radeon_connector->router.i2c_addr, 1130 0x1, val); 1131 } 1132 1133 /* clock/data router switching */ 1134 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1135 { 1136 u8 val; 1137 1138 if (!radeon_connector->router.cd_valid) 1139 return; 1140 1141 if (!radeon_connector->router_bus) 1142 return; 1143 1144 radeon_i2c_get_byte(radeon_connector->router_bus, 1145 radeon_connector->router.i2c_addr, 1146 0x3, &val); 1147 val &= ~radeon_connector->router.cd_mux_control_pin; 1148 radeon_i2c_put_byte(radeon_connector->router_bus, 1149 radeon_connector->router.i2c_addr, 1150 0x3, val); 1151 radeon_i2c_get_byte(radeon_connector->router_bus, 1152 radeon_connector->router.i2c_addr, 1153 0x1, &val); 1154 val &= ~radeon_connector->router.cd_mux_control_pin; 1155 val |= radeon_connector->router.cd_mux_state; 1156 radeon_i2c_put_byte(radeon_connector->router_bus, 1157 radeon_connector->router.i2c_addr, 1158 0x1, val); 1159 } 1160 1161