1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 43 struct drm_encoder *clone_encoder; 44 uint32_t index_mask = 0; 45 int count; 46 47 /* DIG routing gets problematic */ 48 if (rdev->family >= CHIP_R600) 49 return index_mask; 50 /* LVDS/TV are too wacky */ 51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 52 return index_mask; 53 /* DVO requires 2x ppll clocks depending on tmds chip */ 54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) 55 return index_mask; 56 57 count = -1; 58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { 59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); 60 count++; 61 62 if (clone_encoder == encoder) 63 continue; 64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) 65 continue; 66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) 67 continue; 68 else 69 index_mask |= (1 << count); 70 } 71 return index_mask; 72 } 73 74 void radeon_setup_encoder_clones(struct drm_device *dev) 75 { 76 struct drm_encoder *encoder; 77 78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 79 encoder->possible_clones = radeon_encoder_clones(encoder); 80 } 81 } 82 83 uint32_t 84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 85 { 86 struct radeon_device *rdev = dev->dev_private; 87 uint32_t ret = 0; 88 89 switch (supported_device) { 90 case ATOM_DEVICE_CRT1_SUPPORT: 91 case ATOM_DEVICE_TV1_SUPPORT: 92 case ATOM_DEVICE_TV2_SUPPORT: 93 case ATOM_DEVICE_CRT2_SUPPORT: 94 case ATOM_DEVICE_CV_SUPPORT: 95 switch (dac) { 96 case 1: /* dac a */ 97 if ((rdev->family == CHIP_RS300) || 98 (rdev->family == CHIP_RS400) || 99 (rdev->family == CHIP_RS480)) 100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 101 else if (ASIC_IS_AVIVO(rdev)) 102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 103 else 104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; 105 break; 106 case 2: /* dac b */ 107 if (ASIC_IS_AVIVO(rdev)) 108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 109 else { 110 /*if (rdev->family == CHIP_R200) 111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 112 else*/ 113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 114 } 115 break; 116 case 3: /* external dac */ 117 if (ASIC_IS_AVIVO(rdev)) 118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 119 else 120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 121 break; 122 } 123 break; 124 case ATOM_DEVICE_LCD1_SUPPORT: 125 if (ASIC_IS_AVIVO(rdev)) 126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 127 else 128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; 129 break; 130 case ATOM_DEVICE_DFP1_SUPPORT: 131 if ((rdev->family == CHIP_RS300) || 132 (rdev->family == CHIP_RS400) || 133 (rdev->family == CHIP_RS480)) 134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 135 else if (ASIC_IS_AVIVO(rdev)) 136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 137 else 138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; 139 break; 140 case ATOM_DEVICE_LCD2_SUPPORT: 141 case ATOM_DEVICE_DFP2_SUPPORT: 142 if ((rdev->family == CHIP_RS600) || 143 (rdev->family == CHIP_RS690) || 144 (rdev->family == CHIP_RS740)) 145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI; 146 else if (ASIC_IS_AVIVO(rdev)) 147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 148 else 149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 150 break; 151 case ATOM_DEVICE_DFP3_SUPPORT: 152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 153 break; 154 } 155 156 return ret; 157 } 158 159 void 160 radeon_link_encoder_connector(struct drm_device *dev) 161 { 162 struct drm_connector *connector; 163 struct radeon_connector *radeon_connector; 164 struct drm_encoder *encoder; 165 struct radeon_encoder *radeon_encoder; 166 167 /* walk the list and link encoders to connectors */ 168 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 169 radeon_connector = to_radeon_connector(connector); 170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 171 radeon_encoder = to_radeon_encoder(encoder); 172 if (radeon_encoder->devices & radeon_connector->devices) 173 drm_mode_connector_attach_encoder(connector, encoder); 174 } 175 } 176 } 177 178 void radeon_encoder_set_active_device(struct drm_encoder *encoder) 179 { 180 struct drm_device *dev = encoder->dev; 181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 182 struct drm_connector *connector; 183 184 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 185 if (connector->encoder == encoder) { 186 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 187 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; 188 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", 189 radeon_encoder->active_device, radeon_encoder->devices, 190 radeon_connector->devices, encoder->encoder_type); 191 } 192 } 193 } 194 195 static struct drm_connector * 196 radeon_get_connector_for_encoder(struct drm_encoder *encoder) 197 { 198 struct drm_device *dev = encoder->dev; 199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 200 struct drm_connector *connector; 201 struct radeon_connector *radeon_connector; 202 203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 204 radeon_connector = to_radeon_connector(connector); 205 if (radeon_encoder->devices & radeon_connector->devices) 206 return connector; 207 } 208 return NULL; 209 } 210 211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 212 struct drm_display_mode *mode, 213 struct drm_display_mode *adjusted_mode) 214 { 215 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 216 struct drm_device *dev = encoder->dev; 217 struct radeon_device *rdev = dev->dev_private; 218 219 /* set the active encoder to connector routing */ 220 radeon_encoder_set_active_device(encoder); 221 drm_mode_set_crtcinfo(adjusted_mode, 0); 222 223 /* hw bug */ 224 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 225 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 226 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 227 228 /* get the native mode for LVDS */ 229 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 230 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 231 int mode_id = adjusted_mode->base.id; 232 *adjusted_mode = *native_mode; 233 if (!ASIC_IS_AVIVO(rdev)) { 234 adjusted_mode->hdisplay = mode->hdisplay; 235 adjusted_mode->vdisplay = mode->vdisplay; 236 adjusted_mode->crtc_hdisplay = mode->hdisplay; 237 adjusted_mode->crtc_vdisplay = mode->vdisplay; 238 } 239 adjusted_mode->base.id = mode_id; 240 } 241 242 /* get the native mode for TV */ 243 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 244 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 245 if (tv_dac) { 246 if (tv_dac->tv_std == TV_STD_NTSC || 247 tv_dac->tv_std == TV_STD_NTSC_J || 248 tv_dac->tv_std == TV_STD_PAL_M) 249 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 250 else 251 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 252 } 253 } 254 255 if (ASIC_IS_DCE3(rdev) && 256 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { 257 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 258 radeon_dp_set_link_config(connector, mode); 259 } 260 261 return true; 262 } 263 264 static void 265 atombios_dac_setup(struct drm_encoder *encoder, int action) 266 { 267 struct drm_device *dev = encoder->dev; 268 struct radeon_device *rdev = dev->dev_private; 269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 270 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 271 int index = 0, num = 0; 272 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 273 enum radeon_tv_std tv_std = TV_STD_NTSC; 274 275 if (dac_info->tv_std) 276 tv_std = dac_info->tv_std; 277 278 memset(&args, 0, sizeof(args)); 279 280 switch (radeon_encoder->encoder_id) { 281 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 282 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 283 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 284 num = 1; 285 break; 286 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 287 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 288 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 289 num = 2; 290 break; 291 } 292 293 args.ucAction = action; 294 295 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 296 args.ucDacStandard = ATOM_DAC1_PS2; 297 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 298 args.ucDacStandard = ATOM_DAC1_CV; 299 else { 300 switch (tv_std) { 301 case TV_STD_PAL: 302 case TV_STD_PAL_M: 303 case TV_STD_SCART_PAL: 304 case TV_STD_SECAM: 305 case TV_STD_PAL_CN: 306 args.ucDacStandard = ATOM_DAC1_PAL; 307 break; 308 case TV_STD_NTSC: 309 case TV_STD_NTSC_J: 310 case TV_STD_PAL_60: 311 default: 312 args.ucDacStandard = ATOM_DAC1_NTSC; 313 break; 314 } 315 } 316 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 317 318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 319 320 } 321 322 static void 323 atombios_tv_setup(struct drm_encoder *encoder, int action) 324 { 325 struct drm_device *dev = encoder->dev; 326 struct radeon_device *rdev = dev->dev_private; 327 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 328 TV_ENCODER_CONTROL_PS_ALLOCATION args; 329 int index = 0; 330 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 331 enum radeon_tv_std tv_std = TV_STD_NTSC; 332 333 if (dac_info->tv_std) 334 tv_std = dac_info->tv_std; 335 336 memset(&args, 0, sizeof(args)); 337 338 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 339 340 args.sTVEncoder.ucAction = action; 341 342 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 343 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 344 else { 345 switch (tv_std) { 346 case TV_STD_NTSC: 347 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 348 break; 349 case TV_STD_PAL: 350 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 351 break; 352 case TV_STD_PAL_M: 353 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 354 break; 355 case TV_STD_PAL_60: 356 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 357 break; 358 case TV_STD_NTSC_J: 359 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 360 break; 361 case TV_STD_SCART_PAL: 362 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 363 break; 364 case TV_STD_SECAM: 365 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 366 break; 367 case TV_STD_PAL_CN: 368 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 369 break; 370 default: 371 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 372 break; 373 } 374 } 375 376 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 377 378 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 379 380 } 381 382 void 383 atombios_external_tmds_setup(struct drm_encoder *encoder, int action) 384 { 385 struct drm_device *dev = encoder->dev; 386 struct radeon_device *rdev = dev->dev_private; 387 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 388 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; 389 int index = 0; 390 391 memset(&args, 0, sizeof(args)); 392 393 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 394 395 args.sXTmdsEncoder.ucEnable = action; 396 397 if (radeon_encoder->pixel_clock > 165000) 398 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; 399 400 /*if (pScrn->rgbBits == 8)*/ 401 args.sXTmdsEncoder.ucMisc |= (1 << 1); 402 403 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 404 405 } 406 407 static void 408 atombios_ddia_setup(struct drm_encoder *encoder, int action) 409 { 410 struct drm_device *dev = encoder->dev; 411 struct radeon_device *rdev = dev->dev_private; 412 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 413 DVO_ENCODER_CONTROL_PS_ALLOCATION args; 414 int index = 0; 415 416 memset(&args, 0, sizeof(args)); 417 418 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 419 420 args.sDVOEncoder.ucAction = action; 421 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 422 423 if (radeon_encoder->pixel_clock > 165000) 424 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; 425 426 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 427 428 } 429 430 union lvds_encoder_control { 431 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 432 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 433 }; 434 435 void 436 atombios_digital_setup(struct drm_encoder *encoder, int action) 437 { 438 struct drm_device *dev = encoder->dev; 439 struct radeon_device *rdev = dev->dev_private; 440 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 441 union lvds_encoder_control args; 442 int index = 0; 443 int hdmi_detected = 0; 444 uint8_t frev, crev; 445 struct radeon_encoder_atom_dig *dig; 446 struct drm_connector *connector; 447 struct radeon_connector *radeon_connector; 448 struct radeon_connector_atom_dig *dig_connector; 449 450 connector = radeon_get_connector_for_encoder(encoder); 451 if (!connector) 452 return; 453 454 radeon_connector = to_radeon_connector(connector); 455 456 if (!radeon_encoder->enc_priv) 457 return; 458 459 dig = radeon_encoder->enc_priv; 460 461 if (!radeon_connector->con_priv) 462 return; 463 464 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 465 hdmi_detected = 1; 466 467 dig_connector = radeon_connector->con_priv; 468 469 memset(&args, 0, sizeof(args)); 470 471 switch (radeon_encoder->encoder_id) { 472 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 473 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 474 break; 475 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 477 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 478 break; 479 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 481 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 482 else 483 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 484 break; 485 } 486 487 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 488 489 switch (frev) { 490 case 1: 491 case 2: 492 switch (crev) { 493 case 1: 494 args.v1.ucMisc = 0; 495 args.v1.ucAction = action; 496 if (hdmi_detected) 497 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 498 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 499 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 500 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) 501 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 502 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 503 args.v1.ucMisc |= (1 << 1); 504 } else { 505 if (dig_connector->linkb) 506 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 507 if (radeon_encoder->pixel_clock > 165000) 508 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 509 /*if (pScrn->rgbBits == 8) */ 510 args.v1.ucMisc |= (1 << 1); 511 } 512 break; 513 case 2: 514 case 3: 515 args.v2.ucMisc = 0; 516 args.v2.ucAction = action; 517 if (crev == 3) { 518 if (dig->coherent_mode) 519 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 520 } 521 if (hdmi_detected) 522 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 523 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 524 args.v2.ucTruncate = 0; 525 args.v2.ucSpatial = 0; 526 args.v2.ucTemporal = 0; 527 args.v2.ucFRC = 0; 528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 529 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) 530 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 531 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) { 532 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 533 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 534 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 535 } 536 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) { 537 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 538 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 540 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 541 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 542 } 543 } else { 544 if (dig_connector->linkb) 545 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 546 if (radeon_encoder->pixel_clock > 165000) 547 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 548 } 549 break; 550 default: 551 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 552 break; 553 } 554 break; 555 default: 556 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 557 break; 558 } 559 560 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 561 r600_hdmi_enable(encoder, hdmi_detected); 562 } 563 564 int 565 atombios_get_encoder_mode(struct drm_encoder *encoder) 566 { 567 struct drm_connector *connector; 568 struct radeon_connector *radeon_connector; 569 struct radeon_connector_atom_dig *radeon_dig_connector; 570 571 connector = radeon_get_connector_for_encoder(encoder); 572 if (!connector) 573 return 0; 574 575 radeon_connector = to_radeon_connector(connector); 576 577 switch (connector->connector_type) { 578 case DRM_MODE_CONNECTOR_DVII: 579 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 580 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 581 return ATOM_ENCODER_MODE_HDMI; 582 else if (radeon_connector->use_digital) 583 return ATOM_ENCODER_MODE_DVI; 584 else 585 return ATOM_ENCODER_MODE_CRT; 586 break; 587 case DRM_MODE_CONNECTOR_DVID: 588 case DRM_MODE_CONNECTOR_HDMIA: 589 default: 590 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 591 return ATOM_ENCODER_MODE_HDMI; 592 else 593 return ATOM_ENCODER_MODE_DVI; 594 break; 595 case DRM_MODE_CONNECTOR_LVDS: 596 return ATOM_ENCODER_MODE_LVDS; 597 break; 598 case DRM_MODE_CONNECTOR_DisplayPort: 599 case DRM_MODE_CONNECTOR_eDP: 600 radeon_dig_connector = radeon_connector->con_priv; 601 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 602 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 603 return ATOM_ENCODER_MODE_DP; 604 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) 605 return ATOM_ENCODER_MODE_HDMI; 606 else 607 return ATOM_ENCODER_MODE_DVI; 608 break; 609 case DRM_MODE_CONNECTOR_DVIA: 610 case DRM_MODE_CONNECTOR_VGA: 611 return ATOM_ENCODER_MODE_CRT; 612 break; 613 case DRM_MODE_CONNECTOR_Composite: 614 case DRM_MODE_CONNECTOR_SVIDEO: 615 case DRM_MODE_CONNECTOR_9PinDIN: 616 /* fix me */ 617 return ATOM_ENCODER_MODE_TV; 618 /*return ATOM_ENCODER_MODE_CV;*/ 619 break; 620 } 621 } 622 623 /* 624 * DIG Encoder/Transmitter Setup 625 * 626 * DCE 3.0/3.1 627 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 628 * Supports up to 3 digital outputs 629 * - 2 DIG encoder blocks. 630 * DIG1 can drive UNIPHY link A or link B 631 * DIG2 can drive UNIPHY link B or LVTMA 632 * 633 * DCE 3.2 634 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 635 * Supports up to 5 digital outputs 636 * - 2 DIG encoder blocks. 637 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 638 * 639 * Routing 640 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 641 * Examples: 642 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 643 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 644 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 645 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 646 */ 647 static void 648 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) 649 { 650 struct drm_device *dev = encoder->dev; 651 struct radeon_device *rdev = dev->dev_private; 652 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 653 DIG_ENCODER_CONTROL_PS_ALLOCATION args; 654 int index = 0, num = 0; 655 uint8_t frev, crev; 656 struct radeon_encoder_atom_dig *dig; 657 struct drm_connector *connector; 658 struct radeon_connector *radeon_connector; 659 struct radeon_connector_atom_dig *dig_connector; 660 661 connector = radeon_get_connector_for_encoder(encoder); 662 if (!connector) 663 return; 664 665 radeon_connector = to_radeon_connector(connector); 666 667 if (!radeon_connector->con_priv) 668 return; 669 670 dig_connector = radeon_connector->con_priv; 671 672 if (!radeon_encoder->enc_priv) 673 return; 674 675 dig = radeon_encoder->enc_priv; 676 677 memset(&args, 0, sizeof(args)); 678 679 if (ASIC_IS_DCE32(rdev)) { 680 if (dig->dig_block) 681 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 682 else 683 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 684 num = dig->dig_block + 1; 685 } else { 686 switch (radeon_encoder->encoder_id) { 687 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 688 /* XXX doesn't really matter which dig encoder we pick as long as it's 689 * not already in use 690 */ 691 if (dig_connector->linkb) 692 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 693 else 694 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 695 num = 1; 696 break; 697 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 698 /* Only dig2 encoder can drive LVTMA */ 699 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 700 num = 2; 701 break; 702 } 703 } 704 705 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 706 707 args.ucAction = action; 708 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 709 710 if (ASIC_IS_DCE32(rdev)) { 711 switch (radeon_encoder->encoder_id) { 712 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 713 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 714 break; 715 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 716 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 717 break; 718 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 719 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 720 break; 721 } 722 } else { 723 switch (radeon_encoder->encoder_id) { 724 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 725 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; 726 break; 727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 728 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; 729 break; 730 } 731 } 732 733 args.ucEncoderMode = atombios_get_encoder_mode(encoder); 734 735 if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 736 if (dig_connector->dp_clock == 270000) 737 args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 738 args.ucLaneNum = dig_connector->dp_lane_count; 739 } else if (radeon_encoder->pixel_clock > 165000) 740 args.ucLaneNum = 8; 741 else 742 args.ucLaneNum = 4; 743 744 if (dig_connector->linkb) 745 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 746 else 747 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 748 749 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 750 751 } 752 753 union dig_transmitter_control { 754 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 755 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 756 }; 757 758 void 759 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 760 { 761 struct drm_device *dev = encoder->dev; 762 struct radeon_device *rdev = dev->dev_private; 763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 764 union dig_transmitter_control args; 765 int index = 0, num = 0; 766 uint8_t frev, crev; 767 struct radeon_encoder_atom_dig *dig; 768 struct drm_connector *connector; 769 struct radeon_connector *radeon_connector; 770 struct radeon_connector_atom_dig *dig_connector; 771 bool is_dp = false; 772 773 connector = radeon_get_connector_for_encoder(encoder); 774 if (!connector) 775 return; 776 777 radeon_connector = to_radeon_connector(connector); 778 779 if (!radeon_encoder->enc_priv) 780 return; 781 782 dig = radeon_encoder->enc_priv; 783 784 if (!radeon_connector->con_priv) 785 return; 786 787 dig_connector = radeon_connector->con_priv; 788 789 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 790 is_dp = true; 791 792 memset(&args, 0, sizeof(args)); 793 794 if (ASIC_IS_DCE32(rdev)) 795 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 796 else { 797 switch (radeon_encoder->encoder_id) { 798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 799 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); 800 break; 801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 802 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); 803 break; 804 } 805 } 806 807 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 808 809 args.v1.ucAction = action; 810 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 811 args.v1.usInitInfo = radeon_connector->connector_object_id; 812 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 813 args.v1.asMode.ucLaneSel = lane_num; 814 args.v1.asMode.ucLaneSet = lane_set; 815 } else { 816 if (is_dp) 817 args.v1.usPixelClock = 818 cpu_to_le16(dig_connector->dp_clock / 10); 819 else if (radeon_encoder->pixel_clock > 165000) 820 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 821 else 822 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 823 } 824 if (ASIC_IS_DCE32(rdev)) { 825 if (dig->dig_block) 826 args.v2.acConfig.ucEncoderSel = 1; 827 if (dig_connector->linkb) 828 args.v2.acConfig.ucLinkSel = 1; 829 830 switch (radeon_encoder->encoder_id) { 831 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 832 args.v2.acConfig.ucTransmitterSel = 0; 833 num = 0; 834 break; 835 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 836 args.v2.acConfig.ucTransmitterSel = 1; 837 num = 1; 838 break; 839 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 840 args.v2.acConfig.ucTransmitterSel = 2; 841 num = 2; 842 break; 843 } 844 845 if (is_dp) 846 args.v2.acConfig.fCoherentMode = 1; 847 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 848 if (dig->coherent_mode) 849 args.v2.acConfig.fCoherentMode = 1; 850 } 851 } else { 852 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 853 854 switch (radeon_encoder->encoder_id) { 855 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 856 /* XXX doesn't really matter which dig encoder we pick as long as it's 857 * not already in use 858 */ 859 if (dig_connector->linkb) 860 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 861 else 862 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 863 if (rdev->flags & RADEON_IS_IGP) { 864 if (radeon_encoder->pixel_clock > 165000) { 865 if (dig_connector->igp_lane_info & 0x3) 866 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 867 else if (dig_connector->igp_lane_info & 0xc) 868 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 869 } else { 870 if (dig_connector->igp_lane_info & 0x1) 871 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 872 else if (dig_connector->igp_lane_info & 0x2) 873 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 874 else if (dig_connector->igp_lane_info & 0x4) 875 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 876 else if (dig_connector->igp_lane_info & 0x8) 877 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 878 } 879 } 880 break; 881 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 882 /* Only dig2 encoder can drive LVTMA */ 883 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 884 break; 885 } 886 887 if (radeon_encoder->pixel_clock > 165000) 888 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 889 890 if (dig_connector->linkb) 891 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 892 else 893 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 894 895 if (is_dp) 896 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 897 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 898 if (dig->coherent_mode) 899 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 900 } 901 } 902 903 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 904 } 905 906 static void 907 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 908 { 909 struct drm_device *dev = encoder->dev; 910 struct radeon_device *rdev = dev->dev_private; 911 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 912 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 913 ENABLE_YUV_PS_ALLOCATION args; 914 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 915 uint32_t temp, reg; 916 917 memset(&args, 0, sizeof(args)); 918 919 if (rdev->family >= CHIP_R600) 920 reg = R600_BIOS_3_SCRATCH; 921 else 922 reg = RADEON_BIOS_3_SCRATCH; 923 924 /* XXX: fix up scratch reg handling */ 925 temp = RREG32(reg); 926 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 927 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 928 (radeon_crtc->crtc_id << 18))); 929 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 930 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 931 else 932 WREG32(reg, 0); 933 934 if (enable) 935 args.ucEnable = ATOM_ENABLE; 936 args.ucCRTC = radeon_crtc->crtc_id; 937 938 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 939 940 WREG32(reg, temp); 941 } 942 943 static void 944 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 945 { 946 struct drm_device *dev = encoder->dev; 947 struct radeon_device *rdev = dev->dev_private; 948 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 949 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 950 int index = 0; 951 bool is_dig = false; 952 953 memset(&args, 0, sizeof(args)); 954 955 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 956 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 957 radeon_encoder->active_device); 958 switch (radeon_encoder->encoder_id) { 959 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 960 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 961 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 962 break; 963 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 964 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 965 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 966 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 967 is_dig = true; 968 break; 969 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 970 case ENCODER_OBJECT_ID_INTERNAL_DDI: 971 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 972 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 973 break; 974 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 975 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 976 break; 977 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 978 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 979 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 980 else 981 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 982 break; 983 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 984 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 985 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 986 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 987 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 988 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 989 else 990 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 991 break; 992 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 993 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 994 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 995 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 996 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 997 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 998 else 999 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1000 break; 1001 } 1002 1003 if (is_dig) { 1004 switch (mode) { 1005 case DRM_MODE_DPMS_ON: 1006 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1007 { 1008 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1009 dp_link_train(encoder, connector); 1010 } 1011 break; 1012 case DRM_MODE_DPMS_STANDBY: 1013 case DRM_MODE_DPMS_SUSPEND: 1014 case DRM_MODE_DPMS_OFF: 1015 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1016 break; 1017 } 1018 } else { 1019 switch (mode) { 1020 case DRM_MODE_DPMS_ON: 1021 args.ucAction = ATOM_ENABLE; 1022 break; 1023 case DRM_MODE_DPMS_STANDBY: 1024 case DRM_MODE_DPMS_SUSPEND: 1025 case DRM_MODE_DPMS_OFF: 1026 args.ucAction = ATOM_DISABLE; 1027 break; 1028 } 1029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1030 } 1031 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1032 } 1033 1034 union crtc_sourc_param { 1035 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1036 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1037 }; 1038 1039 static void 1040 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1041 { 1042 struct drm_device *dev = encoder->dev; 1043 struct radeon_device *rdev = dev->dev_private; 1044 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1045 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1046 union crtc_sourc_param args; 1047 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1048 uint8_t frev, crev; 1049 1050 memset(&args, 0, sizeof(args)); 1051 1052 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 1053 1054 switch (frev) { 1055 case 1: 1056 switch (crev) { 1057 case 1: 1058 default: 1059 if (ASIC_IS_AVIVO(rdev)) 1060 args.v1.ucCRTC = radeon_crtc->crtc_id; 1061 else { 1062 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1063 args.v1.ucCRTC = radeon_crtc->crtc_id; 1064 } else { 1065 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1066 } 1067 } 1068 switch (radeon_encoder->encoder_id) { 1069 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1070 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1071 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1072 break; 1073 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1074 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1075 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1076 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1077 else 1078 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1079 break; 1080 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1081 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1082 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1083 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1084 break; 1085 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1086 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1087 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1088 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1089 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1090 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1091 else 1092 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1093 break; 1094 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1095 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1096 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1097 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1098 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1099 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1100 else 1101 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1102 break; 1103 } 1104 break; 1105 case 2: 1106 args.v2.ucCRTC = radeon_crtc->crtc_id; 1107 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1108 switch (radeon_encoder->encoder_id) { 1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1110 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1111 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1112 if (ASIC_IS_DCE32(rdev)) { 1113 if (radeon_crtc->crtc_id) 1114 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1115 else 1116 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1117 } else { 1118 struct drm_connector *connector; 1119 struct radeon_connector *radeon_connector; 1120 struct radeon_connector_atom_dig *dig_connector; 1121 1122 connector = radeon_get_connector_for_encoder(encoder); 1123 if (!connector) 1124 return; 1125 radeon_connector = to_radeon_connector(connector); 1126 if (!radeon_connector->con_priv) 1127 return; 1128 dig_connector = radeon_connector->con_priv; 1129 1130 /* XXX doesn't really matter which dig encoder we pick as long as it's 1131 * not already in use 1132 */ 1133 if (dig_connector->linkb) 1134 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1135 else 1136 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1137 } 1138 break; 1139 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1140 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1141 break; 1142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1143 /* Only dig2 encoder can drive LVTMA */ 1144 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1145 break; 1146 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1147 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1148 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1149 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1150 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1151 else 1152 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1153 break; 1154 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1155 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1156 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1157 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1158 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1159 else 1160 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1161 break; 1162 } 1163 break; 1164 } 1165 break; 1166 default: 1167 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1168 break; 1169 } 1170 1171 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1172 } 1173 1174 static void 1175 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1176 struct drm_display_mode *mode) 1177 { 1178 struct drm_device *dev = encoder->dev; 1179 struct radeon_device *rdev = dev->dev_private; 1180 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1181 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1182 1183 /* Funky macbooks */ 1184 if ((dev->pdev->device == 0x71C5) && 1185 (dev->pdev->subsystem_vendor == 0x106b) && 1186 (dev->pdev->subsystem_device == 0x0080)) { 1187 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1188 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1189 1190 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1191 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1192 1193 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1194 } 1195 } 1196 1197 /* set scaler clears this on some chips */ 1198 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { 1199 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) 1200 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1201 AVIVO_D1MODE_INTERLEAVE_EN); 1202 } 1203 } 1204 1205 static void 1206 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1207 struct drm_display_mode *mode, 1208 struct drm_display_mode *adjusted_mode) 1209 { 1210 struct drm_device *dev = encoder->dev; 1211 struct radeon_device *rdev = dev->dev_private; 1212 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1213 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1214 1215 if (radeon_encoder->active_device & 1216 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { 1217 if (radeon_encoder->enc_priv) { 1218 struct radeon_encoder_atom_dig *dig; 1219 1220 dig = radeon_encoder->enc_priv; 1221 dig->dig_block = radeon_crtc->crtc_id; 1222 } 1223 } 1224 radeon_encoder->pixel_clock = adjusted_mode->clock; 1225 1226 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1227 atombios_set_encoder_crtc_source(encoder); 1228 1229 if (ASIC_IS_AVIVO(rdev)) { 1230 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1231 atombios_yuv_setup(encoder, true); 1232 else 1233 atombios_yuv_setup(encoder, false); 1234 } 1235 1236 switch (radeon_encoder->encoder_id) { 1237 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1238 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1239 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1240 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1241 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1242 break; 1243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1246 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1247 /* disable the encoder and transmitter */ 1248 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1249 atombios_dig_encoder_setup(encoder, ATOM_DISABLE); 1250 1251 /* setup and enable the encoder and transmitter */ 1252 atombios_dig_encoder_setup(encoder, ATOM_ENABLE); 1253 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1254 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1255 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1256 break; 1257 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1258 atombios_ddia_setup(encoder, ATOM_ENABLE); 1259 break; 1260 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1261 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1262 atombios_external_tmds_setup(encoder, ATOM_ENABLE); 1263 break; 1264 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1265 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1266 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1267 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1268 atombios_dac_setup(encoder, ATOM_ENABLE); 1269 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1270 atombios_tv_setup(encoder, ATOM_ENABLE); 1271 break; 1272 } 1273 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1274 1275 r600_hdmi_setmode(encoder, adjusted_mode); 1276 } 1277 1278 static bool 1279 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1280 { 1281 struct drm_device *dev = encoder->dev; 1282 struct radeon_device *rdev = dev->dev_private; 1283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1284 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1285 1286 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1287 ATOM_DEVICE_CV_SUPPORT | 1288 ATOM_DEVICE_CRT_SUPPORT)) { 1289 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1290 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1291 uint8_t frev, crev; 1292 1293 memset(&args, 0, sizeof(args)); 1294 1295 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 1296 1297 args.sDacload.ucMisc = 0; 1298 1299 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1300 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1301 args.sDacload.ucDacType = ATOM_DAC_A; 1302 else 1303 args.sDacload.ucDacType = ATOM_DAC_B; 1304 1305 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1306 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1307 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1308 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1309 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1310 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1311 if (crev >= 3) 1312 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1313 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1314 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1315 if (crev >= 3) 1316 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1317 } 1318 1319 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1320 1321 return true; 1322 } else 1323 return false; 1324 } 1325 1326 static enum drm_connector_status 1327 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1328 { 1329 struct drm_device *dev = encoder->dev; 1330 struct radeon_device *rdev = dev->dev_private; 1331 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1332 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1333 uint32_t bios_0_scratch; 1334 1335 if (!atombios_dac_load_detect(encoder, connector)) { 1336 DRM_DEBUG("detect returned false \n"); 1337 return connector_status_unknown; 1338 } 1339 1340 if (rdev->family >= CHIP_R600) 1341 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1342 else 1343 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1344 1345 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1346 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1347 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1348 return connector_status_connected; 1349 } 1350 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1351 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1352 return connector_status_connected; 1353 } 1354 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1355 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1356 return connector_status_connected; 1357 } 1358 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1359 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1360 return connector_status_connected; /* CTV */ 1361 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1362 return connector_status_connected; /* STV */ 1363 } 1364 return connector_status_disconnected; 1365 } 1366 1367 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 1368 { 1369 radeon_atom_output_lock(encoder, true); 1370 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1371 } 1372 1373 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 1374 { 1375 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 1376 radeon_atom_output_lock(encoder, false); 1377 } 1378 1379 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 1380 { 1381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1382 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1383 radeon_encoder->active_device = 0; 1384 } 1385 1386 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 1387 .dpms = radeon_atom_encoder_dpms, 1388 .mode_fixup = radeon_atom_mode_fixup, 1389 .prepare = radeon_atom_encoder_prepare, 1390 .mode_set = radeon_atom_encoder_mode_set, 1391 .commit = radeon_atom_encoder_commit, 1392 .disable = radeon_atom_encoder_disable, 1393 /* no detect for TMDS/LVDS yet */ 1394 }; 1395 1396 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 1397 .dpms = radeon_atom_encoder_dpms, 1398 .mode_fixup = radeon_atom_mode_fixup, 1399 .prepare = radeon_atom_encoder_prepare, 1400 .mode_set = radeon_atom_encoder_mode_set, 1401 .commit = radeon_atom_encoder_commit, 1402 .detect = radeon_atom_dac_detect, 1403 }; 1404 1405 void radeon_enc_destroy(struct drm_encoder *encoder) 1406 { 1407 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1408 kfree(radeon_encoder->enc_priv); 1409 drm_encoder_cleanup(encoder); 1410 kfree(radeon_encoder); 1411 } 1412 1413 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 1414 .destroy = radeon_enc_destroy, 1415 }; 1416 1417 struct radeon_encoder_atom_dac * 1418 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 1419 { 1420 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 1421 1422 if (!dac) 1423 return NULL; 1424 1425 dac->tv_std = TV_STD_NTSC; 1426 return dac; 1427 } 1428 1429 struct radeon_encoder_atom_dig * 1430 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 1431 { 1432 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1433 1434 if (!dig) 1435 return NULL; 1436 1437 /* coherent mode by default */ 1438 dig->coherent_mode = true; 1439 1440 return dig; 1441 } 1442 1443 void 1444 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1445 { 1446 struct radeon_device *rdev = dev->dev_private; 1447 struct drm_encoder *encoder; 1448 struct radeon_encoder *radeon_encoder; 1449 1450 /* see if we already added it */ 1451 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1452 radeon_encoder = to_radeon_encoder(encoder); 1453 if (radeon_encoder->encoder_id == encoder_id) { 1454 radeon_encoder->devices |= supported_device; 1455 return; 1456 } 1457 1458 } 1459 1460 /* add a new one */ 1461 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 1462 if (!radeon_encoder) 1463 return; 1464 1465 encoder = &radeon_encoder->base; 1466 if (rdev->flags & RADEON_SINGLE_CRTC) 1467 encoder->possible_crtcs = 0x1; 1468 else 1469 encoder->possible_crtcs = 0x3; 1470 1471 radeon_encoder->enc_priv = NULL; 1472 1473 radeon_encoder->encoder_id = encoder_id; 1474 radeon_encoder->devices = supported_device; 1475 radeon_encoder->rmx_type = RMX_OFF; 1476 1477 switch (radeon_encoder->encoder_id) { 1478 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1479 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1480 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1481 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1482 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1483 radeon_encoder->rmx_type = RMX_FULL; 1484 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 1485 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1486 } else { 1487 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1488 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1489 } 1490 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1491 break; 1492 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1493 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 1494 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 1495 break; 1496 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1497 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1499 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 1500 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 1501 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 1502 break; 1503 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1504 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1505 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1506 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1507 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1508 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1509 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1510 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1511 radeon_encoder->rmx_type = RMX_FULL; 1512 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 1513 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1514 } else { 1515 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1516 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1517 } 1518 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1519 break; 1520 } 1521 1522 r600_hdmi_init(encoder); 1523 } 1524