1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 43 struct drm_encoder *clone_encoder; 44 uint32_t index_mask = 0; 45 int count; 46 47 /* DIG routing gets problematic */ 48 if (rdev->family >= CHIP_R600) 49 return index_mask; 50 /* LVDS/TV are too wacky */ 51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 52 return index_mask; 53 /* DVO requires 2x ppll clocks depending on tmds chip */ 54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) 55 return index_mask; 56 57 count = -1; 58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { 59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); 60 count++; 61 62 if (clone_encoder == encoder) 63 continue; 64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) 65 continue; 66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) 67 continue; 68 else 69 index_mask |= (1 << count); 70 } 71 return index_mask; 72 } 73 74 void radeon_setup_encoder_clones(struct drm_device *dev) 75 { 76 struct drm_encoder *encoder; 77 78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 79 encoder->possible_clones = radeon_encoder_clones(encoder); 80 } 81 } 82 83 uint32_t 84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 85 { 86 struct radeon_device *rdev = dev->dev_private; 87 uint32_t ret = 0; 88 89 switch (supported_device) { 90 case ATOM_DEVICE_CRT1_SUPPORT: 91 case ATOM_DEVICE_TV1_SUPPORT: 92 case ATOM_DEVICE_TV2_SUPPORT: 93 case ATOM_DEVICE_CRT2_SUPPORT: 94 case ATOM_DEVICE_CV_SUPPORT: 95 switch (dac) { 96 case 1: /* dac a */ 97 if ((rdev->family == CHIP_RS300) || 98 (rdev->family == CHIP_RS400) || 99 (rdev->family == CHIP_RS480)) 100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 101 else if (ASIC_IS_AVIVO(rdev)) 102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 103 else 104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; 105 break; 106 case 2: /* dac b */ 107 if (ASIC_IS_AVIVO(rdev)) 108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 109 else { 110 /*if (rdev->family == CHIP_R200) 111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 112 else*/ 113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; 114 } 115 break; 116 case 3: /* external dac */ 117 if (ASIC_IS_AVIVO(rdev)) 118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 119 else 120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 121 break; 122 } 123 break; 124 case ATOM_DEVICE_LCD1_SUPPORT: 125 if (ASIC_IS_AVIVO(rdev)) 126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 127 else 128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; 129 break; 130 case ATOM_DEVICE_DFP1_SUPPORT: 131 if ((rdev->family == CHIP_RS300) || 132 (rdev->family == CHIP_RS400) || 133 (rdev->family == CHIP_RS480)) 134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 135 else if (ASIC_IS_AVIVO(rdev)) 136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 137 else 138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; 139 break; 140 case ATOM_DEVICE_LCD2_SUPPORT: 141 case ATOM_DEVICE_DFP2_SUPPORT: 142 if ((rdev->family == CHIP_RS600) || 143 (rdev->family == CHIP_RS690) || 144 (rdev->family == CHIP_RS740)) 145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI; 146 else if (ASIC_IS_AVIVO(rdev)) 147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; 148 else 149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; 150 break; 151 case ATOM_DEVICE_DFP3_SUPPORT: 152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; 153 break; 154 } 155 156 return ret; 157 } 158 159 void 160 radeon_link_encoder_connector(struct drm_device *dev) 161 { 162 struct drm_connector *connector; 163 struct radeon_connector *radeon_connector; 164 struct drm_encoder *encoder; 165 struct radeon_encoder *radeon_encoder; 166 167 /* walk the list and link encoders to connectors */ 168 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 169 radeon_connector = to_radeon_connector(connector); 170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 171 radeon_encoder = to_radeon_encoder(encoder); 172 if (radeon_encoder->devices & radeon_connector->devices) 173 drm_mode_connector_attach_encoder(connector, encoder); 174 } 175 } 176 } 177 178 void radeon_encoder_set_active_device(struct drm_encoder *encoder) 179 { 180 struct drm_device *dev = encoder->dev; 181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 182 struct drm_connector *connector; 183 184 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 185 if (connector->encoder == encoder) { 186 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 187 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; 188 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", 189 radeon_encoder->active_device, radeon_encoder->devices, 190 radeon_connector->devices, encoder->encoder_type); 191 } 192 } 193 } 194 195 static struct drm_connector * 196 radeon_get_connector_for_encoder(struct drm_encoder *encoder) 197 { 198 struct drm_device *dev = encoder->dev; 199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 200 struct drm_connector *connector; 201 struct radeon_connector *radeon_connector; 202 203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 204 radeon_connector = to_radeon_connector(connector); 205 if (radeon_encoder->devices & radeon_connector->devices) 206 return connector; 207 } 208 return NULL; 209 } 210 211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 212 struct drm_display_mode *mode, 213 struct drm_display_mode *adjusted_mode) 214 { 215 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 216 struct drm_device *dev = encoder->dev; 217 struct radeon_device *rdev = dev->dev_private; 218 219 /* set the active encoder to connector routing */ 220 radeon_encoder_set_active_device(encoder); 221 drm_mode_set_crtcinfo(adjusted_mode, 0); 222 223 /* hw bug */ 224 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 225 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 226 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 227 228 /* get the native mode for LVDS */ 229 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 230 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 231 int mode_id = adjusted_mode->base.id; 232 *adjusted_mode = *native_mode; 233 if (!ASIC_IS_AVIVO(rdev)) { 234 adjusted_mode->hdisplay = mode->hdisplay; 235 adjusted_mode->vdisplay = mode->vdisplay; 236 adjusted_mode->crtc_hdisplay = mode->hdisplay; 237 adjusted_mode->crtc_vdisplay = mode->vdisplay; 238 } 239 adjusted_mode->base.id = mode_id; 240 } 241 242 /* get the native mode for TV */ 243 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 244 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 245 if (tv_dac) { 246 if (tv_dac->tv_std == TV_STD_NTSC || 247 tv_dac->tv_std == TV_STD_NTSC_J || 248 tv_dac->tv_std == TV_STD_PAL_M) 249 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 250 else 251 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 252 } 253 } 254 255 if (ASIC_IS_DCE3(rdev) && 256 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { 257 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 258 radeon_dp_set_link_config(connector, mode); 259 } 260 261 return true; 262 } 263 264 static void 265 atombios_dac_setup(struct drm_encoder *encoder, int action) 266 { 267 struct drm_device *dev = encoder->dev; 268 struct radeon_device *rdev = dev->dev_private; 269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 270 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 271 int index = 0, num = 0; 272 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 273 enum radeon_tv_std tv_std = TV_STD_NTSC; 274 275 if (dac_info->tv_std) 276 tv_std = dac_info->tv_std; 277 278 memset(&args, 0, sizeof(args)); 279 280 switch (radeon_encoder->encoder_id) { 281 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 282 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 283 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 284 num = 1; 285 break; 286 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 287 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 288 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 289 num = 2; 290 break; 291 } 292 293 args.ucAction = action; 294 295 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 296 args.ucDacStandard = ATOM_DAC1_PS2; 297 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 298 args.ucDacStandard = ATOM_DAC1_CV; 299 else { 300 switch (tv_std) { 301 case TV_STD_PAL: 302 case TV_STD_PAL_M: 303 case TV_STD_SCART_PAL: 304 case TV_STD_SECAM: 305 case TV_STD_PAL_CN: 306 args.ucDacStandard = ATOM_DAC1_PAL; 307 break; 308 case TV_STD_NTSC: 309 case TV_STD_NTSC_J: 310 case TV_STD_PAL_60: 311 default: 312 args.ucDacStandard = ATOM_DAC1_NTSC; 313 break; 314 } 315 } 316 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 317 318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 319 320 } 321 322 static void 323 atombios_tv_setup(struct drm_encoder *encoder, int action) 324 { 325 struct drm_device *dev = encoder->dev; 326 struct radeon_device *rdev = dev->dev_private; 327 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 328 TV_ENCODER_CONTROL_PS_ALLOCATION args; 329 int index = 0; 330 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 331 enum radeon_tv_std tv_std = TV_STD_NTSC; 332 333 if (dac_info->tv_std) 334 tv_std = dac_info->tv_std; 335 336 memset(&args, 0, sizeof(args)); 337 338 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 339 340 args.sTVEncoder.ucAction = action; 341 342 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 343 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 344 else { 345 switch (tv_std) { 346 case TV_STD_NTSC: 347 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 348 break; 349 case TV_STD_PAL: 350 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 351 break; 352 case TV_STD_PAL_M: 353 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 354 break; 355 case TV_STD_PAL_60: 356 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 357 break; 358 case TV_STD_NTSC_J: 359 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 360 break; 361 case TV_STD_SCART_PAL: 362 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 363 break; 364 case TV_STD_SECAM: 365 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 366 break; 367 case TV_STD_PAL_CN: 368 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 369 break; 370 default: 371 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 372 break; 373 } 374 } 375 376 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 377 378 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 379 380 } 381 382 void 383 atombios_external_tmds_setup(struct drm_encoder *encoder, int action) 384 { 385 struct drm_device *dev = encoder->dev; 386 struct radeon_device *rdev = dev->dev_private; 387 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 388 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; 389 int index = 0; 390 391 memset(&args, 0, sizeof(args)); 392 393 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 394 395 args.sXTmdsEncoder.ucEnable = action; 396 397 if (radeon_encoder->pixel_clock > 165000) 398 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; 399 400 /*if (pScrn->rgbBits == 8)*/ 401 args.sXTmdsEncoder.ucMisc |= (1 << 1); 402 403 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 404 405 } 406 407 static void 408 atombios_ddia_setup(struct drm_encoder *encoder, int action) 409 { 410 struct drm_device *dev = encoder->dev; 411 struct radeon_device *rdev = dev->dev_private; 412 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 413 DVO_ENCODER_CONTROL_PS_ALLOCATION args; 414 int index = 0; 415 416 memset(&args, 0, sizeof(args)); 417 418 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 419 420 args.sDVOEncoder.ucAction = action; 421 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 422 423 if (radeon_encoder->pixel_clock > 165000) 424 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; 425 426 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 427 428 } 429 430 union lvds_encoder_control { 431 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 432 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 433 }; 434 435 void 436 atombios_digital_setup(struct drm_encoder *encoder, int action) 437 { 438 struct drm_device *dev = encoder->dev; 439 struct radeon_device *rdev = dev->dev_private; 440 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 441 union lvds_encoder_control args; 442 int index = 0; 443 int hdmi_detected = 0; 444 uint8_t frev, crev; 445 struct radeon_encoder_atom_dig *dig; 446 struct drm_connector *connector; 447 struct radeon_connector *radeon_connector; 448 struct radeon_connector_atom_dig *dig_connector; 449 450 connector = radeon_get_connector_for_encoder(encoder); 451 if (!connector) 452 return; 453 454 radeon_connector = to_radeon_connector(connector); 455 456 if (!radeon_encoder->enc_priv) 457 return; 458 459 dig = radeon_encoder->enc_priv; 460 461 if (!radeon_connector->con_priv) 462 return; 463 464 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 465 hdmi_detected = 1; 466 467 dig_connector = radeon_connector->con_priv; 468 469 memset(&args, 0, sizeof(args)); 470 471 switch (radeon_encoder->encoder_id) { 472 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 473 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 474 break; 475 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 477 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 478 break; 479 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 481 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 482 else 483 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 484 break; 485 } 486 487 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 488 489 switch (frev) { 490 case 1: 491 case 2: 492 switch (crev) { 493 case 1: 494 args.v1.ucMisc = 0; 495 args.v1.ucAction = action; 496 if (hdmi_detected) 497 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 498 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 499 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 500 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) 501 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 502 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 503 args.v1.ucMisc |= (1 << 1); 504 } else { 505 if (dig_connector->linkb) 506 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 507 if (radeon_encoder->pixel_clock > 165000) 508 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 509 /*if (pScrn->rgbBits == 8) */ 510 args.v1.ucMisc |= (1 << 1); 511 } 512 break; 513 case 2: 514 case 3: 515 args.v2.ucMisc = 0; 516 args.v2.ucAction = action; 517 if (crev == 3) { 518 if (dig->coherent_mode) 519 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 520 } 521 if (hdmi_detected) 522 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 523 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 524 args.v2.ucTruncate = 0; 525 args.v2.ucSpatial = 0; 526 args.v2.ucTemporal = 0; 527 args.v2.ucFRC = 0; 528 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 529 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL) 530 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 531 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) { 532 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 533 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 534 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 535 } 536 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) { 537 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 538 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB) 539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 540 if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 541 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 542 } 543 } else { 544 if (dig_connector->linkb) 545 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 546 if (radeon_encoder->pixel_clock > 165000) 547 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 548 } 549 break; 550 default: 551 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 552 break; 553 } 554 break; 555 default: 556 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 557 break; 558 } 559 560 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 561 r600_hdmi_enable(encoder, hdmi_detected); 562 } 563 564 int 565 atombios_get_encoder_mode(struct drm_encoder *encoder) 566 { 567 struct drm_connector *connector; 568 struct radeon_connector *radeon_connector; 569 struct radeon_connector_atom_dig *radeon_dig_connector; 570 571 connector = radeon_get_connector_for_encoder(encoder); 572 if (!connector) 573 return 0; 574 575 radeon_connector = to_radeon_connector(connector); 576 577 switch (connector->connector_type) { 578 case DRM_MODE_CONNECTOR_DVII: 579 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 580 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 581 return ATOM_ENCODER_MODE_HDMI; 582 else if (radeon_connector->use_digital) 583 return ATOM_ENCODER_MODE_DVI; 584 else 585 return ATOM_ENCODER_MODE_CRT; 586 break; 587 case DRM_MODE_CONNECTOR_DVID: 588 case DRM_MODE_CONNECTOR_HDMIA: 589 default: 590 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 591 return ATOM_ENCODER_MODE_HDMI; 592 else 593 return ATOM_ENCODER_MODE_DVI; 594 break; 595 case DRM_MODE_CONNECTOR_LVDS: 596 return ATOM_ENCODER_MODE_LVDS; 597 break; 598 case DRM_MODE_CONNECTOR_DisplayPort: 599 radeon_dig_connector = radeon_connector->con_priv; 600 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 601 return ATOM_ENCODER_MODE_DP; 602 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) 603 return ATOM_ENCODER_MODE_HDMI; 604 else 605 return ATOM_ENCODER_MODE_DVI; 606 break; 607 case CONNECTOR_DVI_A: 608 case CONNECTOR_VGA: 609 return ATOM_ENCODER_MODE_CRT; 610 break; 611 case CONNECTOR_STV: 612 case CONNECTOR_CTV: 613 case CONNECTOR_DIN: 614 /* fix me */ 615 return ATOM_ENCODER_MODE_TV; 616 /*return ATOM_ENCODER_MODE_CV;*/ 617 break; 618 } 619 } 620 621 /* 622 * DIG Encoder/Transmitter Setup 623 * 624 * DCE 3.0/3.1 625 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 626 * Supports up to 3 digital outputs 627 * - 2 DIG encoder blocks. 628 * DIG1 can drive UNIPHY link A or link B 629 * DIG2 can drive UNIPHY link B or LVTMA 630 * 631 * DCE 3.2 632 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 633 * Supports up to 5 digital outputs 634 * - 2 DIG encoder blocks. 635 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 636 * 637 * Routing 638 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 639 * Examples: 640 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 641 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 642 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 643 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 644 */ 645 static void 646 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) 647 { 648 struct drm_device *dev = encoder->dev; 649 struct radeon_device *rdev = dev->dev_private; 650 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 651 DIG_ENCODER_CONTROL_PS_ALLOCATION args; 652 int index = 0, num = 0; 653 uint8_t frev, crev; 654 struct radeon_encoder_atom_dig *dig; 655 struct drm_connector *connector; 656 struct radeon_connector *radeon_connector; 657 struct radeon_connector_atom_dig *dig_connector; 658 659 connector = radeon_get_connector_for_encoder(encoder); 660 if (!connector) 661 return; 662 663 radeon_connector = to_radeon_connector(connector); 664 665 if (!radeon_connector->con_priv) 666 return; 667 668 dig_connector = radeon_connector->con_priv; 669 670 if (!radeon_encoder->enc_priv) 671 return; 672 673 dig = radeon_encoder->enc_priv; 674 675 memset(&args, 0, sizeof(args)); 676 677 if (ASIC_IS_DCE32(rdev)) { 678 if (dig->dig_block) 679 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 680 else 681 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 682 num = dig->dig_block + 1; 683 } else { 684 switch (radeon_encoder->encoder_id) { 685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 686 /* XXX doesn't really matter which dig encoder we pick as long as it's 687 * not already in use 688 */ 689 if (dig_connector->linkb) 690 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 691 else 692 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 693 num = 1; 694 break; 695 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 696 /* Only dig2 encoder can drive LVTMA */ 697 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 698 num = 2; 699 break; 700 } 701 } 702 703 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 704 705 args.ucAction = action; 706 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 707 708 if (ASIC_IS_DCE32(rdev)) { 709 switch (radeon_encoder->encoder_id) { 710 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 711 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 712 break; 713 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 714 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 715 break; 716 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 717 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 718 break; 719 } 720 } else { 721 switch (radeon_encoder->encoder_id) { 722 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 723 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; 724 break; 725 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 726 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; 727 break; 728 } 729 } 730 731 args.ucEncoderMode = atombios_get_encoder_mode(encoder); 732 733 if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 734 if (dig_connector->dp_clock == 270000) 735 args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 736 args.ucLaneNum = dig_connector->dp_lane_count; 737 } else if (radeon_encoder->pixel_clock > 165000) 738 args.ucLaneNum = 8; 739 else 740 args.ucLaneNum = 4; 741 742 if (dig_connector->linkb) 743 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 744 else 745 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 746 747 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 748 749 } 750 751 union dig_transmitter_control { 752 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 753 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 754 }; 755 756 void 757 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 758 { 759 struct drm_device *dev = encoder->dev; 760 struct radeon_device *rdev = dev->dev_private; 761 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 762 union dig_transmitter_control args; 763 int index = 0, num = 0; 764 uint8_t frev, crev; 765 struct radeon_encoder_atom_dig *dig; 766 struct drm_connector *connector; 767 struct radeon_connector *radeon_connector; 768 struct radeon_connector_atom_dig *dig_connector; 769 bool is_dp = false; 770 771 connector = radeon_get_connector_for_encoder(encoder); 772 if (!connector) 773 return; 774 775 radeon_connector = to_radeon_connector(connector); 776 777 if (!radeon_encoder->enc_priv) 778 return; 779 780 dig = radeon_encoder->enc_priv; 781 782 if (!radeon_connector->con_priv) 783 return; 784 785 dig_connector = radeon_connector->con_priv; 786 787 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 788 is_dp = true; 789 790 memset(&args, 0, sizeof(args)); 791 792 if (ASIC_IS_DCE32(rdev)) 793 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 794 else { 795 switch (radeon_encoder->encoder_id) { 796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 797 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); 798 break; 799 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 800 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); 801 break; 802 } 803 } 804 805 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 806 807 args.v1.ucAction = action; 808 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 809 args.v1.usInitInfo = radeon_connector->connector_object_id; 810 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 811 args.v1.asMode.ucLaneSel = lane_num; 812 args.v1.asMode.ucLaneSet = lane_set; 813 } else { 814 if (is_dp) 815 args.v1.usPixelClock = 816 cpu_to_le16(dig_connector->dp_clock / 10); 817 else if (radeon_encoder->pixel_clock > 165000) 818 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 819 else 820 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 821 } 822 if (ASIC_IS_DCE32(rdev)) { 823 if (dig->dig_block) 824 args.v2.acConfig.ucEncoderSel = 1; 825 if (dig_connector->linkb) 826 args.v2.acConfig.ucLinkSel = 1; 827 828 switch (radeon_encoder->encoder_id) { 829 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 830 args.v2.acConfig.ucTransmitterSel = 0; 831 num = 0; 832 break; 833 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 834 args.v2.acConfig.ucTransmitterSel = 1; 835 num = 1; 836 break; 837 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 838 args.v2.acConfig.ucTransmitterSel = 2; 839 num = 2; 840 break; 841 } 842 843 if (is_dp) 844 args.v2.acConfig.fCoherentMode = 1; 845 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 846 if (dig->coherent_mode) 847 args.v2.acConfig.fCoherentMode = 1; 848 } 849 } else { 850 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 851 852 switch (radeon_encoder->encoder_id) { 853 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 854 /* XXX doesn't really matter which dig encoder we pick as long as it's 855 * not already in use 856 */ 857 if (dig_connector->linkb) 858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 859 else 860 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 861 if (rdev->flags & RADEON_IS_IGP) { 862 if (radeon_encoder->pixel_clock > 165000) { 863 if (dig_connector->igp_lane_info & 0x3) 864 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 865 else if (dig_connector->igp_lane_info & 0xc) 866 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 867 } else { 868 if (dig_connector->igp_lane_info & 0x1) 869 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 870 else if (dig_connector->igp_lane_info & 0x2) 871 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 872 else if (dig_connector->igp_lane_info & 0x4) 873 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 874 else if (dig_connector->igp_lane_info & 0x8) 875 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 876 } 877 } 878 break; 879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 880 /* Only dig2 encoder can drive LVTMA */ 881 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 882 break; 883 } 884 885 if (radeon_encoder->pixel_clock > 165000) 886 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 887 888 if (dig_connector->linkb) 889 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 890 else 891 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 892 893 if (is_dp) 894 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 895 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 896 if (dig->coherent_mode) 897 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 898 } 899 } 900 901 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 902 } 903 904 static void 905 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 906 { 907 struct drm_device *dev = encoder->dev; 908 struct radeon_device *rdev = dev->dev_private; 909 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 910 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 911 ENABLE_YUV_PS_ALLOCATION args; 912 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 913 uint32_t temp, reg; 914 915 memset(&args, 0, sizeof(args)); 916 917 if (rdev->family >= CHIP_R600) 918 reg = R600_BIOS_3_SCRATCH; 919 else 920 reg = RADEON_BIOS_3_SCRATCH; 921 922 /* XXX: fix up scratch reg handling */ 923 temp = RREG32(reg); 924 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 925 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 926 (radeon_crtc->crtc_id << 18))); 927 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 928 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 929 else 930 WREG32(reg, 0); 931 932 if (enable) 933 args.ucEnable = ATOM_ENABLE; 934 args.ucCRTC = radeon_crtc->crtc_id; 935 936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 937 938 WREG32(reg, temp); 939 } 940 941 static void 942 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 943 { 944 struct drm_device *dev = encoder->dev; 945 struct radeon_device *rdev = dev->dev_private; 946 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 947 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 948 int index = 0; 949 bool is_dig = false; 950 951 memset(&args, 0, sizeof(args)); 952 953 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 954 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 955 radeon_encoder->active_device); 956 switch (radeon_encoder->encoder_id) { 957 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 958 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 959 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 960 break; 961 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 962 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 963 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 964 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 965 is_dig = true; 966 break; 967 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 968 case ENCODER_OBJECT_ID_INTERNAL_DDI: 969 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 970 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 971 break; 972 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 973 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 974 break; 975 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 976 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 977 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 978 else 979 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 980 break; 981 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 982 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 983 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 984 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 985 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 986 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 987 else 988 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 989 break; 990 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 991 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 992 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 993 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 994 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 995 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 996 else 997 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 998 break; 999 } 1000 1001 if (is_dig) { 1002 switch (mode) { 1003 case DRM_MODE_DPMS_ON: 1004 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1005 { 1006 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1007 dp_link_train(encoder, connector); 1008 } 1009 break; 1010 case DRM_MODE_DPMS_STANDBY: 1011 case DRM_MODE_DPMS_SUSPEND: 1012 case DRM_MODE_DPMS_OFF: 1013 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1014 break; 1015 } 1016 } else { 1017 switch (mode) { 1018 case DRM_MODE_DPMS_ON: 1019 args.ucAction = ATOM_ENABLE; 1020 break; 1021 case DRM_MODE_DPMS_STANDBY: 1022 case DRM_MODE_DPMS_SUSPEND: 1023 case DRM_MODE_DPMS_OFF: 1024 args.ucAction = ATOM_DISABLE; 1025 break; 1026 } 1027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1028 } 1029 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1030 } 1031 1032 union crtc_sourc_param { 1033 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1034 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1035 }; 1036 1037 static void 1038 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1039 { 1040 struct drm_device *dev = encoder->dev; 1041 struct radeon_device *rdev = dev->dev_private; 1042 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1043 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1044 union crtc_sourc_param args; 1045 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1046 uint8_t frev, crev; 1047 1048 memset(&args, 0, sizeof(args)); 1049 1050 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 1051 1052 switch (frev) { 1053 case 1: 1054 switch (crev) { 1055 case 1: 1056 default: 1057 if (ASIC_IS_AVIVO(rdev)) 1058 args.v1.ucCRTC = radeon_crtc->crtc_id; 1059 else { 1060 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1061 args.v1.ucCRTC = radeon_crtc->crtc_id; 1062 } else { 1063 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1064 } 1065 } 1066 switch (radeon_encoder->encoder_id) { 1067 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1068 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1069 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1070 break; 1071 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1072 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1073 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1074 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1075 else 1076 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1077 break; 1078 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1079 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1080 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1081 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1082 break; 1083 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1084 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1085 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1086 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1087 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1088 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1089 else 1090 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1091 break; 1092 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1093 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1094 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1095 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1096 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1097 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1098 else 1099 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1100 break; 1101 } 1102 break; 1103 case 2: 1104 args.v2.ucCRTC = radeon_crtc->crtc_id; 1105 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1106 switch (radeon_encoder->encoder_id) { 1107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1110 if (ASIC_IS_DCE32(rdev)) { 1111 if (radeon_crtc->crtc_id) 1112 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1113 else 1114 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1115 } else { 1116 struct drm_connector *connector; 1117 struct radeon_connector *radeon_connector; 1118 struct radeon_connector_atom_dig *dig_connector; 1119 1120 connector = radeon_get_connector_for_encoder(encoder); 1121 if (!connector) 1122 return; 1123 radeon_connector = to_radeon_connector(connector); 1124 if (!radeon_connector->con_priv) 1125 return; 1126 dig_connector = radeon_connector->con_priv; 1127 1128 /* XXX doesn't really matter which dig encoder we pick as long as it's 1129 * not already in use 1130 */ 1131 if (dig_connector->linkb) 1132 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1133 else 1134 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1135 } 1136 break; 1137 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1138 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1139 break; 1140 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1141 /* Only dig2 encoder can drive LVTMA */ 1142 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1143 break; 1144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1145 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1146 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1148 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1149 else 1150 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1151 break; 1152 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1153 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1154 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1155 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1156 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1157 else 1158 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1159 break; 1160 } 1161 break; 1162 } 1163 break; 1164 default: 1165 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1166 break; 1167 } 1168 1169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1170 } 1171 1172 static void 1173 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1174 struct drm_display_mode *mode) 1175 { 1176 struct drm_device *dev = encoder->dev; 1177 struct radeon_device *rdev = dev->dev_private; 1178 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1179 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1180 1181 /* Funky macbooks */ 1182 if ((dev->pdev->device == 0x71C5) && 1183 (dev->pdev->subsystem_vendor == 0x106b) && 1184 (dev->pdev->subsystem_device == 0x0080)) { 1185 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1186 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1187 1188 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1189 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1190 1191 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1192 } 1193 } 1194 1195 /* set scaler clears this on some chips */ 1196 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { 1197 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) 1198 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1199 AVIVO_D1MODE_INTERLEAVE_EN); 1200 } 1201 } 1202 1203 static void 1204 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1205 struct drm_display_mode *mode, 1206 struct drm_display_mode *adjusted_mode) 1207 { 1208 struct drm_device *dev = encoder->dev; 1209 struct radeon_device *rdev = dev->dev_private; 1210 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1211 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1212 1213 if (radeon_encoder->active_device & 1214 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { 1215 if (radeon_encoder->enc_priv) { 1216 struct radeon_encoder_atom_dig *dig; 1217 1218 dig = radeon_encoder->enc_priv; 1219 dig->dig_block = radeon_crtc->crtc_id; 1220 } 1221 } 1222 radeon_encoder->pixel_clock = adjusted_mode->clock; 1223 1224 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1225 atombios_set_encoder_crtc_source(encoder); 1226 1227 if (ASIC_IS_AVIVO(rdev)) { 1228 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1229 atombios_yuv_setup(encoder, true); 1230 else 1231 atombios_yuv_setup(encoder, false); 1232 } 1233 1234 switch (radeon_encoder->encoder_id) { 1235 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1236 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1237 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1238 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1239 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1240 break; 1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1242 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1244 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1245 /* disable the encoder and transmitter */ 1246 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1247 atombios_dig_encoder_setup(encoder, ATOM_DISABLE); 1248 1249 /* setup and enable the encoder and transmitter */ 1250 atombios_dig_encoder_setup(encoder, ATOM_ENABLE); 1251 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1252 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1253 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1254 break; 1255 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1256 atombios_ddia_setup(encoder, ATOM_ENABLE); 1257 break; 1258 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1259 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1260 atombios_external_tmds_setup(encoder, ATOM_ENABLE); 1261 break; 1262 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1263 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1264 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1265 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1266 atombios_dac_setup(encoder, ATOM_ENABLE); 1267 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1268 atombios_tv_setup(encoder, ATOM_ENABLE); 1269 break; 1270 } 1271 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1272 1273 r600_hdmi_setmode(encoder, adjusted_mode); 1274 } 1275 1276 static bool 1277 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1278 { 1279 struct drm_device *dev = encoder->dev; 1280 struct radeon_device *rdev = dev->dev_private; 1281 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1282 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1283 1284 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1285 ATOM_DEVICE_CV_SUPPORT | 1286 ATOM_DEVICE_CRT_SUPPORT)) { 1287 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1288 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1289 uint8_t frev, crev; 1290 1291 memset(&args, 0, sizeof(args)); 1292 1293 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 1294 1295 args.sDacload.ucMisc = 0; 1296 1297 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1298 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1299 args.sDacload.ucDacType = ATOM_DAC_A; 1300 else 1301 args.sDacload.ucDacType = ATOM_DAC_B; 1302 1303 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1304 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1305 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1306 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1307 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1308 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1309 if (crev >= 3) 1310 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1311 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1312 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1313 if (crev >= 3) 1314 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1315 } 1316 1317 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1318 1319 return true; 1320 } else 1321 return false; 1322 } 1323 1324 static enum drm_connector_status 1325 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1326 { 1327 struct drm_device *dev = encoder->dev; 1328 struct radeon_device *rdev = dev->dev_private; 1329 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1330 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1331 uint32_t bios_0_scratch; 1332 1333 if (!atombios_dac_load_detect(encoder, connector)) { 1334 DRM_DEBUG("detect returned false \n"); 1335 return connector_status_unknown; 1336 } 1337 1338 if (rdev->family >= CHIP_R600) 1339 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1340 else 1341 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1342 1343 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1344 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1345 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1346 return connector_status_connected; 1347 } 1348 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1349 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1350 return connector_status_connected; 1351 } 1352 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1353 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1354 return connector_status_connected; 1355 } 1356 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1357 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1358 return connector_status_connected; /* CTV */ 1359 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1360 return connector_status_connected; /* STV */ 1361 } 1362 return connector_status_disconnected; 1363 } 1364 1365 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 1366 { 1367 radeon_atom_output_lock(encoder, true); 1368 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1369 } 1370 1371 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 1372 { 1373 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 1374 radeon_atom_output_lock(encoder, false); 1375 } 1376 1377 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 1378 { 1379 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1380 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1381 radeon_encoder->active_device = 0; 1382 } 1383 1384 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 1385 .dpms = radeon_atom_encoder_dpms, 1386 .mode_fixup = radeon_atom_mode_fixup, 1387 .prepare = radeon_atom_encoder_prepare, 1388 .mode_set = radeon_atom_encoder_mode_set, 1389 .commit = radeon_atom_encoder_commit, 1390 .disable = radeon_atom_encoder_disable, 1391 /* no detect for TMDS/LVDS yet */ 1392 }; 1393 1394 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 1395 .dpms = radeon_atom_encoder_dpms, 1396 .mode_fixup = radeon_atom_mode_fixup, 1397 .prepare = radeon_atom_encoder_prepare, 1398 .mode_set = radeon_atom_encoder_mode_set, 1399 .commit = radeon_atom_encoder_commit, 1400 .detect = radeon_atom_dac_detect, 1401 }; 1402 1403 void radeon_enc_destroy(struct drm_encoder *encoder) 1404 { 1405 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1406 kfree(radeon_encoder->enc_priv); 1407 drm_encoder_cleanup(encoder); 1408 kfree(radeon_encoder); 1409 } 1410 1411 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 1412 .destroy = radeon_enc_destroy, 1413 }; 1414 1415 struct radeon_encoder_atom_dac * 1416 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 1417 { 1418 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 1419 1420 if (!dac) 1421 return NULL; 1422 1423 dac->tv_std = TV_STD_NTSC; 1424 return dac; 1425 } 1426 1427 struct radeon_encoder_atom_dig * 1428 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 1429 { 1430 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1431 1432 if (!dig) 1433 return NULL; 1434 1435 /* coherent mode by default */ 1436 dig->coherent_mode = true; 1437 1438 return dig; 1439 } 1440 1441 void 1442 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) 1443 { 1444 struct radeon_device *rdev = dev->dev_private; 1445 struct drm_encoder *encoder; 1446 struct radeon_encoder *radeon_encoder; 1447 1448 /* see if we already added it */ 1449 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1450 radeon_encoder = to_radeon_encoder(encoder); 1451 if (radeon_encoder->encoder_id == encoder_id) { 1452 radeon_encoder->devices |= supported_device; 1453 return; 1454 } 1455 1456 } 1457 1458 /* add a new one */ 1459 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 1460 if (!radeon_encoder) 1461 return; 1462 1463 encoder = &radeon_encoder->base; 1464 if (rdev->flags & RADEON_SINGLE_CRTC) 1465 encoder->possible_crtcs = 0x1; 1466 else 1467 encoder->possible_crtcs = 0x3; 1468 1469 radeon_encoder->enc_priv = NULL; 1470 1471 radeon_encoder->encoder_id = encoder_id; 1472 radeon_encoder->devices = supported_device; 1473 radeon_encoder->rmx_type = RMX_OFF; 1474 1475 switch (radeon_encoder->encoder_id) { 1476 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1477 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1478 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1479 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1480 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1481 radeon_encoder->rmx_type = RMX_FULL; 1482 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 1483 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1484 } else { 1485 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1486 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1487 } 1488 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1489 break; 1490 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1491 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 1492 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 1493 break; 1494 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1495 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1496 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1497 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 1498 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 1499 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 1500 break; 1501 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1502 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1503 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1504 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1505 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1506 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1507 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1508 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1509 radeon_encoder->rmx_type = RMX_FULL; 1510 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 1511 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1512 } else { 1513 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 1514 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 1515 } 1516 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1517 break; 1518 } 1519 1520 r600_hdmi_init(encoder); 1521 } 1522