1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 43 struct drm_encoder *clone_encoder; 44 uint32_t index_mask = 0; 45 int count; 46 47 /* DIG routing gets problematic */ 48 if (rdev->family >= CHIP_R600) 49 return index_mask; 50 /* LVDS/TV are too wacky */ 51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 52 return index_mask; 53 /* DVO requires 2x ppll clocks depending on tmds chip */ 54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) 55 return index_mask; 56 57 count = -1; 58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { 59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); 60 count++; 61 62 if (clone_encoder == encoder) 63 continue; 64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) 65 continue; 66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) 67 continue; 68 else 69 index_mask |= (1 << count); 70 } 71 return index_mask; 72 } 73 74 void radeon_setup_encoder_clones(struct drm_device *dev) 75 { 76 struct drm_encoder *encoder; 77 78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 79 encoder->possible_clones = radeon_encoder_clones(encoder); 80 } 81 } 82 83 uint32_t 84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 85 { 86 struct radeon_device *rdev = dev->dev_private; 87 uint32_t ret = 0; 88 89 switch (supported_device) { 90 case ATOM_DEVICE_CRT1_SUPPORT: 91 case ATOM_DEVICE_TV1_SUPPORT: 92 case ATOM_DEVICE_TV2_SUPPORT: 93 case ATOM_DEVICE_CRT2_SUPPORT: 94 case ATOM_DEVICE_CV_SUPPORT: 95 switch (dac) { 96 case 1: /* dac a */ 97 if ((rdev->family == CHIP_RS300) || 98 (rdev->family == CHIP_RS400) || 99 (rdev->family == CHIP_RS480)) 100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; 101 else if (ASIC_IS_AVIVO(rdev)) 102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; 103 else 104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; 105 break; 106 case 2: /* dac b */ 107 if (ASIC_IS_AVIVO(rdev)) 108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; 109 else { 110 /*if (rdev->family == CHIP_R200) 111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 112 else*/ 113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; 114 } 115 break; 116 case 3: /* external dac */ 117 if (ASIC_IS_AVIVO(rdev)) 118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; 119 else 120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 121 break; 122 } 123 break; 124 case ATOM_DEVICE_LCD1_SUPPORT: 125 if (ASIC_IS_AVIVO(rdev)) 126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; 127 else 128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; 129 break; 130 case ATOM_DEVICE_DFP1_SUPPORT: 131 if ((rdev->family == CHIP_RS300) || 132 (rdev->family == CHIP_RS400) || 133 (rdev->family == CHIP_RS480)) 134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 135 else if (ASIC_IS_AVIVO(rdev)) 136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; 137 else 138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; 139 break; 140 case ATOM_DEVICE_LCD2_SUPPORT: 141 case ATOM_DEVICE_DFP2_SUPPORT: 142 if ((rdev->family == CHIP_RS600) || 143 (rdev->family == CHIP_RS690) || 144 (rdev->family == CHIP_RS740)) 145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1; 146 else if (ASIC_IS_AVIVO(rdev)) 147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; 148 else 149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 150 break; 151 case ATOM_DEVICE_DFP3_SUPPORT: 152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; 153 break; 154 } 155 156 return ret; 157 } 158 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 160 { 161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 162 switch (radeon_encoder->encoder_id) { 163 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 167 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 169 case ENCODER_OBJECT_ID_INTERNAL_DDI: 170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 174 return true; 175 default: 176 return false; 177 } 178 } 179 180 void 181 radeon_link_encoder_connector(struct drm_device *dev) 182 { 183 struct drm_connector *connector; 184 struct radeon_connector *radeon_connector; 185 struct drm_encoder *encoder; 186 struct radeon_encoder *radeon_encoder; 187 188 /* walk the list and link encoders to connectors */ 189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 190 radeon_connector = to_radeon_connector(connector); 191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 192 radeon_encoder = to_radeon_encoder(encoder); 193 if (radeon_encoder->devices & radeon_connector->devices) 194 drm_mode_connector_attach_encoder(connector, encoder); 195 } 196 } 197 } 198 199 void radeon_encoder_set_active_device(struct drm_encoder *encoder) 200 { 201 struct drm_device *dev = encoder->dev; 202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 203 struct drm_connector *connector; 204 205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 206 if (connector->encoder == encoder) { 207 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; 209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", 210 radeon_encoder->active_device, radeon_encoder->devices, 211 radeon_connector->devices, encoder->encoder_type); 212 } 213 } 214 } 215 216 struct drm_connector * 217 radeon_get_connector_for_encoder(struct drm_encoder *encoder) 218 { 219 struct drm_device *dev = encoder->dev; 220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 221 struct drm_connector *connector; 222 struct radeon_connector *radeon_connector; 223 224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 225 radeon_connector = to_radeon_connector(connector); 226 if (radeon_encoder->active_device & radeon_connector->devices) 227 return connector; 228 } 229 return NULL; 230 } 231 232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder) 233 { 234 struct drm_device *dev = encoder->dev; 235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 236 struct drm_encoder *other_encoder; 237 struct radeon_encoder *other_radeon_encoder; 238 239 if (radeon_encoder->is_ext_encoder) 240 return NULL; 241 242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 243 if (other_encoder == encoder) 244 continue; 245 other_radeon_encoder = to_radeon_encoder(other_encoder); 246 if (other_radeon_encoder->is_ext_encoder && 247 (radeon_encoder->devices & other_radeon_encoder->devices)) 248 return other_encoder; 249 } 250 return NULL; 251 } 252 253 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 254 struct drm_display_mode *adjusted_mode) 255 { 256 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 257 struct drm_device *dev = encoder->dev; 258 struct radeon_device *rdev = dev->dev_private; 259 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 260 unsigned hblank = native_mode->htotal - native_mode->hdisplay; 261 unsigned vblank = native_mode->vtotal - native_mode->vdisplay; 262 unsigned hover = native_mode->hsync_start - native_mode->hdisplay; 263 unsigned vover = native_mode->vsync_start - native_mode->vdisplay; 264 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; 265 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; 266 267 adjusted_mode->clock = native_mode->clock; 268 adjusted_mode->flags = native_mode->flags; 269 270 if (ASIC_IS_AVIVO(rdev)) { 271 adjusted_mode->hdisplay = native_mode->hdisplay; 272 adjusted_mode->vdisplay = native_mode->vdisplay; 273 } 274 275 adjusted_mode->htotal = native_mode->hdisplay + hblank; 276 adjusted_mode->hsync_start = native_mode->hdisplay + hover; 277 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; 278 279 adjusted_mode->vtotal = native_mode->vdisplay + vblank; 280 adjusted_mode->vsync_start = native_mode->vdisplay + vover; 281 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; 282 283 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 284 285 if (ASIC_IS_AVIVO(rdev)) { 286 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; 287 adjusted_mode->crtc_vdisplay = native_mode->vdisplay; 288 } 289 290 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; 291 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; 292 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; 293 294 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; 295 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; 296 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; 297 298 } 299 300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 301 struct drm_display_mode *mode, 302 struct drm_display_mode *adjusted_mode) 303 { 304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 305 struct drm_device *dev = encoder->dev; 306 struct radeon_device *rdev = dev->dev_private; 307 308 /* set the active encoder to connector routing */ 309 radeon_encoder_set_active_device(encoder); 310 drm_mode_set_crtcinfo(adjusted_mode, 0); 311 312 /* hw bug */ 313 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 314 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 315 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 316 317 /* get the native mode for LVDS */ 318 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 319 radeon_panel_mode_fixup(encoder, adjusted_mode); 320 321 /* get the native mode for TV */ 322 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 323 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 324 if (tv_dac) { 325 if (tv_dac->tv_std == TV_STD_NTSC || 326 tv_dac->tv_std == TV_STD_NTSC_J || 327 tv_dac->tv_std == TV_STD_PAL_M) 328 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 329 else 330 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 331 } 332 } 333 334 if (ASIC_IS_DCE3(rdev) && 335 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { 336 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 337 radeon_dp_set_link_config(connector, mode); 338 } 339 340 return true; 341 } 342 343 static void 344 atombios_dac_setup(struct drm_encoder *encoder, int action) 345 { 346 struct drm_device *dev = encoder->dev; 347 struct radeon_device *rdev = dev->dev_private; 348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 349 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 350 int index = 0; 351 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 352 353 memset(&args, 0, sizeof(args)); 354 355 switch (radeon_encoder->encoder_id) { 356 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 358 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 359 break; 360 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 362 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 363 break; 364 } 365 366 args.ucAction = action; 367 368 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 369 args.ucDacStandard = ATOM_DAC1_PS2; 370 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 371 args.ucDacStandard = ATOM_DAC1_CV; 372 else { 373 switch (dac_info->tv_std) { 374 case TV_STD_PAL: 375 case TV_STD_PAL_M: 376 case TV_STD_SCART_PAL: 377 case TV_STD_SECAM: 378 case TV_STD_PAL_CN: 379 args.ucDacStandard = ATOM_DAC1_PAL; 380 break; 381 case TV_STD_NTSC: 382 case TV_STD_NTSC_J: 383 case TV_STD_PAL_60: 384 default: 385 args.ucDacStandard = ATOM_DAC1_NTSC; 386 break; 387 } 388 } 389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 390 391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 392 393 } 394 395 static void 396 atombios_tv_setup(struct drm_encoder *encoder, int action) 397 { 398 struct drm_device *dev = encoder->dev; 399 struct radeon_device *rdev = dev->dev_private; 400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 401 TV_ENCODER_CONTROL_PS_ALLOCATION args; 402 int index = 0; 403 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 404 405 memset(&args, 0, sizeof(args)); 406 407 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 408 409 args.sTVEncoder.ucAction = action; 410 411 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 413 else { 414 switch (dac_info->tv_std) { 415 case TV_STD_NTSC: 416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 417 break; 418 case TV_STD_PAL: 419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 420 break; 421 case TV_STD_PAL_M: 422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 423 break; 424 case TV_STD_PAL_60: 425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 426 break; 427 case TV_STD_NTSC_J: 428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 429 break; 430 case TV_STD_SCART_PAL: 431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 432 break; 433 case TV_STD_SECAM: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 435 break; 436 case TV_STD_PAL_CN: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 438 break; 439 default: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 441 break; 442 } 443 } 444 445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 446 447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 448 449 } 450 451 union dvo_encoder_control { 452 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 453 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 454 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 455 }; 456 457 void 458 atombios_dvo_setup(struct drm_encoder *encoder, int action) 459 { 460 struct drm_device *dev = encoder->dev; 461 struct radeon_device *rdev = dev->dev_private; 462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 463 union dvo_encoder_control args; 464 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 465 466 memset(&args, 0, sizeof(args)); 467 468 if (ASIC_IS_DCE3(rdev)) { 469 /* DCE3+ */ 470 args.dvo_v3.ucAction = action; 471 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 472 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 473 } else if (ASIC_IS_DCE2(rdev)) { 474 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */ 475 args.dvo.sDVOEncoder.ucAction = action; 476 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 477 /* DFP1, CRT1, TV1 depending on the type of port */ 478 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 479 480 if (radeon_encoder->pixel_clock > 165000) 481 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 482 } else { 483 /* R4xx, R5xx */ 484 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 485 486 if (radeon_encoder->pixel_clock > 165000) 487 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 488 489 /*if (pScrn->rgbBits == 8)*/ 490 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 491 } 492 493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 494 } 495 496 union lvds_encoder_control { 497 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 498 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 499 }; 500 501 void 502 atombios_digital_setup(struct drm_encoder *encoder, int action) 503 { 504 struct drm_device *dev = encoder->dev; 505 struct radeon_device *rdev = dev->dev_private; 506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 508 union lvds_encoder_control args; 509 int index = 0; 510 int hdmi_detected = 0; 511 uint8_t frev, crev; 512 513 if (!dig) 514 return; 515 516 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 517 hdmi_detected = 1; 518 519 memset(&args, 0, sizeof(args)); 520 521 switch (radeon_encoder->encoder_id) { 522 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 523 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 524 break; 525 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 527 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 528 break; 529 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 530 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 531 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 532 else 533 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 534 break; 535 } 536 537 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 538 return; 539 540 switch (frev) { 541 case 1: 542 case 2: 543 switch (crev) { 544 case 1: 545 args.v1.ucMisc = 0; 546 args.v1.ucAction = action; 547 if (hdmi_detected) 548 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 549 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 550 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 551 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 552 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 553 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 554 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 555 } else { 556 if (dig->linkb) 557 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 558 if (radeon_encoder->pixel_clock > 165000) 559 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 560 /*if (pScrn->rgbBits == 8) */ 561 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 562 } 563 break; 564 case 2: 565 case 3: 566 args.v2.ucMisc = 0; 567 args.v2.ucAction = action; 568 if (crev == 3) { 569 if (dig->coherent_mode) 570 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 571 } 572 if (hdmi_detected) 573 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 574 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 575 args.v2.ucTruncate = 0; 576 args.v2.ucSpatial = 0; 577 args.v2.ucTemporal = 0; 578 args.v2.ucFRC = 0; 579 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 580 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 581 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 582 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 583 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 584 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 585 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 586 } 587 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 588 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 590 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 591 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 592 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 593 } 594 } else { 595 if (dig->linkb) 596 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 597 if (radeon_encoder->pixel_clock > 165000) 598 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 599 } 600 break; 601 default: 602 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 603 break; 604 } 605 break; 606 default: 607 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 608 break; 609 } 610 611 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 612 } 613 614 int 615 atombios_get_encoder_mode(struct drm_encoder *encoder) 616 { 617 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 618 struct drm_device *dev = encoder->dev; 619 struct radeon_device *rdev = dev->dev_private; 620 struct drm_connector *connector; 621 struct radeon_connector *radeon_connector; 622 struct radeon_connector_atom_dig *dig_connector; 623 624 connector = radeon_get_connector_for_encoder(encoder); 625 if (!connector) { 626 switch (radeon_encoder->encoder_id) { 627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 632 return ATOM_ENCODER_MODE_DVI; 633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 635 default: 636 return ATOM_ENCODER_MODE_CRT; 637 } 638 } 639 radeon_connector = to_radeon_connector(connector); 640 641 switch (connector->connector_type) { 642 case DRM_MODE_CONNECTOR_DVII: 643 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 644 if (drm_detect_monitor_audio(radeon_connector->edid)) { 645 /* fix me */ 646 if (ASIC_IS_DCE4(rdev)) 647 return ATOM_ENCODER_MODE_DVI; 648 else 649 return ATOM_ENCODER_MODE_HDMI; 650 } else if (radeon_connector->use_digital) 651 return ATOM_ENCODER_MODE_DVI; 652 else 653 return ATOM_ENCODER_MODE_CRT; 654 break; 655 case DRM_MODE_CONNECTOR_DVID: 656 case DRM_MODE_CONNECTOR_HDMIA: 657 default: 658 if (drm_detect_monitor_audio(radeon_connector->edid)) { 659 /* fix me */ 660 if (ASIC_IS_DCE4(rdev)) 661 return ATOM_ENCODER_MODE_DVI; 662 else 663 return ATOM_ENCODER_MODE_HDMI; 664 } else 665 return ATOM_ENCODER_MODE_DVI; 666 break; 667 case DRM_MODE_CONNECTOR_LVDS: 668 return ATOM_ENCODER_MODE_LVDS; 669 break; 670 case DRM_MODE_CONNECTOR_DisplayPort: 671 case DRM_MODE_CONNECTOR_eDP: 672 dig_connector = radeon_connector->con_priv; 673 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 674 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 675 return ATOM_ENCODER_MODE_DP; 676 else if (drm_detect_monitor_audio(radeon_connector->edid)) { 677 /* fix me */ 678 if (ASIC_IS_DCE4(rdev)) 679 return ATOM_ENCODER_MODE_DVI; 680 else 681 return ATOM_ENCODER_MODE_HDMI; 682 } else 683 return ATOM_ENCODER_MODE_DVI; 684 break; 685 case DRM_MODE_CONNECTOR_DVIA: 686 case DRM_MODE_CONNECTOR_VGA: 687 return ATOM_ENCODER_MODE_CRT; 688 break; 689 case DRM_MODE_CONNECTOR_Composite: 690 case DRM_MODE_CONNECTOR_SVIDEO: 691 case DRM_MODE_CONNECTOR_9PinDIN: 692 /* fix me */ 693 return ATOM_ENCODER_MODE_TV; 694 /*return ATOM_ENCODER_MODE_CV;*/ 695 break; 696 } 697 } 698 699 /* 700 * DIG Encoder/Transmitter Setup 701 * 702 * DCE 3.0/3.1 703 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 704 * Supports up to 3 digital outputs 705 * - 2 DIG encoder blocks. 706 * DIG1 can drive UNIPHY link A or link B 707 * DIG2 can drive UNIPHY link B or LVTMA 708 * 709 * DCE 3.2 710 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 711 * Supports up to 5 digital outputs 712 * - 2 DIG encoder blocks. 713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 714 * 715 * DCE 4.0/5.0 716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 717 * Supports up to 6 digital outputs 718 * - 6 DIG encoder blocks. 719 * - DIG to PHY mapping is hardcoded 720 * DIG1 drives UNIPHY0 link A, A+B 721 * DIG2 drives UNIPHY0 link B 722 * DIG3 drives UNIPHY1 link A, A+B 723 * DIG4 drives UNIPHY1 link B 724 * DIG5 drives UNIPHY2 link A, A+B 725 * DIG6 drives UNIPHY2 link B 726 * 727 * DCE 4.1 728 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 729 * Supports up to 6 digital outputs 730 * - 2 DIG encoder blocks. 731 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 732 * 733 * Routing 734 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 735 * Examples: 736 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 737 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 738 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 739 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 740 */ 741 742 union dig_encoder_control { 743 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 744 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 745 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 746 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 747 }; 748 749 void 750 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) 751 { 752 struct drm_device *dev = encoder->dev; 753 struct radeon_device *rdev = dev->dev_private; 754 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 755 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 756 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 757 union dig_encoder_control args; 758 int index = 0; 759 uint8_t frev, crev; 760 int dp_clock = 0; 761 int dp_lane_count = 0; 762 int hpd_id = RADEON_HPD_NONE; 763 764 if (connector) { 765 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 766 struct radeon_connector_atom_dig *dig_connector = 767 radeon_connector->con_priv; 768 769 dp_clock = dig_connector->dp_clock; 770 dp_lane_count = dig_connector->dp_lane_count; 771 hpd_id = radeon_connector->hpd.hpd; 772 } 773 774 /* no dig encoder assigned */ 775 if (dig->dig_encoder == -1) 776 return; 777 778 memset(&args, 0, sizeof(args)); 779 780 if (ASIC_IS_DCE4(rdev)) 781 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 782 else { 783 if (dig->dig_encoder) 784 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 785 else 786 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 787 } 788 789 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 790 return; 791 792 args.v1.ucAction = action; 793 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 794 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 795 796 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || 797 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) 798 args.v1.ucLaneNum = dp_lane_count; 799 else if (radeon_encoder->pixel_clock > 165000) 800 args.v1.ucLaneNum = 8; 801 else 802 args.v1.ucLaneNum = 4; 803 804 if (ASIC_IS_DCE5(rdev)) { 805 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || 806 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) { 807 if (dp_clock == 270000) 808 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 809 else if (dp_clock == 540000) 810 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 811 } 812 args.v4.acConfig.ucDigSel = dig->dig_encoder; 813 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 814 if (hpd_id == RADEON_HPD_NONE) 815 args.v4.ucHPD_ID = 0; 816 else 817 args.v4.ucHPD_ID = hpd_id + 1; 818 } else if (ASIC_IS_DCE4(rdev)) { 819 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) 820 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 821 args.v3.acConfig.ucDigSel = dig->dig_encoder; 822 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 823 } else { 824 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) 825 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 826 switch (radeon_encoder->encoder_id) { 827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 828 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 829 break; 830 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 831 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 832 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 833 break; 834 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 835 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 836 break; 837 } 838 if (dig->linkb) 839 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 840 else 841 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 842 } 843 844 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 845 846 } 847 848 union dig_transmitter_control { 849 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 850 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 851 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 852 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 853 }; 854 855 void 856 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 857 { 858 struct drm_device *dev = encoder->dev; 859 struct radeon_device *rdev = dev->dev_private; 860 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 861 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 862 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 863 union dig_transmitter_control args; 864 int index = 0; 865 uint8_t frev, crev; 866 bool is_dp = false; 867 int pll_id = 0; 868 int dp_clock = 0; 869 int dp_lane_count = 0; 870 int connector_object_id = 0; 871 int igp_lane_info = 0; 872 873 if (connector) { 874 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 875 struct radeon_connector_atom_dig *dig_connector = 876 radeon_connector->con_priv; 877 878 dp_clock = dig_connector->dp_clock; 879 dp_lane_count = dig_connector->dp_lane_count; 880 connector_object_id = 881 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 882 igp_lane_info = dig_connector->igp_lane_info; 883 } 884 885 /* no dig encoder assigned */ 886 if (dig->dig_encoder == -1) 887 return; 888 889 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 890 is_dp = true; 891 892 memset(&args, 0, sizeof(args)); 893 894 switch (radeon_encoder->encoder_id) { 895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 896 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 897 break; 898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 901 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 902 break; 903 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 904 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 905 break; 906 } 907 908 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 909 return; 910 911 args.v1.ucAction = action; 912 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 913 args.v1.usInitInfo = connector_object_id; 914 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 915 args.v1.asMode.ucLaneSel = lane_num; 916 args.v1.asMode.ucLaneSet = lane_set; 917 } else { 918 if (is_dp) 919 args.v1.usPixelClock = 920 cpu_to_le16(dp_clock / 10); 921 else if (radeon_encoder->pixel_clock > 165000) 922 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 923 else 924 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 925 } 926 if (ASIC_IS_DCE4(rdev)) { 927 if (is_dp) 928 args.v3.ucLaneNum = dp_lane_count; 929 else if (radeon_encoder->pixel_clock > 165000) 930 args.v3.ucLaneNum = 8; 931 else 932 args.v3.ucLaneNum = 4; 933 934 if (dig->linkb) { 935 args.v3.acConfig.ucLinkSel = 1; 936 args.v3.acConfig.ucEncoderSel = 1; 937 } 938 939 /* Select the PLL for the PHY 940 * DP PHY should be clocked from external src if there is 941 * one. 942 */ 943 if (encoder->crtc) { 944 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 945 pll_id = radeon_crtc->pll_id; 946 } 947 948 if (ASIC_IS_DCE5(rdev)) { 949 if (is_dp && rdev->clock.dp_extclk) 950 args.v4.acConfig.ucRefClkSource = 3; /* external src */ 951 else 952 args.v4.acConfig.ucRefClkSource = pll_id; 953 } else { 954 if (is_dp && rdev->clock.dp_extclk) 955 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 956 else 957 args.v3.acConfig.ucRefClkSource = pll_id; 958 } 959 960 switch (radeon_encoder->encoder_id) { 961 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 962 args.v3.acConfig.ucTransmitterSel = 0; 963 break; 964 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 965 args.v3.acConfig.ucTransmitterSel = 1; 966 break; 967 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 968 args.v3.acConfig.ucTransmitterSel = 2; 969 break; 970 } 971 972 if (is_dp) 973 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 974 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 975 if (dig->coherent_mode) 976 args.v3.acConfig.fCoherentMode = 1; 977 if (radeon_encoder->pixel_clock > 165000) 978 args.v3.acConfig.fDualLinkConnector = 1; 979 } 980 } else if (ASIC_IS_DCE32(rdev)) { 981 args.v2.acConfig.ucEncoderSel = dig->dig_encoder; 982 if (dig->linkb) 983 args.v2.acConfig.ucLinkSel = 1; 984 985 switch (radeon_encoder->encoder_id) { 986 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 987 args.v2.acConfig.ucTransmitterSel = 0; 988 break; 989 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 990 args.v2.acConfig.ucTransmitterSel = 1; 991 break; 992 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 993 args.v2.acConfig.ucTransmitterSel = 2; 994 break; 995 } 996 997 if (is_dp) 998 args.v2.acConfig.fCoherentMode = 1; 999 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1000 if (dig->coherent_mode) 1001 args.v2.acConfig.fCoherentMode = 1; 1002 if (radeon_encoder->pixel_clock > 165000) 1003 args.v2.acConfig.fDualLinkConnector = 1; 1004 } 1005 } else { 1006 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1007 1008 if (dig->dig_encoder) 1009 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1010 else 1011 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1012 1013 if ((rdev->flags & RADEON_IS_IGP) && 1014 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1015 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { 1016 if (igp_lane_info & 0x1) 1017 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1018 else if (igp_lane_info & 0x2) 1019 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1020 else if (igp_lane_info & 0x4) 1021 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1022 else if (igp_lane_info & 0x8) 1023 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1024 } else { 1025 if (igp_lane_info & 0x3) 1026 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1027 else if (igp_lane_info & 0xc) 1028 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1029 } 1030 } 1031 1032 if (dig->linkb) 1033 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1034 else 1035 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1036 1037 if (is_dp) 1038 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1039 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1040 if (dig->coherent_mode) 1041 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1042 if (radeon_encoder->pixel_clock > 165000) 1043 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1044 } 1045 } 1046 1047 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1048 } 1049 1050 void 1051 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1052 { 1053 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1054 struct drm_device *dev = radeon_connector->base.dev; 1055 struct radeon_device *rdev = dev->dev_private; 1056 union dig_transmitter_control args; 1057 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1058 uint8_t frev, crev; 1059 1060 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1061 return; 1062 1063 if (!ASIC_IS_DCE4(rdev)) 1064 return; 1065 1066 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) || 1067 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1068 return; 1069 1070 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1071 return; 1072 1073 memset(&args, 0, sizeof(args)); 1074 1075 args.v1.ucAction = action; 1076 1077 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1078 } 1079 1080 union external_encoder_control { 1081 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1082 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1083 }; 1084 1085 static void 1086 atombios_external_encoder_setup(struct drm_encoder *encoder, 1087 struct drm_encoder *ext_encoder, 1088 int action) 1089 { 1090 struct drm_device *dev = encoder->dev; 1091 struct radeon_device *rdev = dev->dev_private; 1092 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1093 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1094 union external_encoder_control args; 1095 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1096 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1097 u8 frev, crev; 1098 int dp_clock = 0; 1099 int dp_lane_count = 0; 1100 int connector_object_id = 0; 1101 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1102 1103 if (connector) { 1104 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1105 struct radeon_connector_atom_dig *dig_connector = 1106 radeon_connector->con_priv; 1107 1108 dp_clock = dig_connector->dp_clock; 1109 dp_lane_count = dig_connector->dp_lane_count; 1110 connector_object_id = 1111 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1112 } 1113 1114 memset(&args, 0, sizeof(args)); 1115 1116 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1117 return; 1118 1119 switch (frev) { 1120 case 1: 1121 /* no params on frev 1 */ 1122 break; 1123 case 2: 1124 switch (crev) { 1125 case 1: 1126 case 2: 1127 args.v1.sDigEncoder.ucAction = action; 1128 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1129 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1130 1131 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 1132 if (dp_clock == 270000) 1133 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1134 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1135 } else if (radeon_encoder->pixel_clock > 165000) 1136 args.v1.sDigEncoder.ucLaneNum = 8; 1137 else 1138 args.v1.sDigEncoder.ucLaneNum = 4; 1139 break; 1140 case 3: 1141 args.v3.sExtEncoder.ucAction = action; 1142 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1143 args.v3.sExtEncoder.usConnectorId = connector_object_id; 1144 else 1145 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1146 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1147 1148 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 1149 if (dp_clock == 270000) 1150 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1151 else if (dp_clock == 540000) 1152 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1153 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1154 } else if (radeon_encoder->pixel_clock > 165000) 1155 args.v3.sExtEncoder.ucLaneNum = 8; 1156 else 1157 args.v3.sExtEncoder.ucLaneNum = 4; 1158 switch (ext_enum) { 1159 case GRAPH_OBJECT_ENUM_ID1: 1160 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1161 break; 1162 case GRAPH_OBJECT_ENUM_ID2: 1163 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1164 break; 1165 case GRAPH_OBJECT_ENUM_ID3: 1166 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1167 break; 1168 } 1169 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; 1170 break; 1171 default: 1172 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1173 return; 1174 } 1175 break; 1176 default: 1177 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1178 return; 1179 } 1180 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1181 } 1182 1183 static void 1184 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1185 { 1186 struct drm_device *dev = encoder->dev; 1187 struct radeon_device *rdev = dev->dev_private; 1188 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1189 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1190 ENABLE_YUV_PS_ALLOCATION args; 1191 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1192 uint32_t temp, reg; 1193 1194 memset(&args, 0, sizeof(args)); 1195 1196 if (rdev->family >= CHIP_R600) 1197 reg = R600_BIOS_3_SCRATCH; 1198 else 1199 reg = RADEON_BIOS_3_SCRATCH; 1200 1201 /* XXX: fix up scratch reg handling */ 1202 temp = RREG32(reg); 1203 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1204 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1205 (radeon_crtc->crtc_id << 18))); 1206 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1207 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1208 else 1209 WREG32(reg, 0); 1210 1211 if (enable) 1212 args.ucEnable = ATOM_ENABLE; 1213 args.ucCRTC = radeon_crtc->crtc_id; 1214 1215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1216 1217 WREG32(reg, temp); 1218 } 1219 1220 static void 1221 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1222 { 1223 struct drm_device *dev = encoder->dev; 1224 struct radeon_device *rdev = dev->dev_private; 1225 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1226 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); 1227 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1228 int index = 0; 1229 bool is_dig = false; 1230 bool is_dce5_dac = false; 1231 bool is_dce5_dvo = false; 1232 1233 memset(&args, 0, sizeof(args)); 1234 1235 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1236 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1237 radeon_encoder->active_device); 1238 switch (radeon_encoder->encoder_id) { 1239 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1240 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1241 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1242 break; 1243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1246 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1247 is_dig = true; 1248 break; 1249 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1250 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1251 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1252 break; 1253 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1254 if (ASIC_IS_DCE5(rdev)) 1255 is_dce5_dvo = true; 1256 else if (ASIC_IS_DCE3(rdev)) 1257 is_dig = true; 1258 else 1259 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1260 break; 1261 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1262 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1263 break; 1264 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1265 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1266 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1267 else 1268 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1269 break; 1270 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1271 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1272 if (ASIC_IS_DCE5(rdev)) 1273 is_dce5_dac = true; 1274 else { 1275 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1276 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1277 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1278 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1279 else 1280 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1281 } 1282 break; 1283 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1284 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1285 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1286 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1287 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1288 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1289 else 1290 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1291 break; 1292 } 1293 1294 if (is_dig) { 1295 switch (mode) { 1296 case DRM_MODE_DPMS_ON: 1297 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1298 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1299 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1300 1301 if (connector && 1302 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1303 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1304 struct radeon_connector_atom_dig *radeon_dig_connector = 1305 radeon_connector->con_priv; 1306 atombios_set_edp_panel_power(connector, 1307 ATOM_TRANSMITTER_ACTION_POWER_ON); 1308 radeon_dig_connector->edp_on = true; 1309 } 1310 dp_link_train(encoder, connector); 1311 if (ASIC_IS_DCE4(rdev)) 1312 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); 1313 } 1314 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1315 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1316 break; 1317 case DRM_MODE_DPMS_STANDBY: 1318 case DRM_MODE_DPMS_SUSPEND: 1319 case DRM_MODE_DPMS_OFF: 1320 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1321 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { 1322 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1323 1324 if (ASIC_IS_DCE4(rdev)) 1325 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); 1326 if (connector && 1327 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 1328 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1329 struct radeon_connector_atom_dig *radeon_dig_connector = 1330 radeon_connector->con_priv; 1331 atombios_set_edp_panel_power(connector, 1332 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1333 radeon_dig_connector->edp_on = false; 1334 } 1335 } 1336 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1337 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1338 break; 1339 } 1340 } else if (is_dce5_dac) { 1341 switch (mode) { 1342 case DRM_MODE_DPMS_ON: 1343 atombios_dac_setup(encoder, ATOM_ENABLE); 1344 break; 1345 case DRM_MODE_DPMS_STANDBY: 1346 case DRM_MODE_DPMS_SUSPEND: 1347 case DRM_MODE_DPMS_OFF: 1348 atombios_dac_setup(encoder, ATOM_DISABLE); 1349 break; 1350 } 1351 } else if (is_dce5_dvo) { 1352 switch (mode) { 1353 case DRM_MODE_DPMS_ON: 1354 atombios_dvo_setup(encoder, ATOM_ENABLE); 1355 break; 1356 case DRM_MODE_DPMS_STANDBY: 1357 case DRM_MODE_DPMS_SUSPEND: 1358 case DRM_MODE_DPMS_OFF: 1359 atombios_dvo_setup(encoder, ATOM_DISABLE); 1360 break; 1361 } 1362 } else { 1363 switch (mode) { 1364 case DRM_MODE_DPMS_ON: 1365 args.ucAction = ATOM_ENABLE; 1366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1367 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1368 args.ucAction = ATOM_LCD_BLON; 1369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1370 } 1371 break; 1372 case DRM_MODE_DPMS_STANDBY: 1373 case DRM_MODE_DPMS_SUSPEND: 1374 case DRM_MODE_DPMS_OFF: 1375 args.ucAction = ATOM_DISABLE; 1376 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1377 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1378 args.ucAction = ATOM_LCD_BLOFF; 1379 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1380 } 1381 break; 1382 } 1383 } 1384 1385 if (ext_encoder) { 1386 int action; 1387 1388 switch (mode) { 1389 case DRM_MODE_DPMS_ON: 1390 default: 1391 if (ASIC_IS_DCE41(rdev)) 1392 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; 1393 else 1394 action = ATOM_ENABLE; 1395 break; 1396 case DRM_MODE_DPMS_STANDBY: 1397 case DRM_MODE_DPMS_SUSPEND: 1398 case DRM_MODE_DPMS_OFF: 1399 if (ASIC_IS_DCE41(rdev)) 1400 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; 1401 else 1402 action = ATOM_DISABLE; 1403 break; 1404 } 1405 atombios_external_encoder_setup(encoder, ext_encoder, action); 1406 } 1407 1408 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1409 1410 } 1411 1412 union crtc_source_param { 1413 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1414 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1415 }; 1416 1417 static void 1418 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1419 { 1420 struct drm_device *dev = encoder->dev; 1421 struct radeon_device *rdev = dev->dev_private; 1422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1423 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1424 union crtc_source_param args; 1425 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1426 uint8_t frev, crev; 1427 struct radeon_encoder_atom_dig *dig; 1428 1429 memset(&args, 0, sizeof(args)); 1430 1431 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1432 return; 1433 1434 switch (frev) { 1435 case 1: 1436 switch (crev) { 1437 case 1: 1438 default: 1439 if (ASIC_IS_AVIVO(rdev)) 1440 args.v1.ucCRTC = radeon_crtc->crtc_id; 1441 else { 1442 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1443 args.v1.ucCRTC = radeon_crtc->crtc_id; 1444 } else { 1445 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1446 } 1447 } 1448 switch (radeon_encoder->encoder_id) { 1449 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1450 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1451 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1452 break; 1453 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1454 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1455 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1456 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1457 else 1458 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1459 break; 1460 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1461 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1462 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1463 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1464 break; 1465 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1466 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1467 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1468 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1469 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1470 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1471 else 1472 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1473 break; 1474 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1475 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1476 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1477 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1478 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1479 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1480 else 1481 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1482 break; 1483 } 1484 break; 1485 case 2: 1486 args.v2.ucCRTC = radeon_crtc->crtc_id; 1487 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1488 switch (radeon_encoder->encoder_id) { 1489 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1490 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1491 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1492 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1493 dig = radeon_encoder->enc_priv; 1494 switch (dig->dig_encoder) { 1495 case 0: 1496 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1497 break; 1498 case 1: 1499 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1500 break; 1501 case 2: 1502 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1503 break; 1504 case 3: 1505 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1506 break; 1507 case 4: 1508 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1509 break; 1510 case 5: 1511 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1512 break; 1513 } 1514 break; 1515 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1516 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1517 break; 1518 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1519 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1520 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1521 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1522 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1523 else 1524 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1525 break; 1526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1527 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1528 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1529 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1530 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1531 else 1532 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1533 break; 1534 } 1535 break; 1536 } 1537 break; 1538 default: 1539 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1540 return; 1541 } 1542 1543 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1544 1545 /* update scratch regs with new routing */ 1546 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1547 } 1548 1549 static void 1550 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1551 struct drm_display_mode *mode) 1552 { 1553 struct drm_device *dev = encoder->dev; 1554 struct radeon_device *rdev = dev->dev_private; 1555 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1556 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1557 1558 /* Funky macbooks */ 1559 if ((dev->pdev->device == 0x71C5) && 1560 (dev->pdev->subsystem_vendor == 0x106b) && 1561 (dev->pdev->subsystem_device == 0x0080)) { 1562 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1563 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1564 1565 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1566 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1567 1568 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1569 } 1570 } 1571 1572 /* set scaler clears this on some chips */ 1573 /* XXX check DCE4 */ 1574 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { 1575 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) 1576 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1577 AVIVO_D1MODE_INTERLEAVE_EN); 1578 } 1579 } 1580 1581 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1582 { 1583 struct drm_device *dev = encoder->dev; 1584 struct radeon_device *rdev = dev->dev_private; 1585 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1586 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1587 struct drm_encoder *test_encoder; 1588 struct radeon_encoder_atom_dig *dig; 1589 uint32_t dig_enc_in_use = 0; 1590 1591 /* DCE4/5 */ 1592 if (ASIC_IS_DCE4(rdev)) { 1593 dig = radeon_encoder->enc_priv; 1594 if (ASIC_IS_DCE41(rdev)) { 1595 if (dig->linkb) 1596 return 1; 1597 else 1598 return 0; 1599 } else { 1600 switch (radeon_encoder->encoder_id) { 1601 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1602 if (dig->linkb) 1603 return 1; 1604 else 1605 return 0; 1606 break; 1607 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1608 if (dig->linkb) 1609 return 3; 1610 else 1611 return 2; 1612 break; 1613 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1614 if (dig->linkb) 1615 return 5; 1616 else 1617 return 4; 1618 break; 1619 } 1620 } 1621 } 1622 1623 /* on DCE32 and encoder can driver any block so just crtc id */ 1624 if (ASIC_IS_DCE32(rdev)) { 1625 return radeon_crtc->crtc_id; 1626 } 1627 1628 /* on DCE3 - LVTMA can only be driven by DIGB */ 1629 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1630 struct radeon_encoder *radeon_test_encoder; 1631 1632 if (encoder == test_encoder) 1633 continue; 1634 1635 if (!radeon_encoder_is_digital(test_encoder)) 1636 continue; 1637 1638 radeon_test_encoder = to_radeon_encoder(test_encoder); 1639 dig = radeon_test_encoder->enc_priv; 1640 1641 if (dig->dig_encoder >= 0) 1642 dig_enc_in_use |= (1 << dig->dig_encoder); 1643 } 1644 1645 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 1646 if (dig_enc_in_use & 0x2) 1647 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 1648 return 1; 1649 } 1650 if (!(dig_enc_in_use & 1)) 1651 return 0; 1652 return 1; 1653 } 1654 1655 static void 1656 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1657 struct drm_display_mode *mode, 1658 struct drm_display_mode *adjusted_mode) 1659 { 1660 struct drm_device *dev = encoder->dev; 1661 struct radeon_device *rdev = dev->dev_private; 1662 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1663 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); 1664 1665 radeon_encoder->pixel_clock = adjusted_mode->clock; 1666 1667 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1668 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1669 atombios_yuv_setup(encoder, true); 1670 else 1671 atombios_yuv_setup(encoder, false); 1672 } 1673 1674 switch (radeon_encoder->encoder_id) { 1675 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1676 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1677 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1678 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1679 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1680 break; 1681 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1682 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1683 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1684 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1685 if (ASIC_IS_DCE4(rdev)) { 1686 /* disable the transmitter */ 1687 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1688 /* setup and enable the encoder */ 1689 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); 1690 1691 /* init and enable the transmitter */ 1692 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1693 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1694 } else { 1695 /* disable the encoder and transmitter */ 1696 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1697 atombios_dig_encoder_setup(encoder, ATOM_DISABLE); 1698 1699 /* setup and enable the encoder and transmitter */ 1700 atombios_dig_encoder_setup(encoder, ATOM_ENABLE); 1701 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1702 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1703 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1704 } 1705 break; 1706 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1707 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1708 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1709 atombios_dvo_setup(encoder, ATOM_ENABLE); 1710 break; 1711 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1712 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1713 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1714 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1715 atombios_dac_setup(encoder, ATOM_ENABLE); 1716 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 1717 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1718 atombios_tv_setup(encoder, ATOM_ENABLE); 1719 else 1720 atombios_tv_setup(encoder, ATOM_DISABLE); 1721 } 1722 break; 1723 } 1724 1725 if (ext_encoder) { 1726 if (ASIC_IS_DCE41(rdev)) { 1727 atombios_external_encoder_setup(encoder, ext_encoder, 1728 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 1729 atombios_external_encoder_setup(encoder, ext_encoder, 1730 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1731 } else 1732 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1733 } 1734 1735 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1736 1737 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1738 r600_hdmi_enable(encoder); 1739 r600_hdmi_setmode(encoder, adjusted_mode); 1740 } 1741 } 1742 1743 static bool 1744 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1745 { 1746 struct drm_device *dev = encoder->dev; 1747 struct radeon_device *rdev = dev->dev_private; 1748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1749 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1750 1751 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1752 ATOM_DEVICE_CV_SUPPORT | 1753 ATOM_DEVICE_CRT_SUPPORT)) { 1754 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1755 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1756 uint8_t frev, crev; 1757 1758 memset(&args, 0, sizeof(args)); 1759 1760 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1761 return false; 1762 1763 args.sDacload.ucMisc = 0; 1764 1765 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1766 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1767 args.sDacload.ucDacType = ATOM_DAC_A; 1768 else 1769 args.sDacload.ucDacType = ATOM_DAC_B; 1770 1771 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1772 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1773 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1774 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1775 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1776 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1777 if (crev >= 3) 1778 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1779 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1780 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1781 if (crev >= 3) 1782 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1783 } 1784 1785 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1786 1787 return true; 1788 } else 1789 return false; 1790 } 1791 1792 static enum drm_connector_status 1793 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1794 { 1795 struct drm_device *dev = encoder->dev; 1796 struct radeon_device *rdev = dev->dev_private; 1797 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1798 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1799 uint32_t bios_0_scratch; 1800 1801 if (!atombios_dac_load_detect(encoder, connector)) { 1802 DRM_DEBUG_KMS("detect returned false \n"); 1803 return connector_status_unknown; 1804 } 1805 1806 if (rdev->family >= CHIP_R600) 1807 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1808 else 1809 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1810 1811 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1812 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1813 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1814 return connector_status_connected; 1815 } 1816 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1817 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1818 return connector_status_connected; 1819 } 1820 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1821 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1822 return connector_status_connected; 1823 } 1824 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1825 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1826 return connector_status_connected; /* CTV */ 1827 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1828 return connector_status_connected; /* STV */ 1829 } 1830 return connector_status_disconnected; 1831 } 1832 1833 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 1834 { 1835 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1836 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1837 1838 if (radeon_encoder->active_device & 1839 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { 1840 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1841 if (dig) 1842 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 1843 } 1844 1845 radeon_atom_output_lock(encoder, true); 1846 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1847 1848 /* select the clock/data port if it uses a router */ 1849 if (connector) { 1850 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1851 if (radeon_connector->router.cd_valid) 1852 radeon_router_select_cd_port(radeon_connector); 1853 } 1854 1855 /* this is needed for the pll/ss setup to work correctly in some cases */ 1856 atombios_set_encoder_crtc_source(encoder); 1857 } 1858 1859 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 1860 { 1861 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 1862 radeon_atom_output_lock(encoder, false); 1863 } 1864 1865 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 1866 { 1867 struct drm_device *dev = encoder->dev; 1868 struct radeon_device *rdev = dev->dev_private; 1869 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1870 struct radeon_encoder_atom_dig *dig; 1871 1872 /* check for pre-DCE3 cards with shared encoders; 1873 * can't really use the links individually, so don't disable 1874 * the encoder if it's in use by another connector 1875 */ 1876 if (!ASIC_IS_DCE3(rdev)) { 1877 struct drm_encoder *other_encoder; 1878 struct radeon_encoder *other_radeon_encoder; 1879 1880 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 1881 other_radeon_encoder = to_radeon_encoder(other_encoder); 1882 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 1883 drm_helper_encoder_in_use(other_encoder)) 1884 goto disable_done; 1885 } 1886 } 1887 1888 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1889 1890 switch (radeon_encoder->encoder_id) { 1891 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1893 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1894 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1895 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 1896 break; 1897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1901 if (ASIC_IS_DCE4(rdev)) 1902 /* disable the transmitter */ 1903 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1904 else { 1905 /* disable the encoder and transmitter */ 1906 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1907 atombios_dig_encoder_setup(encoder, ATOM_DISABLE); 1908 } 1909 break; 1910 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1911 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1912 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1913 atombios_dvo_setup(encoder, ATOM_DISABLE); 1914 break; 1915 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1917 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1918 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1919 atombios_dac_setup(encoder, ATOM_DISABLE); 1920 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1921 atombios_tv_setup(encoder, ATOM_DISABLE); 1922 break; 1923 } 1924 1925 disable_done: 1926 if (radeon_encoder_is_digital(encoder)) { 1927 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 1928 r600_hdmi_disable(encoder); 1929 dig = radeon_encoder->enc_priv; 1930 dig->dig_encoder = -1; 1931 } 1932 radeon_encoder->active_device = 0; 1933 } 1934 1935 /* these are handled by the primary encoders */ 1936 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 1937 { 1938 1939 } 1940 1941 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 1942 { 1943 1944 } 1945 1946 static void 1947 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 1948 struct drm_display_mode *mode, 1949 struct drm_display_mode *adjusted_mode) 1950 { 1951 1952 } 1953 1954 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 1955 { 1956 1957 } 1958 1959 static void 1960 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 1961 { 1962 1963 } 1964 1965 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 1966 struct drm_display_mode *mode, 1967 struct drm_display_mode *adjusted_mode) 1968 { 1969 return true; 1970 } 1971 1972 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 1973 .dpms = radeon_atom_ext_dpms, 1974 .mode_fixup = radeon_atom_ext_mode_fixup, 1975 .prepare = radeon_atom_ext_prepare, 1976 .mode_set = radeon_atom_ext_mode_set, 1977 .commit = radeon_atom_ext_commit, 1978 .disable = radeon_atom_ext_disable, 1979 /* no detect for TMDS/LVDS yet */ 1980 }; 1981 1982 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 1983 .dpms = radeon_atom_encoder_dpms, 1984 .mode_fixup = radeon_atom_mode_fixup, 1985 .prepare = radeon_atom_encoder_prepare, 1986 .mode_set = radeon_atom_encoder_mode_set, 1987 .commit = radeon_atom_encoder_commit, 1988 .disable = radeon_atom_encoder_disable, 1989 /* no detect for TMDS/LVDS yet */ 1990 }; 1991 1992 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 1993 .dpms = radeon_atom_encoder_dpms, 1994 .mode_fixup = radeon_atom_mode_fixup, 1995 .prepare = radeon_atom_encoder_prepare, 1996 .mode_set = radeon_atom_encoder_mode_set, 1997 .commit = radeon_atom_encoder_commit, 1998 .detect = radeon_atom_dac_detect, 1999 }; 2000 2001 void radeon_enc_destroy(struct drm_encoder *encoder) 2002 { 2003 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2004 kfree(radeon_encoder->enc_priv); 2005 drm_encoder_cleanup(encoder); 2006 kfree(radeon_encoder); 2007 } 2008 2009 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2010 .destroy = radeon_enc_destroy, 2011 }; 2012 2013 struct radeon_encoder_atom_dac * 2014 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2015 { 2016 struct drm_device *dev = radeon_encoder->base.dev; 2017 struct radeon_device *rdev = dev->dev_private; 2018 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2019 2020 if (!dac) 2021 return NULL; 2022 2023 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2024 return dac; 2025 } 2026 2027 struct radeon_encoder_atom_dig * 2028 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2029 { 2030 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2031 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2032 2033 if (!dig) 2034 return NULL; 2035 2036 /* coherent mode by default */ 2037 dig->coherent_mode = true; 2038 dig->dig_encoder = -1; 2039 2040 if (encoder_enum == 2) 2041 dig->linkb = true; 2042 else 2043 dig->linkb = false; 2044 2045 return dig; 2046 } 2047 2048 void 2049 radeon_add_atom_encoder(struct drm_device *dev, 2050 uint32_t encoder_enum, 2051 uint32_t supported_device, 2052 u16 caps) 2053 { 2054 struct radeon_device *rdev = dev->dev_private; 2055 struct drm_encoder *encoder; 2056 struct radeon_encoder *radeon_encoder; 2057 2058 /* see if we already added it */ 2059 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2060 radeon_encoder = to_radeon_encoder(encoder); 2061 if (radeon_encoder->encoder_enum == encoder_enum) { 2062 radeon_encoder->devices |= supported_device; 2063 return; 2064 } 2065 2066 } 2067 2068 /* add a new one */ 2069 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2070 if (!radeon_encoder) 2071 return; 2072 2073 encoder = &radeon_encoder->base; 2074 switch (rdev->num_crtc) { 2075 case 1: 2076 encoder->possible_crtcs = 0x1; 2077 break; 2078 case 2: 2079 default: 2080 encoder->possible_crtcs = 0x3; 2081 break; 2082 case 6: 2083 encoder->possible_crtcs = 0x3f; 2084 break; 2085 } 2086 2087 radeon_encoder->enc_priv = NULL; 2088 2089 radeon_encoder->encoder_enum = encoder_enum; 2090 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2091 radeon_encoder->devices = supported_device; 2092 radeon_encoder->rmx_type = RMX_OFF; 2093 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2094 radeon_encoder->is_ext_encoder = false; 2095 radeon_encoder->caps = caps; 2096 2097 switch (radeon_encoder->encoder_id) { 2098 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2099 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2100 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2101 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2102 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2103 radeon_encoder->rmx_type = RMX_FULL; 2104 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2105 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2106 } else { 2107 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2108 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2109 if (ASIC_IS_AVIVO(rdev)) 2110 radeon_encoder->underscan_type = UNDERSCAN_AUTO; 2111 } 2112 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2113 break; 2114 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2115 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2116 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2117 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2118 break; 2119 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2121 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2122 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2123 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2124 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2125 break; 2126 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2127 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2128 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2129 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2130 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2133 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2134 radeon_encoder->rmx_type = RMX_FULL; 2135 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2136 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2137 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2138 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2139 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2140 } else { 2141 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2142 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2143 if (ASIC_IS_AVIVO(rdev)) 2144 radeon_encoder->underscan_type = UNDERSCAN_AUTO; 2145 } 2146 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2147 break; 2148 case ENCODER_OBJECT_ID_SI170B: 2149 case ENCODER_OBJECT_ID_CH7303: 2150 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2151 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2152 case ENCODER_OBJECT_ID_TITFP513: 2153 case ENCODER_OBJECT_ID_VT1623: 2154 case ENCODER_OBJECT_ID_HDMI_SI1930: 2155 case ENCODER_OBJECT_ID_TRAVIS: 2156 case ENCODER_OBJECT_ID_NUTMEG: 2157 /* these are handled by the primary encoders */ 2158 radeon_encoder->is_ext_encoder = true; 2159 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2160 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2161 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2162 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2163 else 2164 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2165 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2166 break; 2167 } 2168 } 2169