1 /**
2  * \file radeon_drv.c
3  * ATI Radeon driver
4  *
5  * \author Gareth Hughes <gareth@valinux.com>
6  */
7 
8 /*
9  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice (including the next
20  * paragraph) shall be included in all copies or substantial portions of the
21  * Software.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
26  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29  * OTHER DEALINGS IN THE SOFTWARE.
30  */
31 
32 #include <drm/drmP.h>
33 #include <drm/radeon_drm.h>
34 #include "radeon_drv.h"
35 
36 #include <drm/drm_pciids.h>
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/vga_switcheroo.h>
41 #include <drm/drm_gem.h>
42 #include <drm/drm_fb_helper.h>
43 
44 #include "drm_crtc_helper.h"
45 #include "radeon_kfd.h"
46 
47 /*
48  * KMS wrapper.
49  * - 2.0.0 - initial interface
50  * - 2.1.0 - add square tiling interface
51  * - 2.2.0 - add r6xx/r7xx const buffer support
52  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
53  * - 2.4.0 - add crtc id query
54  * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
55  * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
56  *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
57  *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
58  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
59  *   2.10.0 - fusion 2D tiling
60  *   2.11.0 - backend map, initial compute support for the CS checker
61  *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
62  *   2.13.0 - virtual memory support, streamout
63  *   2.14.0 - add evergreen tiling informations
64  *   2.15.0 - add max_pipes query
65  *   2.16.0 - fix evergreen 2D tiled surface calculation
66  *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
67  *   2.18.0 - r600-eg: allow "invalid" DB formats
68  *   2.19.0 - r600-eg: MSAA textures
69  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
70  *   2.21.0 - r600-r700: FMASK and CMASK
71  *   2.22.0 - r600 only: RESOLVE_BOX allowed
72  *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
73  *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
74  *   2.25.0 - eg+: new info request for num SE and num SH
75  *   2.26.0 - r600-eg: fix htile size computation
76  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
77  *   2.28.0 - r600-eg: Add MEM_WRITE packet support
78  *   2.29.0 - R500 FP16 color clear registers
79  *   2.30.0 - fix for FMASK texturing
80  *   2.31.0 - Add fastfb support for rs690
81  *   2.32.0 - new info request for rings working
82  *   2.33.0 - Add SI tiling mode array query
83  *   2.34.0 - Add CIK tiling mode array query
84  *   2.35.0 - Add CIK macrotile mode array query
85  *   2.36.0 - Fix CIK DCE tiling setup
86  *   2.37.0 - allow GS ring setup on r6xx/r7xx
87  *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
88  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
89  *   2.39.0 - Add INFO query for number of active CUs
90  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
91  *            CS to GPU on >= r600
92  *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
93  *   2.42.0 - Add VCE/VUI (Video Usability Information) support
94  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
95  *   2.44.0 - SET_APPEND_CNT packet3 support
96  *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
97  *   2.46.0 - Add PFP_SYNC_ME support on evergreen
98  *   2.47.0 - Add UVD_NO_OP register support
99  *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
100  */
101 #define KMS_DRIVER_MAJOR	2
102 #define KMS_DRIVER_MINOR	48
103 #define KMS_DRIVER_PATCHLEVEL	0
104 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
105 int radeon_driver_unload_kms(struct drm_device *dev);
106 void radeon_driver_lastclose_kms(struct drm_device *dev);
107 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
108 void radeon_driver_postclose_kms(struct drm_device *dev,
109 				 struct drm_file *file_priv);
110 void radeon_driver_preclose_kms(struct drm_device *dev,
111 				struct drm_file *file_priv);
112 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
113 		       bool fbcon, bool freeze);
114 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
115 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
116 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
117 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
118 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
119 				    int *max_error,
120 				    struct timeval *vblank_time,
121 				    unsigned flags);
122 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
123 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
124 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
125 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
126 void radeon_gem_object_free(struct drm_gem_object *obj);
127 int radeon_gem_object_open(struct drm_gem_object *obj,
128 				struct drm_file *file_priv);
129 void radeon_gem_object_close(struct drm_gem_object *obj,
130 				struct drm_file *file_priv);
131 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
132 					struct drm_gem_object *gobj,
133 					int flags);
134 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
135 				      unsigned int flags, int *vpos, int *hpos,
136 				      ktime_t *stime, ktime_t *etime,
137 				      const struct drm_display_mode *mode);
138 extern bool radeon_is_px(struct drm_device *dev);
139 extern const struct drm_ioctl_desc radeon_ioctls_kms[];
140 extern int radeon_max_kms_ioctl;
141 int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
142 int radeon_mode_dumb_mmap(struct drm_file *filp,
143 			  struct drm_device *dev,
144 			  uint32_t handle, uint64_t *offset_p);
145 int radeon_mode_dumb_create(struct drm_file *file_priv,
146 			    struct drm_device *dev,
147 			    struct drm_mode_create_dumb *args);
148 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
149 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
150 							struct dma_buf_attachment *,
151 							struct sg_table *sg);
152 int radeon_gem_prime_pin(struct drm_gem_object *obj);
153 void radeon_gem_prime_unpin(struct drm_gem_object *obj);
154 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
155 void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
156 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
157 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
158 				    unsigned long arg);
159 
160 /* atpx handler */
161 #if defined(CONFIG_VGA_SWITCHEROO)
162 void radeon_register_atpx_handler(void);
163 void radeon_unregister_atpx_handler(void);
164 bool radeon_has_atpx_dgpu_power_cntl(void);
165 bool radeon_is_atpx_hybrid(void);
166 #else
167 static inline void radeon_register_atpx_handler(void) {}
168 static inline void radeon_unregister_atpx_handler(void) {}
169 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
170 static inline bool radeon_is_atpx_hybrid(void) { return false; }
171 #endif
172 
173 int radeon_no_wb;
174 int radeon_modeset = -1;
175 int radeon_dynclks = -1;
176 int radeon_r4xx_atom = 0;
177 int radeon_agpmode = 0;
178 int radeon_vram_limit = 0;
179 int radeon_gart_size = -1; /* auto */
180 int radeon_benchmarking = 0;
181 int radeon_testing = 0;
182 int radeon_connector_table = 0;
183 int radeon_tv = 1;
184 int radeon_audio = -1;
185 int radeon_disp_priority = 0;
186 int radeon_hw_i2c = 0;
187 int radeon_pcie_gen2 = -1;
188 int radeon_msi = -1;
189 int radeon_lockup_timeout = 10000;
190 int radeon_fastfb = 0;
191 int radeon_dpm = -1;
192 int radeon_aspm = -1;
193 int radeon_runtime_pm = -1;
194 int radeon_hard_reset = 0;
195 int radeon_vm_size = 8;
196 int radeon_vm_block_size = -1;
197 int radeon_deep_color = 0;
198 int radeon_use_pflipirq = 2;
199 int radeon_bapm = -1;
200 int radeon_backlight = -1;
201 int radeon_auxch = -1;
202 int radeon_mst = 0;
203 int radeon_uvd = 1;
204 int radeon_vce = 1;
205 
206 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
207 module_param_named(no_wb, radeon_no_wb, int, 0444);
208 
209 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
210 module_param_named(modeset, radeon_modeset, int, 0400);
211 
212 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
213 module_param_named(dynclks, radeon_dynclks, int, 0444);
214 
215 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
216 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
217 
218 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
219 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
220 
221 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
222 module_param_named(agpmode, radeon_agpmode, int, 0444);
223 
224 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
225 module_param_named(gartsize, radeon_gart_size, int, 0600);
226 
227 MODULE_PARM_DESC(benchmark, "Run benchmark");
228 module_param_named(benchmark, radeon_benchmarking, int, 0444);
229 
230 MODULE_PARM_DESC(test, "Run tests");
231 module_param_named(test, radeon_testing, int, 0444);
232 
233 MODULE_PARM_DESC(connector_table, "Force connector table");
234 module_param_named(connector_table, radeon_connector_table, int, 0444);
235 
236 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
237 module_param_named(tv, radeon_tv, int, 0444);
238 
239 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
240 module_param_named(audio, radeon_audio, int, 0444);
241 
242 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
243 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
244 
245 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
246 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
247 
248 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
249 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
250 
251 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
252 module_param_named(msi, radeon_msi, int, 0444);
253 
254 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
255 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
256 
257 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
258 module_param_named(fastfb, radeon_fastfb, int, 0444);
259 
260 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
261 module_param_named(dpm, radeon_dpm, int, 0444);
262 
263 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
264 module_param_named(aspm, radeon_aspm, int, 0444);
265 
266 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
267 module_param_named(runpm, radeon_runtime_pm, int, 0444);
268 
269 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
270 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
271 
272 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
273 module_param_named(vm_size, radeon_vm_size, int, 0444);
274 
275 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
276 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
277 
278 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
279 module_param_named(deep_color, radeon_deep_color, int, 0444);
280 
281 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
282 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
283 
284 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
285 module_param_named(bapm, radeon_bapm, int, 0444);
286 
287 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
288 module_param_named(backlight, radeon_backlight, int, 0444);
289 
290 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
291 module_param_named(auxch, radeon_auxch, int, 0444);
292 
293 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
294 module_param_named(mst, radeon_mst, int, 0444);
295 
296 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
297 module_param_named(uvd, radeon_uvd, int, 0444);
298 
299 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
300 module_param_named(vce, radeon_vce, int, 0444);
301 
302 static struct pci_device_id pciidlist[] = {
303 	radeon_PCI_IDS
304 };
305 
306 MODULE_DEVICE_TABLE(pci, pciidlist);
307 
308 static struct drm_driver kms_driver;
309 
310 bool radeon_device_is_virtual(void);
311 
312 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
313 {
314 	struct apertures_struct *ap;
315 	bool primary = false;
316 
317 	ap = alloc_apertures(1);
318 	if (!ap)
319 		return -ENOMEM;
320 
321 	ap->ranges[0].base = pci_resource_start(pdev, 0);
322 	ap->ranges[0].size = pci_resource_len(pdev, 0);
323 
324 #ifdef CONFIG_X86
325 	primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
326 #endif
327 	drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
328 	kfree(ap);
329 
330 	return 0;
331 }
332 
333 static int radeon_pci_probe(struct pci_dev *pdev,
334 			    const struct pci_device_id *ent)
335 {
336 	int ret;
337 
338 	/*
339 	 * Initialize amdkfd before starting radeon. If it was not loaded yet,
340 	 * defer radeon probing
341 	 */
342 	ret = radeon_kfd_init();
343 	if (ret == -EPROBE_DEFER)
344 		return ret;
345 
346 	if (vga_switcheroo_client_probe_defer(pdev))
347 		return -EPROBE_DEFER;
348 
349 	/* Get rid of things like offb */
350 	ret = radeon_kick_out_firmware_fb(pdev);
351 	if (ret)
352 		return ret;
353 
354 	return drm_get_pci_dev(pdev, ent, &kms_driver);
355 }
356 
357 static void
358 radeon_pci_remove(struct pci_dev *pdev)
359 {
360 	struct drm_device *dev = pci_get_drvdata(pdev);
361 
362 	drm_put_dev(dev);
363 }
364 
365 static void
366 radeon_pci_shutdown(struct pci_dev *pdev)
367 {
368 	/* if we are running in a VM, make sure the device
369 	 * torn down properly on reboot/shutdown.
370 	 * unfortunately we can't detect certain
371 	 * hypervisors so just do this all the time.
372 	 */
373 	radeon_pci_remove(pdev);
374 }
375 
376 static int radeon_pmops_suspend(struct device *dev)
377 {
378 	struct pci_dev *pdev = to_pci_dev(dev);
379 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
380 	return radeon_suspend_kms(drm_dev, true, true, false);
381 }
382 
383 static int radeon_pmops_resume(struct device *dev)
384 {
385 	struct pci_dev *pdev = to_pci_dev(dev);
386 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
387 
388 	/* GPU comes up enabled by the bios on resume */
389 	if (radeon_is_px(drm_dev)) {
390 		pm_runtime_disable(dev);
391 		pm_runtime_set_active(dev);
392 		pm_runtime_enable(dev);
393 	}
394 
395 	return radeon_resume_kms(drm_dev, true, true);
396 }
397 
398 static int radeon_pmops_freeze(struct device *dev)
399 {
400 	struct pci_dev *pdev = to_pci_dev(dev);
401 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
402 	return radeon_suspend_kms(drm_dev, false, true, true);
403 }
404 
405 static int radeon_pmops_thaw(struct device *dev)
406 {
407 	struct pci_dev *pdev = to_pci_dev(dev);
408 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
409 	return radeon_resume_kms(drm_dev, false, true);
410 }
411 
412 static int radeon_pmops_runtime_suspend(struct device *dev)
413 {
414 	struct pci_dev *pdev = to_pci_dev(dev);
415 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
416 	int ret;
417 
418 	if (!radeon_is_px(drm_dev)) {
419 		pm_runtime_forbid(dev);
420 		return -EBUSY;
421 	}
422 
423 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
424 	drm_kms_helper_poll_disable(drm_dev);
425 	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
426 
427 	ret = radeon_suspend_kms(drm_dev, false, false, false);
428 	pci_save_state(pdev);
429 	pci_disable_device(pdev);
430 	pci_ignore_hotplug(pdev);
431 	if (radeon_is_atpx_hybrid())
432 		pci_set_power_state(pdev, PCI_D3cold);
433 	else if (!radeon_has_atpx_dgpu_power_cntl())
434 		pci_set_power_state(pdev, PCI_D3hot);
435 	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
436 
437 	return 0;
438 }
439 
440 static int radeon_pmops_runtime_resume(struct device *dev)
441 {
442 	struct pci_dev *pdev = to_pci_dev(dev);
443 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
444 	int ret;
445 
446 	if (!radeon_is_px(drm_dev))
447 		return -EINVAL;
448 
449 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
450 
451 	if (radeon_is_atpx_hybrid() ||
452 	    !radeon_has_atpx_dgpu_power_cntl())
453 		pci_set_power_state(pdev, PCI_D0);
454 	pci_restore_state(pdev);
455 	ret = pci_enable_device(pdev);
456 	if (ret)
457 		return ret;
458 	pci_set_master(pdev);
459 
460 	ret = radeon_resume_kms(drm_dev, false, false);
461 	drm_kms_helper_poll_enable(drm_dev);
462 	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
463 	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
464 	return 0;
465 }
466 
467 static int radeon_pmops_runtime_idle(struct device *dev)
468 {
469 	struct pci_dev *pdev = to_pci_dev(dev);
470 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
471 	struct drm_crtc *crtc;
472 
473 	if (!radeon_is_px(drm_dev)) {
474 		pm_runtime_forbid(dev);
475 		return -EBUSY;
476 	}
477 
478 	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
479 		if (crtc->enabled) {
480 			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
481 			return -EBUSY;
482 		}
483 	}
484 
485 	pm_runtime_mark_last_busy(dev);
486 	pm_runtime_autosuspend(dev);
487 	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
488 	return 1;
489 }
490 
491 long radeon_drm_ioctl(struct file *filp,
492 		      unsigned int cmd, unsigned long arg)
493 {
494 	struct drm_file *file_priv = filp->private_data;
495 	struct drm_device *dev;
496 	long ret;
497 	dev = file_priv->minor->dev;
498 	ret = pm_runtime_get_sync(dev->dev);
499 	if (ret < 0)
500 		return ret;
501 
502 	ret = drm_ioctl(filp, cmd, arg);
503 
504 	pm_runtime_mark_last_busy(dev->dev);
505 	pm_runtime_put_autosuspend(dev->dev);
506 	return ret;
507 }
508 
509 static const struct dev_pm_ops radeon_pm_ops = {
510 	.suspend = radeon_pmops_suspend,
511 	.resume = radeon_pmops_resume,
512 	.freeze = radeon_pmops_freeze,
513 	.thaw = radeon_pmops_thaw,
514 	.poweroff = radeon_pmops_freeze,
515 	.restore = radeon_pmops_resume,
516 	.runtime_suspend = radeon_pmops_runtime_suspend,
517 	.runtime_resume = radeon_pmops_runtime_resume,
518 	.runtime_idle = radeon_pmops_runtime_idle,
519 };
520 
521 static const struct file_operations radeon_driver_kms_fops = {
522 	.owner = THIS_MODULE,
523 	.open = drm_open,
524 	.release = drm_release,
525 	.unlocked_ioctl = radeon_drm_ioctl,
526 	.mmap = radeon_mmap,
527 	.poll = drm_poll,
528 	.read = drm_read,
529 #ifdef CONFIG_COMPAT
530 	.compat_ioctl = radeon_kms_compat_ioctl,
531 #endif
532 };
533 
534 static struct drm_driver kms_driver = {
535 	.driver_features =
536 	    DRIVER_USE_AGP |
537 	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
538 	    DRIVER_PRIME | DRIVER_RENDER,
539 	.load = radeon_driver_load_kms,
540 	.open = radeon_driver_open_kms,
541 	.preclose = radeon_driver_preclose_kms,
542 	.postclose = radeon_driver_postclose_kms,
543 	.lastclose = radeon_driver_lastclose_kms,
544 	.set_busid = drm_pci_set_busid,
545 	.unload = radeon_driver_unload_kms,
546 	.get_vblank_counter = radeon_get_vblank_counter_kms,
547 	.enable_vblank = radeon_enable_vblank_kms,
548 	.disable_vblank = radeon_disable_vblank_kms,
549 	.get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
550 	.get_scanout_position = radeon_get_crtc_scanoutpos,
551 	.irq_preinstall = radeon_driver_irq_preinstall_kms,
552 	.irq_postinstall = radeon_driver_irq_postinstall_kms,
553 	.irq_uninstall = radeon_driver_irq_uninstall_kms,
554 	.irq_handler = radeon_driver_irq_handler_kms,
555 	.ioctls = radeon_ioctls_kms,
556 	.gem_free_object_unlocked = radeon_gem_object_free,
557 	.gem_open_object = radeon_gem_object_open,
558 	.gem_close_object = radeon_gem_object_close,
559 	.dumb_create = radeon_mode_dumb_create,
560 	.dumb_map_offset = radeon_mode_dumb_mmap,
561 	.dumb_destroy = drm_gem_dumb_destroy,
562 	.fops = &radeon_driver_kms_fops,
563 
564 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
565 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
566 	.gem_prime_export = radeon_gem_prime_export,
567 	.gem_prime_import = drm_gem_prime_import,
568 	.gem_prime_pin = radeon_gem_prime_pin,
569 	.gem_prime_unpin = radeon_gem_prime_unpin,
570 	.gem_prime_res_obj = radeon_gem_prime_res_obj,
571 	.gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
572 	.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
573 	.gem_prime_vmap = radeon_gem_prime_vmap,
574 	.gem_prime_vunmap = radeon_gem_prime_vunmap,
575 
576 	.name = DRIVER_NAME,
577 	.desc = DRIVER_DESC,
578 	.date = DRIVER_DATE,
579 	.major = KMS_DRIVER_MAJOR,
580 	.minor = KMS_DRIVER_MINOR,
581 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
582 };
583 
584 static struct drm_driver *driver;
585 static struct pci_driver *pdriver;
586 
587 static struct pci_driver radeon_kms_pci_driver = {
588 	.name = DRIVER_NAME,
589 	.id_table = pciidlist,
590 	.probe = radeon_pci_probe,
591 	.remove = radeon_pci_remove,
592 	.shutdown = radeon_pci_shutdown,
593 	.driver.pm = &radeon_pm_ops,
594 };
595 
596 static int __init radeon_init(void)
597 {
598 	if (vgacon_text_force() && radeon_modeset == -1) {
599 		DRM_INFO("VGACON disable radeon kernel modesetting.\n");
600 		radeon_modeset = 0;
601 	}
602 	/* set to modesetting by default if not nomodeset */
603 	if (radeon_modeset == -1)
604 		radeon_modeset = 1;
605 
606 	if (radeon_modeset == 1) {
607 		DRM_INFO("radeon kernel modesetting enabled.\n");
608 		driver = &kms_driver;
609 		pdriver = &radeon_kms_pci_driver;
610 		driver->driver_features |= DRIVER_MODESET;
611 		driver->num_ioctls = radeon_max_kms_ioctl;
612 		radeon_register_atpx_handler();
613 
614 	} else {
615 		DRM_ERROR("No UMS support in radeon module!\n");
616 		return -EINVAL;
617 	}
618 
619 	/* let modprobe override vga console setting */
620 	return drm_pci_init(driver, pdriver);
621 }
622 
623 static void __exit radeon_exit(void)
624 {
625 	radeon_kfd_fini();
626 	drm_pci_exit(driver, pdriver);
627 	radeon_unregister_atpx_handler();
628 }
629 
630 module_init(radeon_init);
631 module_exit(radeon_exit);
632 
633 MODULE_AUTHOR(DRIVER_AUTHOR);
634 MODULE_DESCRIPTION(DRIVER_DESC);
635 MODULE_LICENSE("GPL and additional rights");
636