1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 40 41 /* 42 * KMS wrapper. 43 * - 2.0.0 - initial interface 44 * - 2.1.0 - add square tiling interface 45 * - 2.2.0 - add r6xx/r7xx const buffer support 46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 47 * - 2.4.0 - add crtc id query 48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 49 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 50 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 51 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 52 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 53 * 2.10.0 - fusion 2D tiling 54 * 2.11.0 - backend map, initial compute support for the CS checker 55 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 56 * 2.13.0 - virtual memory support, streamout 57 * 2.14.0 - add evergreen tiling informations 58 * 2.15.0 - add max_pipes query 59 * 2.16.0 - fix evergreen 2D tiled surface calculation 60 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 61 * 2.18.0 - r600-eg: allow "invalid" DB formats 62 * 2.19.0 - r600-eg: MSAA textures 63 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 64 * 2.21.0 - r600-r700: FMASK and CMASK 65 * 2.22.0 - r600 only: RESOLVE_BOX allowed 66 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 67 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 68 * 2.25.0 - eg+: new info request for num SE and num SH 69 * 2.26.0 - r600-eg: fix htile size computation 70 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 71 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 72 * 2.29.0 - R500 FP16 color clear registers 73 * 2.30.0 - fix for FMASK texturing 74 * 2.31.0 - Add fastfb support for rs690 75 * 2.32.0 - new info request for rings working 76 * 2.33.0 - Add SI tiling mode array query 77 */ 78 #define KMS_DRIVER_MAJOR 2 79 #define KMS_DRIVER_MINOR 33 80 #define KMS_DRIVER_PATCHLEVEL 0 81 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 82 int radeon_driver_unload_kms(struct drm_device *dev); 83 int radeon_driver_firstopen_kms(struct drm_device *dev); 84 void radeon_driver_lastclose_kms(struct drm_device *dev); 85 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 86 void radeon_driver_postclose_kms(struct drm_device *dev, 87 struct drm_file *file_priv); 88 void radeon_driver_preclose_kms(struct drm_device *dev, 89 struct drm_file *file_priv); 90 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 91 int radeon_resume_kms(struct drm_device *dev); 92 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); 93 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); 94 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); 95 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 96 int *max_error, 97 struct timeval *vblank_time, 98 unsigned flags); 99 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 100 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 101 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 102 irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); 103 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, 104 struct drm_file *file_priv); 105 int radeon_gem_object_init(struct drm_gem_object *obj); 106 void radeon_gem_object_free(struct drm_gem_object *obj); 107 int radeon_gem_object_open(struct drm_gem_object *obj, 108 struct drm_file *file_priv); 109 void radeon_gem_object_close(struct drm_gem_object *obj, 110 struct drm_file *file_priv); 111 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 112 int *vpos, int *hpos); 113 extern struct drm_ioctl_desc radeon_ioctls_kms[]; 114 extern int radeon_max_kms_ioctl; 115 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 116 int radeon_mode_dumb_mmap(struct drm_file *filp, 117 struct drm_device *dev, 118 uint32_t handle, uint64_t *offset_p); 119 int radeon_mode_dumb_create(struct drm_file *file_priv, 120 struct drm_device *dev, 121 struct drm_mode_create_dumb *args); 122 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 123 struct drm_device *dev, 124 uint32_t handle); 125 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 126 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 127 size_t size, 128 struct sg_table *sg); 129 int radeon_gem_prime_pin(struct drm_gem_object *obj); 130 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 131 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 132 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 133 unsigned long arg); 134 135 #if defined(CONFIG_DEBUG_FS) 136 int radeon_debugfs_init(struct drm_minor *minor); 137 void radeon_debugfs_cleanup(struct drm_minor *minor); 138 #endif 139 140 /* atpx handler */ 141 #if defined(CONFIG_VGA_SWITCHEROO) 142 void radeon_register_atpx_handler(void); 143 void radeon_unregister_atpx_handler(void); 144 #else 145 static inline void radeon_register_atpx_handler(void) {} 146 static inline void radeon_unregister_atpx_handler(void) {} 147 #endif 148 149 int radeon_no_wb; 150 int radeon_modeset = -1; 151 int radeon_dynclks = -1; 152 int radeon_r4xx_atom = 0; 153 int radeon_agpmode = 0; 154 int radeon_vram_limit = 0; 155 int radeon_gart_size = 512; /* default gart size */ 156 int radeon_benchmarking = 0; 157 int radeon_testing = 0; 158 int radeon_connector_table = 0; 159 int radeon_tv = 1; 160 int radeon_audio = 0; 161 int radeon_disp_priority = 0; 162 int radeon_hw_i2c = 0; 163 int radeon_pcie_gen2 = -1; 164 int radeon_msi = -1; 165 int radeon_lockup_timeout = 10000; 166 int radeon_fastfb = 0; 167 168 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 169 module_param_named(no_wb, radeon_no_wb, int, 0444); 170 171 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 172 module_param_named(modeset, radeon_modeset, int, 0400); 173 174 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 175 module_param_named(dynclks, radeon_dynclks, int, 0444); 176 177 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 178 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 179 180 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); 181 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 182 183 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 184 module_param_named(agpmode, radeon_agpmode, int, 0444); 185 186 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc)"); 187 module_param_named(gartsize, radeon_gart_size, int, 0600); 188 189 MODULE_PARM_DESC(benchmark, "Run benchmark"); 190 module_param_named(benchmark, radeon_benchmarking, int, 0444); 191 192 MODULE_PARM_DESC(test, "Run tests"); 193 module_param_named(test, radeon_testing, int, 0444); 194 195 MODULE_PARM_DESC(connector_table, "Force connector table"); 196 module_param_named(connector_table, radeon_connector_table, int, 0444); 197 198 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 199 module_param_named(tv, radeon_tv, int, 0444); 200 201 MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); 202 module_param_named(audio, radeon_audio, int, 0444); 203 204 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 205 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 206 207 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 208 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 209 210 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 211 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 212 213 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 214 module_param_named(msi, radeon_msi, int, 0444); 215 216 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 217 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 218 219 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 220 module_param_named(fastfb, radeon_fastfb, int, 0444); 221 222 static struct pci_device_id pciidlist[] = { 223 radeon_PCI_IDS 224 }; 225 226 MODULE_DEVICE_TABLE(pci, pciidlist); 227 228 #ifdef CONFIG_DRM_RADEON_UMS 229 230 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 231 { 232 drm_radeon_private_t *dev_priv = dev->dev_private; 233 234 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 235 return 0; 236 237 /* Disable *all* interrupts */ 238 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 239 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 240 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 241 return 0; 242 } 243 244 static int radeon_resume(struct drm_device *dev) 245 { 246 drm_radeon_private_t *dev_priv = dev->dev_private; 247 248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 249 return 0; 250 251 /* Restore interrupt registers */ 252 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 253 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 254 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 255 return 0; 256 } 257 258 static const struct file_operations radeon_driver_old_fops = { 259 .owner = THIS_MODULE, 260 .open = drm_open, 261 .release = drm_release, 262 .unlocked_ioctl = drm_ioctl, 263 .mmap = drm_mmap, 264 .poll = drm_poll, 265 .fasync = drm_fasync, 266 .read = drm_read, 267 #ifdef CONFIG_COMPAT 268 .compat_ioctl = radeon_compat_ioctl, 269 #endif 270 .llseek = noop_llseek, 271 }; 272 273 static struct drm_driver driver_old = { 274 .driver_features = 275 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | 276 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 277 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 278 .load = radeon_driver_load, 279 .firstopen = radeon_driver_firstopen, 280 .open = radeon_driver_open, 281 .preclose = radeon_driver_preclose, 282 .postclose = radeon_driver_postclose, 283 .lastclose = radeon_driver_lastclose, 284 .unload = radeon_driver_unload, 285 .suspend = radeon_suspend, 286 .resume = radeon_resume, 287 .get_vblank_counter = radeon_get_vblank_counter, 288 .enable_vblank = radeon_enable_vblank, 289 .disable_vblank = radeon_disable_vblank, 290 .master_create = radeon_master_create, 291 .master_destroy = radeon_master_destroy, 292 .irq_preinstall = radeon_driver_irq_preinstall, 293 .irq_postinstall = radeon_driver_irq_postinstall, 294 .irq_uninstall = radeon_driver_irq_uninstall, 295 .irq_handler = radeon_driver_irq_handler, 296 .ioctls = radeon_ioctls, 297 .dma_ioctl = radeon_cp_buffers, 298 .fops = &radeon_driver_old_fops, 299 .name = DRIVER_NAME, 300 .desc = DRIVER_DESC, 301 .date = DRIVER_DATE, 302 .major = DRIVER_MAJOR, 303 .minor = DRIVER_MINOR, 304 .patchlevel = DRIVER_PATCHLEVEL, 305 }; 306 307 #endif 308 309 static struct drm_driver kms_driver; 310 311 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 312 { 313 struct apertures_struct *ap; 314 bool primary = false; 315 316 ap = alloc_apertures(1); 317 if (!ap) 318 return -ENOMEM; 319 320 ap->ranges[0].base = pci_resource_start(pdev, 0); 321 ap->ranges[0].size = pci_resource_len(pdev, 0); 322 323 #ifdef CONFIG_X86 324 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 325 #endif 326 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 327 kfree(ap); 328 329 return 0; 330 } 331 332 static int radeon_pci_probe(struct pci_dev *pdev, 333 const struct pci_device_id *ent) 334 { 335 int ret; 336 337 /* Get rid of things like offb */ 338 ret = radeon_kick_out_firmware_fb(pdev); 339 if (ret) 340 return ret; 341 342 return drm_get_pci_dev(pdev, ent, &kms_driver); 343 } 344 345 static void 346 radeon_pci_remove(struct pci_dev *pdev) 347 { 348 struct drm_device *dev = pci_get_drvdata(pdev); 349 350 drm_put_dev(dev); 351 } 352 353 static int 354 radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state) 355 { 356 struct drm_device *dev = pci_get_drvdata(pdev); 357 return radeon_suspend_kms(dev, state); 358 } 359 360 static int 361 radeon_pci_resume(struct pci_dev *pdev) 362 { 363 struct drm_device *dev = pci_get_drvdata(pdev); 364 return radeon_resume_kms(dev); 365 } 366 367 static const struct file_operations radeon_driver_kms_fops = { 368 .owner = THIS_MODULE, 369 .open = drm_open, 370 .release = drm_release, 371 .unlocked_ioctl = drm_ioctl, 372 .mmap = radeon_mmap, 373 .poll = drm_poll, 374 .fasync = drm_fasync, 375 .read = drm_read, 376 #ifdef CONFIG_COMPAT 377 .compat_ioctl = radeon_kms_compat_ioctl, 378 #endif 379 }; 380 381 static struct drm_driver kms_driver = { 382 .driver_features = 383 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | 384 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM | 385 DRIVER_PRIME, 386 .dev_priv_size = 0, 387 .load = radeon_driver_load_kms, 388 .firstopen = radeon_driver_firstopen_kms, 389 .open = radeon_driver_open_kms, 390 .preclose = radeon_driver_preclose_kms, 391 .postclose = radeon_driver_postclose_kms, 392 .lastclose = radeon_driver_lastclose_kms, 393 .unload = radeon_driver_unload_kms, 394 .suspend = radeon_suspend_kms, 395 .resume = radeon_resume_kms, 396 .get_vblank_counter = radeon_get_vblank_counter_kms, 397 .enable_vblank = radeon_enable_vblank_kms, 398 .disable_vblank = radeon_disable_vblank_kms, 399 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 400 .get_scanout_position = radeon_get_crtc_scanoutpos, 401 #if defined(CONFIG_DEBUG_FS) 402 .debugfs_init = radeon_debugfs_init, 403 .debugfs_cleanup = radeon_debugfs_cleanup, 404 #endif 405 .irq_preinstall = radeon_driver_irq_preinstall_kms, 406 .irq_postinstall = radeon_driver_irq_postinstall_kms, 407 .irq_uninstall = radeon_driver_irq_uninstall_kms, 408 .irq_handler = radeon_driver_irq_handler_kms, 409 .ioctls = radeon_ioctls_kms, 410 .gem_init_object = radeon_gem_object_init, 411 .gem_free_object = radeon_gem_object_free, 412 .gem_open_object = radeon_gem_object_open, 413 .gem_close_object = radeon_gem_object_close, 414 .dma_ioctl = radeon_dma_ioctl_kms, 415 .dumb_create = radeon_mode_dumb_create, 416 .dumb_map_offset = radeon_mode_dumb_mmap, 417 .dumb_destroy = radeon_mode_dumb_destroy, 418 .fops = &radeon_driver_kms_fops, 419 420 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 421 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 422 .gem_prime_export = drm_gem_prime_export, 423 .gem_prime_import = drm_gem_prime_import, 424 .gem_prime_pin = radeon_gem_prime_pin, 425 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 426 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 427 .gem_prime_vmap = radeon_gem_prime_vmap, 428 .gem_prime_vunmap = radeon_gem_prime_vunmap, 429 430 .name = DRIVER_NAME, 431 .desc = DRIVER_DESC, 432 .date = DRIVER_DATE, 433 .major = KMS_DRIVER_MAJOR, 434 .minor = KMS_DRIVER_MINOR, 435 .patchlevel = KMS_DRIVER_PATCHLEVEL, 436 }; 437 438 static struct drm_driver *driver; 439 static struct pci_driver *pdriver; 440 441 #ifdef CONFIG_DRM_RADEON_UMS 442 static struct pci_driver radeon_pci_driver = { 443 .name = DRIVER_NAME, 444 .id_table = pciidlist, 445 }; 446 #endif 447 448 static struct pci_driver radeon_kms_pci_driver = { 449 .name = DRIVER_NAME, 450 .id_table = pciidlist, 451 .probe = radeon_pci_probe, 452 .remove = radeon_pci_remove, 453 .suspend = radeon_pci_suspend, 454 .resume = radeon_pci_resume, 455 }; 456 457 static int __init radeon_init(void) 458 { 459 #ifdef CONFIG_VGA_CONSOLE 460 if (vgacon_text_force() && radeon_modeset == -1) { 461 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 462 radeon_modeset = 0; 463 } 464 #endif 465 /* set to modesetting by default if not nomodeset */ 466 if (radeon_modeset == -1) 467 radeon_modeset = 1; 468 469 if (radeon_modeset == 1) { 470 DRM_INFO("radeon kernel modesetting enabled.\n"); 471 driver = &kms_driver; 472 pdriver = &radeon_kms_pci_driver; 473 driver->driver_features |= DRIVER_MODESET; 474 driver->num_ioctls = radeon_max_kms_ioctl; 475 radeon_register_atpx_handler(); 476 477 } else { 478 #ifdef CONFIG_DRM_RADEON_UMS 479 DRM_INFO("radeon userspace modesetting enabled.\n"); 480 driver = &driver_old; 481 pdriver = &radeon_pci_driver; 482 driver->driver_features &= ~DRIVER_MODESET; 483 driver->num_ioctls = radeon_max_ioctl; 484 #else 485 DRM_ERROR("No UMS support in radeon module!\n"); 486 return -EINVAL; 487 #endif 488 } 489 490 /* let modprobe override vga console setting */ 491 return drm_pci_init(driver, pdriver); 492 } 493 494 static void __exit radeon_exit(void) 495 { 496 drm_pci_exit(driver, pdriver); 497 radeon_unregister_atpx_handler(); 498 } 499 500 module_init(radeon_init); 501 module_exit(radeon_exit); 502 503 MODULE_AUTHOR(DRIVER_AUTHOR); 504 MODULE_DESCRIPTION(DRIVER_DESC); 505 MODULE_LICENSE("GPL and additional rights"); 506