1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/vga_switcheroo.h> 41 #include <drm/drm_gem.h> 42 43 #include "drm_crtc_helper.h" 44 #include "radeon_kfd.h" 45 46 /* 47 * KMS wrapper. 48 * - 2.0.0 - initial interface 49 * - 2.1.0 - add square tiling interface 50 * - 2.2.0 - add r6xx/r7xx const buffer support 51 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 52 * - 2.4.0 - add crtc id query 53 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 54 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 55 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 56 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 57 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 58 * 2.10.0 - fusion 2D tiling 59 * 2.11.0 - backend map, initial compute support for the CS checker 60 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 61 * 2.13.0 - virtual memory support, streamout 62 * 2.14.0 - add evergreen tiling informations 63 * 2.15.0 - add max_pipes query 64 * 2.16.0 - fix evergreen 2D tiled surface calculation 65 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 66 * 2.18.0 - r600-eg: allow "invalid" DB formats 67 * 2.19.0 - r600-eg: MSAA textures 68 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 69 * 2.21.0 - r600-r700: FMASK and CMASK 70 * 2.22.0 - r600 only: RESOLVE_BOX allowed 71 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 72 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 73 * 2.25.0 - eg+: new info request for num SE and num SH 74 * 2.26.0 - r600-eg: fix htile size computation 75 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 76 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 77 * 2.29.0 - R500 FP16 color clear registers 78 * 2.30.0 - fix for FMASK texturing 79 * 2.31.0 - Add fastfb support for rs690 80 * 2.32.0 - new info request for rings working 81 * 2.33.0 - Add SI tiling mode array query 82 * 2.34.0 - Add CIK tiling mode array query 83 * 2.35.0 - Add CIK macrotile mode array query 84 * 2.36.0 - Fix CIK DCE tiling setup 85 * 2.37.0 - allow GS ring setup on r6xx/r7xx 86 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 87 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 88 * 2.39.0 - Add INFO query for number of active CUs 89 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 90 * CS to GPU on >= r600 91 */ 92 #define KMS_DRIVER_MAJOR 2 93 #define KMS_DRIVER_MINOR 40 94 #define KMS_DRIVER_PATCHLEVEL 0 95 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 96 int radeon_driver_unload_kms(struct drm_device *dev); 97 void radeon_driver_lastclose_kms(struct drm_device *dev); 98 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 99 void radeon_driver_postclose_kms(struct drm_device *dev, 100 struct drm_file *file_priv); 101 void radeon_driver_preclose_kms(struct drm_device *dev, 102 struct drm_file *file_priv); 103 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 104 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 105 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); 106 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); 107 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); 108 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 109 int *max_error, 110 struct timeval *vblank_time, 111 unsigned flags); 112 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 113 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 114 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 115 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 116 void radeon_gem_object_free(struct drm_gem_object *obj); 117 int radeon_gem_object_open(struct drm_gem_object *obj, 118 struct drm_file *file_priv); 119 void radeon_gem_object_close(struct drm_gem_object *obj, 120 struct drm_file *file_priv); 121 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, 122 struct drm_gem_object *gobj, 123 int flags); 124 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 125 unsigned int flags, 126 int *vpos, int *hpos, ktime_t *stime, 127 ktime_t *etime); 128 extern bool radeon_is_px(struct drm_device *dev); 129 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 130 extern int radeon_max_kms_ioctl; 131 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 132 int radeon_mode_dumb_mmap(struct drm_file *filp, 133 struct drm_device *dev, 134 uint32_t handle, uint64_t *offset_p); 135 int radeon_mode_dumb_create(struct drm_file *file_priv, 136 struct drm_device *dev, 137 struct drm_mode_create_dumb *args); 138 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 139 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 140 struct dma_buf_attachment *, 141 struct sg_table *sg); 142 int radeon_gem_prime_pin(struct drm_gem_object *obj); 143 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 144 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 145 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 146 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 147 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 148 unsigned long arg); 149 150 #if defined(CONFIG_DEBUG_FS) 151 int radeon_debugfs_init(struct drm_minor *minor); 152 void radeon_debugfs_cleanup(struct drm_minor *minor); 153 #endif 154 155 /* atpx handler */ 156 #if defined(CONFIG_VGA_SWITCHEROO) 157 void radeon_register_atpx_handler(void); 158 void radeon_unregister_atpx_handler(void); 159 #else 160 static inline void radeon_register_atpx_handler(void) {} 161 static inline void radeon_unregister_atpx_handler(void) {} 162 #endif 163 164 int radeon_no_wb; 165 int radeon_modeset = -1; 166 int radeon_dynclks = -1; 167 int radeon_r4xx_atom = 0; 168 int radeon_agpmode = 0; 169 int radeon_vram_limit = 0; 170 int radeon_gart_size = -1; /* auto */ 171 int radeon_benchmarking = 0; 172 int radeon_testing = 0; 173 int radeon_connector_table = 0; 174 int radeon_tv = 1; 175 int radeon_audio = -1; 176 int radeon_disp_priority = 0; 177 int radeon_hw_i2c = 0; 178 int radeon_pcie_gen2 = -1; 179 int radeon_msi = -1; 180 int radeon_lockup_timeout = 10000; 181 int radeon_fastfb = 0; 182 int radeon_dpm = -1; 183 int radeon_aspm = -1; 184 int radeon_runtime_pm = -1; 185 int radeon_hard_reset = 0; 186 int radeon_vm_size = 8; 187 int radeon_vm_block_size = -1; 188 int radeon_deep_color = 0; 189 int radeon_use_pflipirq = 2; 190 int radeon_bapm = -1; 191 int radeon_backlight = -1; 192 193 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 194 module_param_named(no_wb, radeon_no_wb, int, 0444); 195 196 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 197 module_param_named(modeset, radeon_modeset, int, 0400); 198 199 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 200 module_param_named(dynclks, radeon_dynclks, int, 0444); 201 202 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 203 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 204 205 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 206 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 207 208 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 209 module_param_named(agpmode, radeon_agpmode, int, 0444); 210 211 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 212 module_param_named(gartsize, radeon_gart_size, int, 0600); 213 214 MODULE_PARM_DESC(benchmark, "Run benchmark"); 215 module_param_named(benchmark, radeon_benchmarking, int, 0444); 216 217 MODULE_PARM_DESC(test, "Run tests"); 218 module_param_named(test, radeon_testing, int, 0444); 219 220 MODULE_PARM_DESC(connector_table, "Force connector table"); 221 module_param_named(connector_table, radeon_connector_table, int, 0444); 222 223 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 224 module_param_named(tv, radeon_tv, int, 0444); 225 226 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 227 module_param_named(audio, radeon_audio, int, 0444); 228 229 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 230 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 231 232 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 233 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 234 235 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 236 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 237 238 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 239 module_param_named(msi, radeon_msi, int, 0444); 240 241 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 242 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 243 244 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 245 module_param_named(fastfb, radeon_fastfb, int, 0444); 246 247 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 248 module_param_named(dpm, radeon_dpm, int, 0444); 249 250 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 251 module_param_named(aspm, radeon_aspm, int, 0444); 252 253 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 254 module_param_named(runpm, radeon_runtime_pm, int, 0444); 255 256 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 257 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 258 259 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 260 module_param_named(vm_size, radeon_vm_size, int, 0444); 261 262 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 263 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 264 265 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 266 module_param_named(deep_color, radeon_deep_color, int, 0444); 267 268 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 269 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 270 271 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 272 module_param_named(bapm, radeon_bapm, int, 0444); 273 274 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 275 module_param_named(backlight, radeon_backlight, int, 0444); 276 277 static struct pci_device_id pciidlist[] = { 278 radeon_PCI_IDS 279 }; 280 281 MODULE_DEVICE_TABLE(pci, pciidlist); 282 283 #ifdef CONFIG_DRM_RADEON_UMS 284 285 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 286 { 287 drm_radeon_private_t *dev_priv = dev->dev_private; 288 289 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 290 return 0; 291 292 /* Disable *all* interrupts */ 293 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 294 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 295 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 296 return 0; 297 } 298 299 static int radeon_resume(struct drm_device *dev) 300 { 301 drm_radeon_private_t *dev_priv = dev->dev_private; 302 303 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 304 return 0; 305 306 /* Restore interrupt registers */ 307 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 308 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 309 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 310 return 0; 311 } 312 313 314 static const struct file_operations radeon_driver_old_fops = { 315 .owner = THIS_MODULE, 316 .open = drm_open, 317 .release = drm_release, 318 .unlocked_ioctl = drm_ioctl, 319 .mmap = drm_legacy_mmap, 320 .poll = drm_poll, 321 .read = drm_read, 322 #ifdef CONFIG_COMPAT 323 .compat_ioctl = radeon_compat_ioctl, 324 #endif 325 .llseek = noop_llseek, 326 }; 327 328 static struct drm_driver driver_old = { 329 .driver_features = 330 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 331 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 332 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 333 .load = radeon_driver_load, 334 .firstopen = radeon_driver_firstopen, 335 .open = radeon_driver_open, 336 .preclose = radeon_driver_preclose, 337 .postclose = radeon_driver_postclose, 338 .lastclose = radeon_driver_lastclose, 339 .set_busid = drm_pci_set_busid, 340 .unload = radeon_driver_unload, 341 .suspend = radeon_suspend, 342 .resume = radeon_resume, 343 .get_vblank_counter = radeon_get_vblank_counter, 344 .enable_vblank = radeon_enable_vblank, 345 .disable_vblank = radeon_disable_vblank, 346 .master_create = radeon_master_create, 347 .master_destroy = radeon_master_destroy, 348 .irq_preinstall = radeon_driver_irq_preinstall, 349 .irq_postinstall = radeon_driver_irq_postinstall, 350 .irq_uninstall = radeon_driver_irq_uninstall, 351 .irq_handler = radeon_driver_irq_handler, 352 .ioctls = radeon_ioctls, 353 .dma_ioctl = radeon_cp_buffers, 354 .fops = &radeon_driver_old_fops, 355 .name = DRIVER_NAME, 356 .desc = DRIVER_DESC, 357 .date = DRIVER_DATE, 358 .major = DRIVER_MAJOR, 359 .minor = DRIVER_MINOR, 360 .patchlevel = DRIVER_PATCHLEVEL, 361 }; 362 363 #endif 364 365 static struct drm_driver kms_driver; 366 367 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 368 { 369 struct apertures_struct *ap; 370 bool primary = false; 371 372 ap = alloc_apertures(1); 373 if (!ap) 374 return -ENOMEM; 375 376 ap->ranges[0].base = pci_resource_start(pdev, 0); 377 ap->ranges[0].size = pci_resource_len(pdev, 0); 378 379 #ifdef CONFIG_X86 380 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 381 #endif 382 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 383 kfree(ap); 384 385 return 0; 386 } 387 388 static int radeon_pci_probe(struct pci_dev *pdev, 389 const struct pci_device_id *ent) 390 { 391 int ret; 392 393 /* Get rid of things like offb */ 394 ret = radeon_kick_out_firmware_fb(pdev); 395 if (ret) 396 return ret; 397 398 return drm_get_pci_dev(pdev, ent, &kms_driver); 399 } 400 401 static void 402 radeon_pci_remove(struct pci_dev *pdev) 403 { 404 struct drm_device *dev = pci_get_drvdata(pdev); 405 406 drm_put_dev(dev); 407 } 408 409 static int radeon_pmops_suspend(struct device *dev) 410 { 411 struct pci_dev *pdev = to_pci_dev(dev); 412 struct drm_device *drm_dev = pci_get_drvdata(pdev); 413 return radeon_suspend_kms(drm_dev, true, true); 414 } 415 416 static int radeon_pmops_resume(struct device *dev) 417 { 418 struct pci_dev *pdev = to_pci_dev(dev); 419 struct drm_device *drm_dev = pci_get_drvdata(pdev); 420 return radeon_resume_kms(drm_dev, true, true); 421 } 422 423 static int radeon_pmops_freeze(struct device *dev) 424 { 425 struct pci_dev *pdev = to_pci_dev(dev); 426 struct drm_device *drm_dev = pci_get_drvdata(pdev); 427 return radeon_suspend_kms(drm_dev, false, true); 428 } 429 430 static int radeon_pmops_thaw(struct device *dev) 431 { 432 struct pci_dev *pdev = to_pci_dev(dev); 433 struct drm_device *drm_dev = pci_get_drvdata(pdev); 434 return radeon_resume_kms(drm_dev, false, true); 435 } 436 437 static int radeon_pmops_runtime_suspend(struct device *dev) 438 { 439 struct pci_dev *pdev = to_pci_dev(dev); 440 struct drm_device *drm_dev = pci_get_drvdata(pdev); 441 int ret; 442 443 if (!radeon_is_px(drm_dev)) { 444 pm_runtime_forbid(dev); 445 return -EBUSY; 446 } 447 448 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 449 drm_kms_helper_poll_disable(drm_dev); 450 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 451 452 ret = radeon_suspend_kms(drm_dev, false, false); 453 pci_save_state(pdev); 454 pci_disable_device(pdev); 455 pci_ignore_hotplug(pdev); 456 pci_set_power_state(pdev, PCI_D3cold); 457 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 458 459 return 0; 460 } 461 462 static int radeon_pmops_runtime_resume(struct device *dev) 463 { 464 struct pci_dev *pdev = to_pci_dev(dev); 465 struct drm_device *drm_dev = pci_get_drvdata(pdev); 466 int ret; 467 468 if (!radeon_is_px(drm_dev)) 469 return -EINVAL; 470 471 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 472 473 pci_set_power_state(pdev, PCI_D0); 474 pci_restore_state(pdev); 475 ret = pci_enable_device(pdev); 476 if (ret) 477 return ret; 478 pci_set_master(pdev); 479 480 ret = radeon_resume_kms(drm_dev, false, false); 481 drm_kms_helper_poll_enable(drm_dev); 482 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 483 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 484 return 0; 485 } 486 487 static int radeon_pmops_runtime_idle(struct device *dev) 488 { 489 struct pci_dev *pdev = to_pci_dev(dev); 490 struct drm_device *drm_dev = pci_get_drvdata(pdev); 491 struct drm_crtc *crtc; 492 493 if (!radeon_is_px(drm_dev)) { 494 pm_runtime_forbid(dev); 495 return -EBUSY; 496 } 497 498 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 499 if (crtc->enabled) { 500 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 501 return -EBUSY; 502 } 503 } 504 505 pm_runtime_mark_last_busy(dev); 506 pm_runtime_autosuspend(dev); 507 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 508 return 1; 509 } 510 511 long radeon_drm_ioctl(struct file *filp, 512 unsigned int cmd, unsigned long arg) 513 { 514 struct drm_file *file_priv = filp->private_data; 515 struct drm_device *dev; 516 long ret; 517 dev = file_priv->minor->dev; 518 ret = pm_runtime_get_sync(dev->dev); 519 if (ret < 0) 520 return ret; 521 522 ret = drm_ioctl(filp, cmd, arg); 523 524 pm_runtime_mark_last_busy(dev->dev); 525 pm_runtime_put_autosuspend(dev->dev); 526 return ret; 527 } 528 529 static const struct dev_pm_ops radeon_pm_ops = { 530 .suspend = radeon_pmops_suspend, 531 .resume = radeon_pmops_resume, 532 .freeze = radeon_pmops_freeze, 533 .thaw = radeon_pmops_thaw, 534 .poweroff = radeon_pmops_freeze, 535 .restore = radeon_pmops_resume, 536 .runtime_suspend = radeon_pmops_runtime_suspend, 537 .runtime_resume = radeon_pmops_runtime_resume, 538 .runtime_idle = radeon_pmops_runtime_idle, 539 }; 540 541 static const struct file_operations radeon_driver_kms_fops = { 542 .owner = THIS_MODULE, 543 .open = drm_open, 544 .release = drm_release, 545 .unlocked_ioctl = radeon_drm_ioctl, 546 .mmap = radeon_mmap, 547 .poll = drm_poll, 548 .read = drm_read, 549 #ifdef CONFIG_COMPAT 550 .compat_ioctl = radeon_kms_compat_ioctl, 551 #endif 552 }; 553 554 static struct drm_driver kms_driver = { 555 .driver_features = 556 DRIVER_USE_AGP | 557 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 558 DRIVER_PRIME | DRIVER_RENDER, 559 .load = radeon_driver_load_kms, 560 .open = radeon_driver_open_kms, 561 .preclose = radeon_driver_preclose_kms, 562 .postclose = radeon_driver_postclose_kms, 563 .lastclose = radeon_driver_lastclose_kms, 564 .set_busid = drm_pci_set_busid, 565 .unload = radeon_driver_unload_kms, 566 .get_vblank_counter = radeon_get_vblank_counter_kms, 567 .enable_vblank = radeon_enable_vblank_kms, 568 .disable_vblank = radeon_disable_vblank_kms, 569 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 570 .get_scanout_position = radeon_get_crtc_scanoutpos, 571 #if defined(CONFIG_DEBUG_FS) 572 .debugfs_init = radeon_debugfs_init, 573 .debugfs_cleanup = radeon_debugfs_cleanup, 574 #endif 575 .irq_preinstall = radeon_driver_irq_preinstall_kms, 576 .irq_postinstall = radeon_driver_irq_postinstall_kms, 577 .irq_uninstall = radeon_driver_irq_uninstall_kms, 578 .irq_handler = radeon_driver_irq_handler_kms, 579 .ioctls = radeon_ioctls_kms, 580 .gem_free_object = radeon_gem_object_free, 581 .gem_open_object = radeon_gem_object_open, 582 .gem_close_object = radeon_gem_object_close, 583 .dumb_create = radeon_mode_dumb_create, 584 .dumb_map_offset = radeon_mode_dumb_mmap, 585 .dumb_destroy = drm_gem_dumb_destroy, 586 .fops = &radeon_driver_kms_fops, 587 588 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 589 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 590 .gem_prime_export = radeon_gem_prime_export, 591 .gem_prime_import = drm_gem_prime_import, 592 .gem_prime_pin = radeon_gem_prime_pin, 593 .gem_prime_unpin = radeon_gem_prime_unpin, 594 .gem_prime_res_obj = radeon_gem_prime_res_obj, 595 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 596 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 597 .gem_prime_vmap = radeon_gem_prime_vmap, 598 .gem_prime_vunmap = radeon_gem_prime_vunmap, 599 600 .name = DRIVER_NAME, 601 .desc = DRIVER_DESC, 602 .date = DRIVER_DATE, 603 .major = KMS_DRIVER_MAJOR, 604 .minor = KMS_DRIVER_MINOR, 605 .patchlevel = KMS_DRIVER_PATCHLEVEL, 606 }; 607 608 static struct drm_driver *driver; 609 static struct pci_driver *pdriver; 610 611 #ifdef CONFIG_DRM_RADEON_UMS 612 static struct pci_driver radeon_pci_driver = { 613 .name = DRIVER_NAME, 614 .id_table = pciidlist, 615 }; 616 #endif 617 618 static struct pci_driver radeon_kms_pci_driver = { 619 .name = DRIVER_NAME, 620 .id_table = pciidlist, 621 .probe = radeon_pci_probe, 622 .remove = radeon_pci_remove, 623 .driver.pm = &radeon_pm_ops, 624 }; 625 626 static int __init radeon_init(void) 627 { 628 #ifdef CONFIG_VGA_CONSOLE 629 if (vgacon_text_force() && radeon_modeset == -1) { 630 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 631 radeon_modeset = 0; 632 } 633 #endif 634 /* set to modesetting by default if not nomodeset */ 635 if (radeon_modeset == -1) 636 radeon_modeset = 1; 637 638 if (radeon_modeset == 1) { 639 DRM_INFO("radeon kernel modesetting enabled.\n"); 640 driver = &kms_driver; 641 pdriver = &radeon_kms_pci_driver; 642 driver->driver_features |= DRIVER_MODESET; 643 driver->num_ioctls = radeon_max_kms_ioctl; 644 radeon_register_atpx_handler(); 645 646 } else { 647 #ifdef CONFIG_DRM_RADEON_UMS 648 DRM_INFO("radeon userspace modesetting enabled.\n"); 649 driver = &driver_old; 650 pdriver = &radeon_pci_driver; 651 driver->driver_features &= ~DRIVER_MODESET; 652 driver->num_ioctls = radeon_max_ioctl; 653 #else 654 DRM_ERROR("No UMS support in radeon module!\n"); 655 return -EINVAL; 656 #endif 657 } 658 659 radeon_kfd_init(); 660 661 /* let modprobe override vga console setting */ 662 return drm_pci_init(driver, pdriver); 663 } 664 665 static void __exit radeon_exit(void) 666 { 667 radeon_kfd_fini(); 668 drm_pci_exit(driver, pdriver); 669 radeon_unregister_atpx_handler(); 670 } 671 672 module_init(radeon_init); 673 module_exit(radeon_exit); 674 675 MODULE_AUTHOR(DRIVER_AUTHOR); 676 MODULE_DESCRIPTION(DRIVER_DESC); 677 MODULE_LICENSE("GPL and additional rights"); 678