1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pci.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/drm_file.h> 46 #include <drm/drm_gem.h> 47 #include <drm/drm_ioctl.h> 48 #include <drm/drm_pciids.h> 49 #include <drm/drm_probe_helper.h> 50 #include <drm/drm_vblank.h> 51 #include <drm/radeon_drm.h> 52 53 #include "radeon_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 2.0.0 - initial interface 58 * - 2.1.0 - add square tiling interface 59 * - 2.2.0 - add r6xx/r7xx const buffer support 60 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 61 * - 2.4.0 - add crtc id query 62 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 63 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 64 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 65 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 66 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 67 * 2.10.0 - fusion 2D tiling 68 * 2.11.0 - backend map, initial compute support for the CS checker 69 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 70 * 2.13.0 - virtual memory support, streamout 71 * 2.14.0 - add evergreen tiling informations 72 * 2.15.0 - add max_pipes query 73 * 2.16.0 - fix evergreen 2D tiled surface calculation 74 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 75 * 2.18.0 - r600-eg: allow "invalid" DB formats 76 * 2.19.0 - r600-eg: MSAA textures 77 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 78 * 2.21.0 - r600-r700: FMASK and CMASK 79 * 2.22.0 - r600 only: RESOLVE_BOX allowed 80 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 81 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 82 * 2.25.0 - eg+: new info request for num SE and num SH 83 * 2.26.0 - r600-eg: fix htile size computation 84 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 85 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 86 * 2.29.0 - R500 FP16 color clear registers 87 * 2.30.0 - fix for FMASK texturing 88 * 2.31.0 - Add fastfb support for rs690 89 * 2.32.0 - new info request for rings working 90 * 2.33.0 - Add SI tiling mode array query 91 * 2.34.0 - Add CIK tiling mode array query 92 * 2.35.0 - Add CIK macrotile mode array query 93 * 2.36.0 - Fix CIK DCE tiling setup 94 * 2.37.0 - allow GS ring setup on r6xx/r7xx 95 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 96 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 97 * 2.39.0 - Add INFO query for number of active CUs 98 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 99 * CS to GPU on >= r600 100 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 101 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 102 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 103 * 2.44.0 - SET_APPEND_CNT packet3 support 104 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 105 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 106 * 2.47.0 - Add UVD_NO_OP register support 107 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 108 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 109 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 110 */ 111 #define KMS_DRIVER_MAJOR 2 112 #define KMS_DRIVER_MINOR 50 113 #define KMS_DRIVER_PATCHLEVEL 0 114 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 115 void radeon_driver_unload_kms(struct drm_device *dev); 116 void radeon_driver_lastclose_kms(struct drm_device *dev); 117 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 118 void radeon_driver_postclose_kms(struct drm_device *dev, 119 struct drm_file *file_priv); 120 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 121 bool fbcon, bool freeze); 122 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 123 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 124 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 125 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 126 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 127 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 128 unsigned int flags, int *vpos, int *hpos, 129 ktime_t *stime, ktime_t *etime, 130 const struct drm_display_mode *mode); 131 extern bool radeon_is_px(struct drm_device *dev); 132 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 133 extern int radeon_max_kms_ioctl; 134 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 135 int radeon_mode_dumb_mmap(struct drm_file *filp, 136 struct drm_device *dev, 137 uint32_t handle, uint64_t *offset_p); 138 int radeon_mode_dumb_create(struct drm_file *file_priv, 139 struct drm_device *dev, 140 struct drm_mode_create_dumb *args); 141 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 142 struct dma_buf_attachment *, 143 struct sg_table *sg); 144 145 /* atpx handler */ 146 #if defined(CONFIG_VGA_SWITCHEROO) 147 void radeon_register_atpx_handler(void); 148 void radeon_unregister_atpx_handler(void); 149 bool radeon_has_atpx_dgpu_power_cntl(void); 150 bool radeon_is_atpx_hybrid(void); 151 #else 152 static inline void radeon_register_atpx_handler(void) {} 153 static inline void radeon_unregister_atpx_handler(void) {} 154 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 155 static inline bool radeon_is_atpx_hybrid(void) { return false; } 156 #endif 157 158 int radeon_no_wb; 159 int radeon_modeset = -1; 160 int radeon_dynclks = -1; 161 int radeon_r4xx_atom = 0; 162 int radeon_agpmode = -1; 163 int radeon_vram_limit = 0; 164 int radeon_gart_size = -1; /* auto */ 165 int radeon_benchmarking = 0; 166 int radeon_testing = 0; 167 int radeon_connector_table = 0; 168 int radeon_tv = 1; 169 int radeon_audio = -1; 170 int radeon_disp_priority = 0; 171 int radeon_hw_i2c = 0; 172 int radeon_pcie_gen2 = -1; 173 int radeon_msi = -1; 174 int radeon_lockup_timeout = 10000; 175 int radeon_fastfb = 0; 176 int radeon_dpm = -1; 177 int radeon_aspm = -1; 178 int radeon_runtime_pm = -1; 179 int radeon_hard_reset = 0; 180 int radeon_vm_size = 8; 181 int radeon_vm_block_size = -1; 182 int radeon_deep_color = 0; 183 int radeon_use_pflipirq = 2; 184 int radeon_bapm = -1; 185 int radeon_backlight = -1; 186 int radeon_auxch = -1; 187 int radeon_mst = 0; 188 int radeon_uvd = 1; 189 int radeon_vce = 1; 190 191 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 192 module_param_named(no_wb, radeon_no_wb, int, 0444); 193 194 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 195 module_param_named(modeset, radeon_modeset, int, 0400); 196 197 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 198 module_param_named(dynclks, radeon_dynclks, int, 0444); 199 200 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 201 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 202 203 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 204 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 205 206 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 207 module_param_named(agpmode, radeon_agpmode, int, 0444); 208 209 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 210 module_param_named(gartsize, radeon_gart_size, int, 0600); 211 212 MODULE_PARM_DESC(benchmark, "Run benchmark"); 213 module_param_named(benchmark, radeon_benchmarking, int, 0444); 214 215 MODULE_PARM_DESC(test, "Run tests"); 216 module_param_named(test, radeon_testing, int, 0444); 217 218 MODULE_PARM_DESC(connector_table, "Force connector table"); 219 module_param_named(connector_table, radeon_connector_table, int, 0444); 220 221 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 222 module_param_named(tv, radeon_tv, int, 0444); 223 224 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 225 module_param_named(audio, radeon_audio, int, 0444); 226 227 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 228 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 229 230 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 231 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 232 233 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 234 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 235 236 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 237 module_param_named(msi, radeon_msi, int, 0444); 238 239 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 240 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 241 242 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 243 module_param_named(fastfb, radeon_fastfb, int, 0444); 244 245 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 246 module_param_named(dpm, radeon_dpm, int, 0444); 247 248 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 249 module_param_named(aspm, radeon_aspm, int, 0444); 250 251 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 252 module_param_named(runpm, radeon_runtime_pm, int, 0444); 253 254 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 255 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 256 257 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 258 module_param_named(vm_size, radeon_vm_size, int, 0444); 259 260 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 261 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 262 263 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 264 module_param_named(deep_color, radeon_deep_color, int, 0444); 265 266 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 267 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 268 269 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 270 module_param_named(bapm, radeon_bapm, int, 0444); 271 272 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 273 module_param_named(backlight, radeon_backlight, int, 0444); 274 275 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 276 module_param_named(auxch, radeon_auxch, int, 0444); 277 278 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 279 module_param_named(mst, radeon_mst, int, 0444); 280 281 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 282 module_param_named(uvd, radeon_uvd, int, 0444); 283 284 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 285 module_param_named(vce, radeon_vce, int, 0444); 286 287 int radeon_si_support = 1; 288 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 289 module_param_named(si_support, radeon_si_support, int, 0444); 290 291 int radeon_cik_support = 1; 292 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 293 module_param_named(cik_support, radeon_cik_support, int, 0444); 294 295 static struct pci_device_id pciidlist[] = { 296 radeon_PCI_IDS 297 }; 298 299 MODULE_DEVICE_TABLE(pci, pciidlist); 300 301 static struct drm_driver kms_driver; 302 303 bool radeon_device_is_virtual(void); 304 305 static int radeon_pci_probe(struct pci_dev *pdev, 306 const struct pci_device_id *ent) 307 { 308 unsigned long flags = 0; 309 struct drm_device *dev; 310 int ret; 311 312 if (!ent) 313 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 314 315 flags = ent->driver_data; 316 317 if (!radeon_si_support) { 318 switch (flags & RADEON_FAMILY_MASK) { 319 case CHIP_TAHITI: 320 case CHIP_PITCAIRN: 321 case CHIP_VERDE: 322 case CHIP_OLAND: 323 case CHIP_HAINAN: 324 dev_info(&pdev->dev, 325 "SI support disabled by module param\n"); 326 return -ENODEV; 327 } 328 } 329 if (!radeon_cik_support) { 330 switch (flags & RADEON_FAMILY_MASK) { 331 case CHIP_KAVERI: 332 case CHIP_BONAIRE: 333 case CHIP_HAWAII: 334 case CHIP_KABINI: 335 case CHIP_MULLINS: 336 dev_info(&pdev->dev, 337 "CIK support disabled by module param\n"); 338 return -ENODEV; 339 } 340 } 341 342 if (vga_switcheroo_client_probe_defer(pdev)) 343 return -EPROBE_DEFER; 344 345 /* Get rid of things like offb */ 346 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 347 if (ret) 348 return ret; 349 350 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 351 if (IS_ERR(dev)) 352 return PTR_ERR(dev); 353 354 ret = pci_enable_device(pdev); 355 if (ret) 356 goto err_free; 357 358 dev->pdev = pdev; 359 #ifdef __alpha__ 360 dev->hose = pdev->sysdata; 361 #endif 362 363 pci_set_drvdata(pdev, dev); 364 365 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) 366 dev->agp = drm_agp_init(dev); 367 if (dev->agp) { 368 dev->agp->agp_mtrr = arch_phys_wc_add( 369 dev->agp->agp_info.aper_base, 370 dev->agp->agp_info.aper_size * 371 1024 * 1024); 372 } 373 374 ret = drm_dev_register(dev, ent->driver_data); 375 if (ret) 376 goto err_agp; 377 378 return 0; 379 380 err_agp: 381 if (dev->agp) 382 arch_phys_wc_del(dev->agp->agp_mtrr); 383 kfree(dev->agp); 384 pci_disable_device(pdev); 385 err_free: 386 drm_dev_put(dev); 387 return ret; 388 } 389 390 static void 391 radeon_pci_remove(struct pci_dev *pdev) 392 { 393 struct drm_device *dev = pci_get_drvdata(pdev); 394 395 drm_put_dev(dev); 396 } 397 398 static void 399 radeon_pci_shutdown(struct pci_dev *pdev) 400 { 401 /* if we are running in a VM, make sure the device 402 * torn down properly on reboot/shutdown 403 */ 404 if (radeon_device_is_virtual()) 405 radeon_pci_remove(pdev); 406 407 #ifdef CONFIG_PPC64 408 /* 409 * Some adapters need to be suspended before a 410 * shutdown occurs in order to prevent an error 411 * during kexec. 412 * Make this power specific becauase it breaks 413 * some non-power boards. 414 */ 415 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 416 #endif 417 } 418 419 static int radeon_pmops_suspend(struct device *dev) 420 { 421 struct drm_device *drm_dev = dev_get_drvdata(dev); 422 return radeon_suspend_kms(drm_dev, true, true, false); 423 } 424 425 static int radeon_pmops_resume(struct device *dev) 426 { 427 struct drm_device *drm_dev = dev_get_drvdata(dev); 428 429 /* GPU comes up enabled by the bios on resume */ 430 if (radeon_is_px(drm_dev)) { 431 pm_runtime_disable(dev); 432 pm_runtime_set_active(dev); 433 pm_runtime_enable(dev); 434 } 435 436 return radeon_resume_kms(drm_dev, true, true); 437 } 438 439 static int radeon_pmops_freeze(struct device *dev) 440 { 441 struct drm_device *drm_dev = dev_get_drvdata(dev); 442 return radeon_suspend_kms(drm_dev, false, true, true); 443 } 444 445 static int radeon_pmops_thaw(struct device *dev) 446 { 447 struct drm_device *drm_dev = dev_get_drvdata(dev); 448 return radeon_resume_kms(drm_dev, false, true); 449 } 450 451 static int radeon_pmops_runtime_suspend(struct device *dev) 452 { 453 struct pci_dev *pdev = to_pci_dev(dev); 454 struct drm_device *drm_dev = pci_get_drvdata(pdev); 455 int ret; 456 457 if (!radeon_is_px(drm_dev)) { 458 pm_runtime_forbid(dev); 459 return -EBUSY; 460 } 461 462 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 463 drm_kms_helper_poll_disable(drm_dev); 464 465 ret = radeon_suspend_kms(drm_dev, false, false, false); 466 pci_save_state(pdev); 467 pci_disable_device(pdev); 468 pci_ignore_hotplug(pdev); 469 if (radeon_is_atpx_hybrid()) 470 pci_set_power_state(pdev, PCI_D3cold); 471 else if (!radeon_has_atpx_dgpu_power_cntl()) 472 pci_set_power_state(pdev, PCI_D3hot); 473 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 474 475 return 0; 476 } 477 478 static int radeon_pmops_runtime_resume(struct device *dev) 479 { 480 struct pci_dev *pdev = to_pci_dev(dev); 481 struct drm_device *drm_dev = pci_get_drvdata(pdev); 482 int ret; 483 484 if (!radeon_is_px(drm_dev)) 485 return -EINVAL; 486 487 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 488 489 if (radeon_is_atpx_hybrid() || 490 !radeon_has_atpx_dgpu_power_cntl()) 491 pci_set_power_state(pdev, PCI_D0); 492 pci_restore_state(pdev); 493 ret = pci_enable_device(pdev); 494 if (ret) 495 return ret; 496 pci_set_master(pdev); 497 498 ret = radeon_resume_kms(drm_dev, false, false); 499 drm_kms_helper_poll_enable(drm_dev); 500 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 501 return 0; 502 } 503 504 static int radeon_pmops_runtime_idle(struct device *dev) 505 { 506 struct drm_device *drm_dev = dev_get_drvdata(dev); 507 struct drm_crtc *crtc; 508 509 if (!radeon_is_px(drm_dev)) { 510 pm_runtime_forbid(dev); 511 return -EBUSY; 512 } 513 514 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 515 if (crtc->enabled) { 516 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 517 return -EBUSY; 518 } 519 } 520 521 pm_runtime_mark_last_busy(dev); 522 pm_runtime_autosuspend(dev); 523 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 524 return 1; 525 } 526 527 long radeon_drm_ioctl(struct file *filp, 528 unsigned int cmd, unsigned long arg) 529 { 530 struct drm_file *file_priv = filp->private_data; 531 struct drm_device *dev; 532 long ret; 533 dev = file_priv->minor->dev; 534 ret = pm_runtime_get_sync(dev->dev); 535 if (ret < 0) { 536 pm_runtime_put_autosuspend(dev->dev); 537 return ret; 538 } 539 540 ret = drm_ioctl(filp, cmd, arg); 541 542 pm_runtime_mark_last_busy(dev->dev); 543 pm_runtime_put_autosuspend(dev->dev); 544 return ret; 545 } 546 547 #ifdef CONFIG_COMPAT 548 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 549 { 550 unsigned int nr = DRM_IOCTL_NR(cmd); 551 int ret; 552 553 if (nr < DRM_COMMAND_BASE) 554 return drm_compat_ioctl(filp, cmd, arg); 555 556 ret = radeon_drm_ioctl(filp, cmd, arg); 557 558 return ret; 559 } 560 #endif 561 562 static const struct dev_pm_ops radeon_pm_ops = { 563 .suspend = radeon_pmops_suspend, 564 .resume = radeon_pmops_resume, 565 .freeze = radeon_pmops_freeze, 566 .thaw = radeon_pmops_thaw, 567 .poweroff = radeon_pmops_freeze, 568 .restore = radeon_pmops_resume, 569 .runtime_suspend = radeon_pmops_runtime_suspend, 570 .runtime_resume = radeon_pmops_runtime_resume, 571 .runtime_idle = radeon_pmops_runtime_idle, 572 }; 573 574 static const struct file_operations radeon_driver_kms_fops = { 575 .owner = THIS_MODULE, 576 .open = drm_open, 577 .release = drm_release, 578 .unlocked_ioctl = radeon_drm_ioctl, 579 .mmap = radeon_mmap, 580 .poll = drm_poll, 581 .read = drm_read, 582 #ifdef CONFIG_COMPAT 583 .compat_ioctl = radeon_kms_compat_ioctl, 584 #endif 585 }; 586 587 static struct drm_driver kms_driver = { 588 .driver_features = 589 DRIVER_GEM | DRIVER_RENDER, 590 .load = radeon_driver_load_kms, 591 .open = radeon_driver_open_kms, 592 .postclose = radeon_driver_postclose_kms, 593 .lastclose = radeon_driver_lastclose_kms, 594 .unload = radeon_driver_unload_kms, 595 .irq_preinstall = radeon_driver_irq_preinstall_kms, 596 .irq_postinstall = radeon_driver_irq_postinstall_kms, 597 .irq_uninstall = radeon_driver_irq_uninstall_kms, 598 .irq_handler = radeon_driver_irq_handler_kms, 599 .ioctls = radeon_ioctls_kms, 600 .dumb_create = radeon_mode_dumb_create, 601 .dumb_map_offset = radeon_mode_dumb_mmap, 602 .fops = &radeon_driver_kms_fops, 603 604 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 605 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 606 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 607 608 .name = DRIVER_NAME, 609 .desc = DRIVER_DESC, 610 .date = DRIVER_DATE, 611 .major = KMS_DRIVER_MAJOR, 612 .minor = KMS_DRIVER_MINOR, 613 .patchlevel = KMS_DRIVER_PATCHLEVEL, 614 }; 615 616 static struct drm_driver *driver; 617 static struct pci_driver *pdriver; 618 619 static struct pci_driver radeon_kms_pci_driver = { 620 .name = DRIVER_NAME, 621 .id_table = pciidlist, 622 .probe = radeon_pci_probe, 623 .remove = radeon_pci_remove, 624 .shutdown = radeon_pci_shutdown, 625 .driver.pm = &radeon_pm_ops, 626 }; 627 628 static int __init radeon_init(void) 629 { 630 if (vgacon_text_force() && radeon_modeset == -1) { 631 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 632 radeon_modeset = 0; 633 } 634 /* set to modesetting by default if not nomodeset */ 635 if (radeon_modeset == -1) 636 radeon_modeset = 1; 637 638 if (radeon_modeset == 1) { 639 DRM_INFO("radeon kernel modesetting enabled.\n"); 640 driver = &kms_driver; 641 pdriver = &radeon_kms_pci_driver; 642 driver->driver_features |= DRIVER_MODESET; 643 driver->num_ioctls = radeon_max_kms_ioctl; 644 radeon_register_atpx_handler(); 645 646 } else { 647 DRM_ERROR("No UMS support in radeon module!\n"); 648 return -EINVAL; 649 } 650 651 return pci_register_driver(pdriver); 652 } 653 654 static void __exit radeon_exit(void) 655 { 656 pci_unregister_driver(pdriver); 657 radeon_unregister_atpx_handler(); 658 mmu_notifier_synchronize(); 659 } 660 661 module_init(radeon_init); 662 module_exit(radeon_exit); 663 664 MODULE_AUTHOR(DRIVER_AUTHOR); 665 MODULE_DESCRIPTION(DRIVER_DESC); 666 MODULE_LICENSE("GPL and additional rights"); 667