1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pci.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/drm_file.h> 46 #include <drm/drm_gem.h> 47 #include <drm/drm_ioctl.h> 48 #include <drm/drm_pciids.h> 49 #include <drm/drm_probe_helper.h> 50 #include <drm/drm_vblank.h> 51 #include <drm/radeon_drm.h> 52 53 #include "radeon_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 2.0.0 - initial interface 58 * - 2.1.0 - add square tiling interface 59 * - 2.2.0 - add r6xx/r7xx const buffer support 60 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 61 * - 2.4.0 - add crtc id query 62 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 63 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 64 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 65 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 66 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 67 * 2.10.0 - fusion 2D tiling 68 * 2.11.0 - backend map, initial compute support for the CS checker 69 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 70 * 2.13.0 - virtual memory support, streamout 71 * 2.14.0 - add evergreen tiling informations 72 * 2.15.0 - add max_pipes query 73 * 2.16.0 - fix evergreen 2D tiled surface calculation 74 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 75 * 2.18.0 - r600-eg: allow "invalid" DB formats 76 * 2.19.0 - r600-eg: MSAA textures 77 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 78 * 2.21.0 - r600-r700: FMASK and CMASK 79 * 2.22.0 - r600 only: RESOLVE_BOX allowed 80 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 81 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 82 * 2.25.0 - eg+: new info request for num SE and num SH 83 * 2.26.0 - r600-eg: fix htile size computation 84 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 85 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 86 * 2.29.0 - R500 FP16 color clear registers 87 * 2.30.0 - fix for FMASK texturing 88 * 2.31.0 - Add fastfb support for rs690 89 * 2.32.0 - new info request for rings working 90 * 2.33.0 - Add SI tiling mode array query 91 * 2.34.0 - Add CIK tiling mode array query 92 * 2.35.0 - Add CIK macrotile mode array query 93 * 2.36.0 - Fix CIK DCE tiling setup 94 * 2.37.0 - allow GS ring setup on r6xx/r7xx 95 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 96 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 97 * 2.39.0 - Add INFO query for number of active CUs 98 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 99 * CS to GPU on >= r600 100 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 101 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 102 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 103 * 2.44.0 - SET_APPEND_CNT packet3 support 104 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 105 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 106 * 2.47.0 - Add UVD_NO_OP register support 107 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 108 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 109 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 110 */ 111 #define KMS_DRIVER_MAJOR 2 112 #define KMS_DRIVER_MINOR 50 113 #define KMS_DRIVER_PATCHLEVEL 0 114 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 115 void radeon_driver_unload_kms(struct drm_device *dev); 116 void radeon_driver_lastclose_kms(struct drm_device *dev); 117 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 118 void radeon_driver_postclose_kms(struct drm_device *dev, 119 struct drm_file *file_priv); 120 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 121 bool fbcon, bool freeze); 122 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 123 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 124 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 125 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 126 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 127 void radeon_gem_object_free(struct drm_gem_object *obj); 128 int radeon_gem_object_open(struct drm_gem_object *obj, 129 struct drm_file *file_priv); 130 void radeon_gem_object_close(struct drm_gem_object *obj, 131 struct drm_file *file_priv); 132 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj, 133 int flags); 134 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 135 unsigned int flags, int *vpos, int *hpos, 136 ktime_t *stime, ktime_t *etime, 137 const struct drm_display_mode *mode); 138 extern bool radeon_is_px(struct drm_device *dev); 139 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 140 extern int radeon_max_kms_ioctl; 141 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 142 int radeon_mode_dumb_mmap(struct drm_file *filp, 143 struct drm_device *dev, 144 uint32_t handle, uint64_t *offset_p); 145 int radeon_mode_dumb_create(struct drm_file *file_priv, 146 struct drm_device *dev, 147 struct drm_mode_create_dumb *args); 148 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 149 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 150 struct dma_buf_attachment *, 151 struct sg_table *sg); 152 int radeon_gem_prime_pin(struct drm_gem_object *obj); 153 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 154 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 155 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 156 157 /* atpx handler */ 158 #if defined(CONFIG_VGA_SWITCHEROO) 159 void radeon_register_atpx_handler(void); 160 void radeon_unregister_atpx_handler(void); 161 bool radeon_has_atpx_dgpu_power_cntl(void); 162 bool radeon_is_atpx_hybrid(void); 163 #else 164 static inline void radeon_register_atpx_handler(void) {} 165 static inline void radeon_unregister_atpx_handler(void) {} 166 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 167 static inline bool radeon_is_atpx_hybrid(void) { return false; } 168 #endif 169 170 int radeon_no_wb; 171 int radeon_modeset = -1; 172 int radeon_dynclks = -1; 173 int radeon_r4xx_atom = 0; 174 #ifdef __powerpc__ 175 /* Default to PCI on PowerPC (fdo #95017) */ 176 int radeon_agpmode = -1; 177 #else 178 int radeon_agpmode = 0; 179 #endif 180 int radeon_vram_limit = 0; 181 int radeon_gart_size = -1; /* auto */ 182 int radeon_benchmarking = 0; 183 int radeon_testing = 0; 184 int radeon_connector_table = 0; 185 int radeon_tv = 1; 186 int radeon_audio = -1; 187 int radeon_disp_priority = 0; 188 int radeon_hw_i2c = 0; 189 int radeon_pcie_gen2 = -1; 190 int radeon_msi = -1; 191 int radeon_lockup_timeout = 10000; 192 int radeon_fastfb = 0; 193 int radeon_dpm = -1; 194 int radeon_aspm = -1; 195 int radeon_runtime_pm = -1; 196 int radeon_hard_reset = 0; 197 int radeon_vm_size = 8; 198 int radeon_vm_block_size = -1; 199 int radeon_deep_color = 0; 200 int radeon_use_pflipirq = 2; 201 int radeon_bapm = -1; 202 int radeon_backlight = -1; 203 int radeon_auxch = -1; 204 int radeon_mst = 0; 205 int radeon_uvd = 1; 206 int radeon_vce = 1; 207 208 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 209 module_param_named(no_wb, radeon_no_wb, int, 0444); 210 211 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 212 module_param_named(modeset, radeon_modeset, int, 0400); 213 214 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 215 module_param_named(dynclks, radeon_dynclks, int, 0444); 216 217 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 218 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 219 220 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 221 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 222 223 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 224 module_param_named(agpmode, radeon_agpmode, int, 0444); 225 226 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 227 module_param_named(gartsize, radeon_gart_size, int, 0600); 228 229 MODULE_PARM_DESC(benchmark, "Run benchmark"); 230 module_param_named(benchmark, radeon_benchmarking, int, 0444); 231 232 MODULE_PARM_DESC(test, "Run tests"); 233 module_param_named(test, radeon_testing, int, 0444); 234 235 MODULE_PARM_DESC(connector_table, "Force connector table"); 236 module_param_named(connector_table, radeon_connector_table, int, 0444); 237 238 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 239 module_param_named(tv, radeon_tv, int, 0444); 240 241 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 242 module_param_named(audio, radeon_audio, int, 0444); 243 244 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 245 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 246 247 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 248 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 249 250 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 251 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 252 253 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 254 module_param_named(msi, radeon_msi, int, 0444); 255 256 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 257 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 258 259 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 260 module_param_named(fastfb, radeon_fastfb, int, 0444); 261 262 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 263 module_param_named(dpm, radeon_dpm, int, 0444); 264 265 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 266 module_param_named(aspm, radeon_aspm, int, 0444); 267 268 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 269 module_param_named(runpm, radeon_runtime_pm, int, 0444); 270 271 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 272 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 273 274 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 275 module_param_named(vm_size, radeon_vm_size, int, 0444); 276 277 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 278 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 279 280 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 281 module_param_named(deep_color, radeon_deep_color, int, 0444); 282 283 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 284 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 285 286 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 287 module_param_named(bapm, radeon_bapm, int, 0444); 288 289 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(backlight, radeon_backlight, int, 0444); 291 292 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(auxch, radeon_auxch, int, 0444); 294 295 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 296 module_param_named(mst, radeon_mst, int, 0444); 297 298 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 299 module_param_named(uvd, radeon_uvd, int, 0444); 300 301 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 302 module_param_named(vce, radeon_vce, int, 0444); 303 304 int radeon_si_support = 1; 305 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 306 module_param_named(si_support, radeon_si_support, int, 0444); 307 308 int radeon_cik_support = 1; 309 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 310 module_param_named(cik_support, radeon_cik_support, int, 0444); 311 312 static struct pci_device_id pciidlist[] = { 313 radeon_PCI_IDS 314 }; 315 316 MODULE_DEVICE_TABLE(pci, pciidlist); 317 318 static struct drm_driver kms_driver; 319 320 bool radeon_device_is_virtual(void); 321 322 static int radeon_pci_probe(struct pci_dev *pdev, 323 const struct pci_device_id *ent) 324 { 325 unsigned long flags = 0; 326 struct drm_device *dev; 327 int ret; 328 329 if (!ent) 330 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 331 332 flags = ent->driver_data; 333 334 if (!radeon_si_support) { 335 switch (flags & RADEON_FAMILY_MASK) { 336 case CHIP_TAHITI: 337 case CHIP_PITCAIRN: 338 case CHIP_VERDE: 339 case CHIP_OLAND: 340 case CHIP_HAINAN: 341 dev_info(&pdev->dev, 342 "SI support disabled by module param\n"); 343 return -ENODEV; 344 } 345 } 346 if (!radeon_cik_support) { 347 switch (flags & RADEON_FAMILY_MASK) { 348 case CHIP_KAVERI: 349 case CHIP_BONAIRE: 350 case CHIP_HAWAII: 351 case CHIP_KABINI: 352 case CHIP_MULLINS: 353 dev_info(&pdev->dev, 354 "CIK support disabled by module param\n"); 355 return -ENODEV; 356 } 357 } 358 359 if (vga_switcheroo_client_probe_defer(pdev)) 360 return -EPROBE_DEFER; 361 362 /* Get rid of things like offb */ 363 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 364 if (ret) 365 return ret; 366 367 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 368 if (IS_ERR(dev)) 369 return PTR_ERR(dev); 370 371 ret = pci_enable_device(pdev); 372 if (ret) 373 goto err_free; 374 375 dev->pdev = pdev; 376 #ifdef __alpha__ 377 dev->hose = pdev->sysdata; 378 #endif 379 380 pci_set_drvdata(pdev, dev); 381 382 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) 383 dev->agp = drm_agp_init(dev); 384 if (dev->agp) { 385 dev->agp->agp_mtrr = arch_phys_wc_add( 386 dev->agp->agp_info.aper_base, 387 dev->agp->agp_info.aper_size * 388 1024 * 1024); 389 } 390 391 ret = drm_dev_register(dev, ent->driver_data); 392 if (ret) 393 goto err_agp; 394 395 return 0; 396 397 err_agp: 398 if (dev->agp) 399 arch_phys_wc_del(dev->agp->agp_mtrr); 400 kfree(dev->agp); 401 pci_disable_device(pdev); 402 err_free: 403 drm_dev_put(dev); 404 return ret; 405 } 406 407 static void 408 radeon_pci_remove(struct pci_dev *pdev) 409 { 410 struct drm_device *dev = pci_get_drvdata(pdev); 411 412 drm_put_dev(dev); 413 } 414 415 static void 416 radeon_pci_shutdown(struct pci_dev *pdev) 417 { 418 /* if we are running in a VM, make sure the device 419 * torn down properly on reboot/shutdown 420 */ 421 if (radeon_device_is_virtual()) 422 radeon_pci_remove(pdev); 423 424 #ifdef CONFIG_PPC64 425 /* 426 * Some adapters need to be suspended before a 427 * shutdown occurs in order to prevent an error 428 * during kexec. 429 * Make this power specific becauase it breaks 430 * some non-power boards. 431 */ 432 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 433 #endif 434 } 435 436 static int radeon_pmops_suspend(struct device *dev) 437 { 438 struct drm_device *drm_dev = dev_get_drvdata(dev); 439 return radeon_suspend_kms(drm_dev, true, true, false); 440 } 441 442 static int radeon_pmops_resume(struct device *dev) 443 { 444 struct drm_device *drm_dev = dev_get_drvdata(dev); 445 446 /* GPU comes up enabled by the bios on resume */ 447 if (radeon_is_px(drm_dev)) { 448 pm_runtime_disable(dev); 449 pm_runtime_set_active(dev); 450 pm_runtime_enable(dev); 451 } 452 453 return radeon_resume_kms(drm_dev, true, true); 454 } 455 456 static int radeon_pmops_freeze(struct device *dev) 457 { 458 struct drm_device *drm_dev = dev_get_drvdata(dev); 459 return radeon_suspend_kms(drm_dev, false, true, true); 460 } 461 462 static int radeon_pmops_thaw(struct device *dev) 463 { 464 struct drm_device *drm_dev = dev_get_drvdata(dev); 465 return radeon_resume_kms(drm_dev, false, true); 466 } 467 468 static int radeon_pmops_runtime_suspend(struct device *dev) 469 { 470 struct pci_dev *pdev = to_pci_dev(dev); 471 struct drm_device *drm_dev = pci_get_drvdata(pdev); 472 int ret; 473 474 if (!radeon_is_px(drm_dev)) { 475 pm_runtime_forbid(dev); 476 return -EBUSY; 477 } 478 479 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 480 drm_kms_helper_poll_disable(drm_dev); 481 482 ret = radeon_suspend_kms(drm_dev, false, false, false); 483 pci_save_state(pdev); 484 pci_disable_device(pdev); 485 pci_ignore_hotplug(pdev); 486 if (radeon_is_atpx_hybrid()) 487 pci_set_power_state(pdev, PCI_D3cold); 488 else if (!radeon_has_atpx_dgpu_power_cntl()) 489 pci_set_power_state(pdev, PCI_D3hot); 490 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 491 492 return 0; 493 } 494 495 static int radeon_pmops_runtime_resume(struct device *dev) 496 { 497 struct pci_dev *pdev = to_pci_dev(dev); 498 struct drm_device *drm_dev = pci_get_drvdata(pdev); 499 int ret; 500 501 if (!radeon_is_px(drm_dev)) 502 return -EINVAL; 503 504 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 505 506 if (radeon_is_atpx_hybrid() || 507 !radeon_has_atpx_dgpu_power_cntl()) 508 pci_set_power_state(pdev, PCI_D0); 509 pci_restore_state(pdev); 510 ret = pci_enable_device(pdev); 511 if (ret) 512 return ret; 513 pci_set_master(pdev); 514 515 ret = radeon_resume_kms(drm_dev, false, false); 516 drm_kms_helper_poll_enable(drm_dev); 517 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 518 return 0; 519 } 520 521 static int radeon_pmops_runtime_idle(struct device *dev) 522 { 523 struct drm_device *drm_dev = dev_get_drvdata(dev); 524 struct drm_crtc *crtc; 525 526 if (!radeon_is_px(drm_dev)) { 527 pm_runtime_forbid(dev); 528 return -EBUSY; 529 } 530 531 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 532 if (crtc->enabled) { 533 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 534 return -EBUSY; 535 } 536 } 537 538 pm_runtime_mark_last_busy(dev); 539 pm_runtime_autosuspend(dev); 540 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 541 return 1; 542 } 543 544 long radeon_drm_ioctl(struct file *filp, 545 unsigned int cmd, unsigned long arg) 546 { 547 struct drm_file *file_priv = filp->private_data; 548 struct drm_device *dev; 549 long ret; 550 dev = file_priv->minor->dev; 551 ret = pm_runtime_get_sync(dev->dev); 552 if (ret < 0) 553 return ret; 554 555 ret = drm_ioctl(filp, cmd, arg); 556 557 pm_runtime_mark_last_busy(dev->dev); 558 pm_runtime_put_autosuspend(dev->dev); 559 return ret; 560 } 561 562 #ifdef CONFIG_COMPAT 563 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 564 { 565 unsigned int nr = DRM_IOCTL_NR(cmd); 566 int ret; 567 568 if (nr < DRM_COMMAND_BASE) 569 return drm_compat_ioctl(filp, cmd, arg); 570 571 ret = radeon_drm_ioctl(filp, cmd, arg); 572 573 return ret; 574 } 575 #endif 576 577 static const struct dev_pm_ops radeon_pm_ops = { 578 .suspend = radeon_pmops_suspend, 579 .resume = radeon_pmops_resume, 580 .freeze = radeon_pmops_freeze, 581 .thaw = radeon_pmops_thaw, 582 .poweroff = radeon_pmops_freeze, 583 .restore = radeon_pmops_resume, 584 .runtime_suspend = radeon_pmops_runtime_suspend, 585 .runtime_resume = radeon_pmops_runtime_resume, 586 .runtime_idle = radeon_pmops_runtime_idle, 587 }; 588 589 static const struct file_operations radeon_driver_kms_fops = { 590 .owner = THIS_MODULE, 591 .open = drm_open, 592 .release = drm_release, 593 .unlocked_ioctl = radeon_drm_ioctl, 594 .mmap = radeon_mmap, 595 .poll = drm_poll, 596 .read = drm_read, 597 #ifdef CONFIG_COMPAT 598 .compat_ioctl = radeon_kms_compat_ioctl, 599 #endif 600 }; 601 602 static struct drm_driver kms_driver = { 603 .driver_features = 604 DRIVER_GEM | DRIVER_RENDER, 605 .load = radeon_driver_load_kms, 606 .open = radeon_driver_open_kms, 607 .postclose = radeon_driver_postclose_kms, 608 .lastclose = radeon_driver_lastclose_kms, 609 .unload = radeon_driver_unload_kms, 610 .irq_preinstall = radeon_driver_irq_preinstall_kms, 611 .irq_postinstall = radeon_driver_irq_postinstall_kms, 612 .irq_uninstall = radeon_driver_irq_uninstall_kms, 613 .irq_handler = radeon_driver_irq_handler_kms, 614 .ioctls = radeon_ioctls_kms, 615 .gem_free_object_unlocked = radeon_gem_object_free, 616 .gem_open_object = radeon_gem_object_open, 617 .gem_close_object = radeon_gem_object_close, 618 .dumb_create = radeon_mode_dumb_create, 619 .dumb_map_offset = radeon_mode_dumb_mmap, 620 .fops = &radeon_driver_kms_fops, 621 622 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 623 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 624 .gem_prime_export = radeon_gem_prime_export, 625 .gem_prime_pin = radeon_gem_prime_pin, 626 .gem_prime_unpin = radeon_gem_prime_unpin, 627 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 628 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 629 .gem_prime_vmap = radeon_gem_prime_vmap, 630 .gem_prime_vunmap = radeon_gem_prime_vunmap, 631 632 .name = DRIVER_NAME, 633 .desc = DRIVER_DESC, 634 .date = DRIVER_DATE, 635 .major = KMS_DRIVER_MAJOR, 636 .minor = KMS_DRIVER_MINOR, 637 .patchlevel = KMS_DRIVER_PATCHLEVEL, 638 }; 639 640 static struct drm_driver *driver; 641 static struct pci_driver *pdriver; 642 643 static struct pci_driver radeon_kms_pci_driver = { 644 .name = DRIVER_NAME, 645 .id_table = pciidlist, 646 .probe = radeon_pci_probe, 647 .remove = radeon_pci_remove, 648 .shutdown = radeon_pci_shutdown, 649 .driver.pm = &radeon_pm_ops, 650 }; 651 652 static int __init radeon_init(void) 653 { 654 if (vgacon_text_force() && radeon_modeset == -1) { 655 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 656 radeon_modeset = 0; 657 } 658 /* set to modesetting by default if not nomodeset */ 659 if (radeon_modeset == -1) 660 radeon_modeset = 1; 661 662 if (radeon_modeset == 1) { 663 DRM_INFO("radeon kernel modesetting enabled.\n"); 664 driver = &kms_driver; 665 pdriver = &radeon_kms_pci_driver; 666 driver->driver_features |= DRIVER_MODESET; 667 driver->num_ioctls = radeon_max_kms_ioctl; 668 radeon_register_atpx_handler(); 669 670 } else { 671 DRM_ERROR("No UMS support in radeon module!\n"); 672 return -EINVAL; 673 } 674 675 return pci_register_driver(pdriver); 676 } 677 678 static void __exit radeon_exit(void) 679 { 680 pci_unregister_driver(pdriver); 681 radeon_unregister_atpx_handler(); 682 mmu_notifier_synchronize(); 683 } 684 685 module_init(radeon_init); 686 module_exit(radeon_exit); 687 688 MODULE_AUTHOR(DRIVER_AUTHOR); 689 MODULE_DESCRIPTION(DRIVER_DESC); 690 MODULE_LICENSE("GPL and additional rights"); 691