1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pci.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/drm_file.h> 46 #include <drm/drm_gem.h> 47 #include <drm/drm_ioctl.h> 48 #include <drm/drm_pciids.h> 49 #include <drm/drm_probe_helper.h> 50 #include <drm/drm_vblank.h> 51 #include <drm/radeon_drm.h> 52 53 #include "radeon_drv.h" 54 #include "radeon.h" 55 56 /* 57 * KMS wrapper. 58 * - 2.0.0 - initial interface 59 * - 2.1.0 - add square tiling interface 60 * - 2.2.0 - add r6xx/r7xx const buffer support 61 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 62 * - 2.4.0 - add crtc id query 63 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 64 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 65 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 66 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 67 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 68 * 2.10.0 - fusion 2D tiling 69 * 2.11.0 - backend map, initial compute support for the CS checker 70 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 71 * 2.13.0 - virtual memory support, streamout 72 * 2.14.0 - add evergreen tiling informations 73 * 2.15.0 - add max_pipes query 74 * 2.16.0 - fix evergreen 2D tiled surface calculation 75 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 76 * 2.18.0 - r600-eg: allow "invalid" DB formats 77 * 2.19.0 - r600-eg: MSAA textures 78 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 79 * 2.21.0 - r600-r700: FMASK and CMASK 80 * 2.22.0 - r600 only: RESOLVE_BOX allowed 81 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 82 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 83 * 2.25.0 - eg+: new info request for num SE and num SH 84 * 2.26.0 - r600-eg: fix htile size computation 85 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 86 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 87 * 2.29.0 - R500 FP16 color clear registers 88 * 2.30.0 - fix for FMASK texturing 89 * 2.31.0 - Add fastfb support for rs690 90 * 2.32.0 - new info request for rings working 91 * 2.33.0 - Add SI tiling mode array query 92 * 2.34.0 - Add CIK tiling mode array query 93 * 2.35.0 - Add CIK macrotile mode array query 94 * 2.36.0 - Fix CIK DCE tiling setup 95 * 2.37.0 - allow GS ring setup on r6xx/r7xx 96 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 97 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 98 * 2.39.0 - Add INFO query for number of active CUs 99 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 100 * CS to GPU on >= r600 101 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 102 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 103 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 104 * 2.44.0 - SET_APPEND_CNT packet3 support 105 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 106 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 107 * 2.47.0 - Add UVD_NO_OP register support 108 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 109 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 110 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 111 */ 112 #define KMS_DRIVER_MAJOR 2 113 #define KMS_DRIVER_MINOR 50 114 #define KMS_DRIVER_PATCHLEVEL 0 115 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 116 void radeon_driver_unload_kms(struct drm_device *dev); 117 void radeon_driver_lastclose_kms(struct drm_device *dev); 118 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 119 void radeon_driver_postclose_kms(struct drm_device *dev, 120 struct drm_file *file_priv); 121 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 122 bool fbcon, bool freeze); 123 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 124 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 125 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 126 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 127 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 128 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 129 unsigned int flags, int *vpos, int *hpos, 130 ktime_t *stime, ktime_t *etime, 131 const struct drm_display_mode *mode); 132 extern bool radeon_is_px(struct drm_device *dev); 133 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 134 int radeon_mode_dumb_mmap(struct drm_file *filp, 135 struct drm_device *dev, 136 uint32_t handle, uint64_t *offset_p); 137 int radeon_mode_dumb_create(struct drm_file *file_priv, 138 struct drm_device *dev, 139 struct drm_mode_create_dumb *args); 140 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 141 struct dma_buf_attachment *, 142 struct sg_table *sg); 143 144 /* atpx handler */ 145 #if defined(CONFIG_VGA_SWITCHEROO) 146 void radeon_register_atpx_handler(void); 147 void radeon_unregister_atpx_handler(void); 148 bool radeon_has_atpx_dgpu_power_cntl(void); 149 bool radeon_is_atpx_hybrid(void); 150 #else 151 static inline void radeon_register_atpx_handler(void) {} 152 static inline void radeon_unregister_atpx_handler(void) {} 153 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 154 static inline bool radeon_is_atpx_hybrid(void) { return false; } 155 #endif 156 157 int radeon_no_wb; 158 int radeon_modeset = -1; 159 int radeon_dynclks = -1; 160 int radeon_r4xx_atom = 0; 161 int radeon_agpmode = -1; 162 int radeon_vram_limit = 0; 163 int radeon_gart_size = -1; /* auto */ 164 int radeon_benchmarking = 0; 165 int radeon_testing = 0; 166 int radeon_connector_table = 0; 167 int radeon_tv = 1; 168 int radeon_audio = -1; 169 int radeon_disp_priority = 0; 170 int radeon_hw_i2c = 0; 171 int radeon_pcie_gen2 = -1; 172 int radeon_msi = -1; 173 int radeon_lockup_timeout = 10000; 174 int radeon_fastfb = 0; 175 int radeon_dpm = -1; 176 int radeon_aspm = -1; 177 int radeon_runtime_pm = -1; 178 int radeon_hard_reset = 0; 179 int radeon_vm_size = 8; 180 int radeon_vm_block_size = -1; 181 int radeon_deep_color = 0; 182 int radeon_use_pflipirq = 2; 183 int radeon_bapm = -1; 184 int radeon_backlight = -1; 185 int radeon_auxch = -1; 186 int radeon_mst = 0; 187 int radeon_uvd = 1; 188 int radeon_vce = 1; 189 190 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 191 module_param_named(no_wb, radeon_no_wb, int, 0444); 192 193 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 194 module_param_named(modeset, radeon_modeset, int, 0400); 195 196 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 197 module_param_named(dynclks, radeon_dynclks, int, 0444); 198 199 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 200 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 201 202 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 203 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 204 205 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 206 module_param_named(agpmode, radeon_agpmode, int, 0444); 207 208 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 209 module_param_named(gartsize, radeon_gart_size, int, 0600); 210 211 MODULE_PARM_DESC(benchmark, "Run benchmark"); 212 module_param_named(benchmark, radeon_benchmarking, int, 0444); 213 214 MODULE_PARM_DESC(test, "Run tests"); 215 module_param_named(test, radeon_testing, int, 0444); 216 217 MODULE_PARM_DESC(connector_table, "Force connector table"); 218 module_param_named(connector_table, radeon_connector_table, int, 0444); 219 220 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 221 module_param_named(tv, radeon_tv, int, 0444); 222 223 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 224 module_param_named(audio, radeon_audio, int, 0444); 225 226 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 227 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 228 229 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 230 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 231 232 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 233 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 234 235 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 236 module_param_named(msi, radeon_msi, int, 0444); 237 238 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 239 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 240 241 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 242 module_param_named(fastfb, radeon_fastfb, int, 0444); 243 244 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 245 module_param_named(dpm, radeon_dpm, int, 0444); 246 247 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 248 module_param_named(aspm, radeon_aspm, int, 0444); 249 250 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 251 module_param_named(runpm, radeon_runtime_pm, int, 0444); 252 253 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 254 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 255 256 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 257 module_param_named(vm_size, radeon_vm_size, int, 0444); 258 259 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 260 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 261 262 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 263 module_param_named(deep_color, radeon_deep_color, int, 0444); 264 265 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 266 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 267 268 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 269 module_param_named(bapm, radeon_bapm, int, 0444); 270 271 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 272 module_param_named(backlight, radeon_backlight, int, 0444); 273 274 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 275 module_param_named(auxch, radeon_auxch, int, 0444); 276 277 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 278 module_param_named(mst, radeon_mst, int, 0444); 279 280 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 281 module_param_named(uvd, radeon_uvd, int, 0444); 282 283 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 284 module_param_named(vce, radeon_vce, int, 0444); 285 286 int radeon_si_support = 1; 287 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 288 module_param_named(si_support, radeon_si_support, int, 0444); 289 290 int radeon_cik_support = 1; 291 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 292 module_param_named(cik_support, radeon_cik_support, int, 0444); 293 294 static struct pci_device_id pciidlist[] = { 295 radeon_PCI_IDS 296 }; 297 298 MODULE_DEVICE_TABLE(pci, pciidlist); 299 300 static const struct drm_driver kms_driver; 301 302 bool radeon_device_is_virtual(void); 303 304 static int radeon_pci_probe(struct pci_dev *pdev, 305 const struct pci_device_id *ent) 306 { 307 unsigned long flags = 0; 308 struct drm_device *dev; 309 int ret; 310 311 if (!ent) 312 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 313 314 flags = ent->driver_data; 315 316 if (!radeon_si_support) { 317 switch (flags & RADEON_FAMILY_MASK) { 318 case CHIP_TAHITI: 319 case CHIP_PITCAIRN: 320 case CHIP_VERDE: 321 case CHIP_OLAND: 322 case CHIP_HAINAN: 323 dev_info(&pdev->dev, 324 "SI support disabled by module param\n"); 325 return -ENODEV; 326 } 327 } 328 if (!radeon_cik_support) { 329 switch (flags & RADEON_FAMILY_MASK) { 330 case CHIP_KAVERI: 331 case CHIP_BONAIRE: 332 case CHIP_HAWAII: 333 case CHIP_KABINI: 334 case CHIP_MULLINS: 335 dev_info(&pdev->dev, 336 "CIK support disabled by module param\n"); 337 return -ENODEV; 338 } 339 } 340 341 if (vga_switcheroo_client_probe_defer(pdev)) 342 return -EPROBE_DEFER; 343 344 /* Get rid of things like offb */ 345 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 346 if (ret) 347 return ret; 348 349 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 350 if (IS_ERR(dev)) 351 return PTR_ERR(dev); 352 353 ret = pci_enable_device(pdev); 354 if (ret) 355 goto err_free; 356 357 dev->pdev = pdev; 358 #ifdef __alpha__ 359 dev->hose = pdev->sysdata; 360 #endif 361 362 pci_set_drvdata(pdev, dev); 363 364 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) 365 dev->agp = drm_agp_init(dev); 366 if (dev->agp) { 367 dev->agp->agp_mtrr = arch_phys_wc_add( 368 dev->agp->agp_info.aper_base, 369 dev->agp->agp_info.aper_size * 370 1024 * 1024); 371 } 372 373 ret = drm_dev_register(dev, ent->driver_data); 374 if (ret) 375 goto err_agp; 376 377 return 0; 378 379 err_agp: 380 if (dev->agp) 381 arch_phys_wc_del(dev->agp->agp_mtrr); 382 kfree(dev->agp); 383 pci_disable_device(pdev); 384 err_free: 385 drm_dev_put(dev); 386 return ret; 387 } 388 389 static void 390 radeon_pci_remove(struct pci_dev *pdev) 391 { 392 struct drm_device *dev = pci_get_drvdata(pdev); 393 394 drm_put_dev(dev); 395 } 396 397 static void 398 radeon_pci_shutdown(struct pci_dev *pdev) 399 { 400 /* if we are running in a VM, make sure the device 401 * torn down properly on reboot/shutdown 402 */ 403 if (radeon_device_is_virtual()) 404 radeon_pci_remove(pdev); 405 406 #ifdef CONFIG_PPC64 407 /* 408 * Some adapters need to be suspended before a 409 * shutdown occurs in order to prevent an error 410 * during kexec. 411 * Make this power specific becauase it breaks 412 * some non-power boards. 413 */ 414 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 415 #endif 416 } 417 418 static int radeon_pmops_suspend(struct device *dev) 419 { 420 struct drm_device *drm_dev = dev_get_drvdata(dev); 421 return radeon_suspend_kms(drm_dev, true, true, false); 422 } 423 424 static int radeon_pmops_resume(struct device *dev) 425 { 426 struct drm_device *drm_dev = dev_get_drvdata(dev); 427 428 /* GPU comes up enabled by the bios on resume */ 429 if (radeon_is_px(drm_dev)) { 430 pm_runtime_disable(dev); 431 pm_runtime_set_active(dev); 432 pm_runtime_enable(dev); 433 } 434 435 return radeon_resume_kms(drm_dev, true, true); 436 } 437 438 static int radeon_pmops_freeze(struct device *dev) 439 { 440 struct drm_device *drm_dev = dev_get_drvdata(dev); 441 return radeon_suspend_kms(drm_dev, false, true, true); 442 } 443 444 static int radeon_pmops_thaw(struct device *dev) 445 { 446 struct drm_device *drm_dev = dev_get_drvdata(dev); 447 return radeon_resume_kms(drm_dev, false, true); 448 } 449 450 static int radeon_pmops_runtime_suspend(struct device *dev) 451 { 452 struct pci_dev *pdev = to_pci_dev(dev); 453 struct drm_device *drm_dev = pci_get_drvdata(pdev); 454 int ret; 455 456 if (!radeon_is_px(drm_dev)) { 457 pm_runtime_forbid(dev); 458 return -EBUSY; 459 } 460 461 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 462 drm_kms_helper_poll_disable(drm_dev); 463 464 ret = radeon_suspend_kms(drm_dev, false, false, false); 465 pci_save_state(pdev); 466 pci_disable_device(pdev); 467 pci_ignore_hotplug(pdev); 468 if (radeon_is_atpx_hybrid()) 469 pci_set_power_state(pdev, PCI_D3cold); 470 else if (!radeon_has_atpx_dgpu_power_cntl()) 471 pci_set_power_state(pdev, PCI_D3hot); 472 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 473 474 return 0; 475 } 476 477 static int radeon_pmops_runtime_resume(struct device *dev) 478 { 479 struct pci_dev *pdev = to_pci_dev(dev); 480 struct drm_device *drm_dev = pci_get_drvdata(pdev); 481 int ret; 482 483 if (!radeon_is_px(drm_dev)) 484 return -EINVAL; 485 486 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 487 488 if (radeon_is_atpx_hybrid() || 489 !radeon_has_atpx_dgpu_power_cntl()) 490 pci_set_power_state(pdev, PCI_D0); 491 pci_restore_state(pdev); 492 ret = pci_enable_device(pdev); 493 if (ret) 494 return ret; 495 pci_set_master(pdev); 496 497 ret = radeon_resume_kms(drm_dev, false, false); 498 drm_kms_helper_poll_enable(drm_dev); 499 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 500 return 0; 501 } 502 503 static int radeon_pmops_runtime_idle(struct device *dev) 504 { 505 struct drm_device *drm_dev = dev_get_drvdata(dev); 506 struct drm_crtc *crtc; 507 508 if (!radeon_is_px(drm_dev)) { 509 pm_runtime_forbid(dev); 510 return -EBUSY; 511 } 512 513 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 514 if (crtc->enabled) { 515 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 516 return -EBUSY; 517 } 518 } 519 520 pm_runtime_mark_last_busy(dev); 521 pm_runtime_autosuspend(dev); 522 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 523 return 1; 524 } 525 526 long radeon_drm_ioctl(struct file *filp, 527 unsigned int cmd, unsigned long arg) 528 { 529 struct drm_file *file_priv = filp->private_data; 530 struct drm_device *dev; 531 long ret; 532 dev = file_priv->minor->dev; 533 ret = pm_runtime_get_sync(dev->dev); 534 if (ret < 0) { 535 pm_runtime_put_autosuspend(dev->dev); 536 return ret; 537 } 538 539 ret = drm_ioctl(filp, cmd, arg); 540 541 pm_runtime_mark_last_busy(dev->dev); 542 pm_runtime_put_autosuspend(dev->dev); 543 return ret; 544 } 545 546 #ifdef CONFIG_COMPAT 547 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 548 { 549 unsigned int nr = DRM_IOCTL_NR(cmd); 550 int ret; 551 552 if (nr < DRM_COMMAND_BASE) 553 return drm_compat_ioctl(filp, cmd, arg); 554 555 ret = radeon_drm_ioctl(filp, cmd, arg); 556 557 return ret; 558 } 559 #endif 560 561 static const struct dev_pm_ops radeon_pm_ops = { 562 .suspend = radeon_pmops_suspend, 563 .resume = radeon_pmops_resume, 564 .freeze = radeon_pmops_freeze, 565 .thaw = radeon_pmops_thaw, 566 .poweroff = radeon_pmops_freeze, 567 .restore = radeon_pmops_resume, 568 .runtime_suspend = radeon_pmops_runtime_suspend, 569 .runtime_resume = radeon_pmops_runtime_resume, 570 .runtime_idle = radeon_pmops_runtime_idle, 571 }; 572 573 static const struct file_operations radeon_driver_kms_fops = { 574 .owner = THIS_MODULE, 575 .open = drm_open, 576 .release = drm_release, 577 .unlocked_ioctl = radeon_drm_ioctl, 578 .mmap = radeon_mmap, 579 .poll = drm_poll, 580 .read = drm_read, 581 #ifdef CONFIG_COMPAT 582 .compat_ioctl = radeon_kms_compat_ioctl, 583 #endif 584 }; 585 586 static const struct drm_ioctl_desc radeon_ioctls_kms[] = { 587 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 588 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 589 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 590 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 591 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 592 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 593 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 594 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 595 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 596 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 597 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 598 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 599 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 600 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 601 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 602 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 603 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 604 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 605 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 606 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 607 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 608 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 609 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 610 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 611 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 612 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 613 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 614 /* KMS */ 615 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 616 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 617 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 618 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 619 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 620 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 621 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 622 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 623 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 624 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 625 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 626 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 627 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 628 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 629 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 630 }; 631 632 static const struct drm_driver kms_driver = { 633 .driver_features = 634 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, 635 .load = radeon_driver_load_kms, 636 .open = radeon_driver_open_kms, 637 .postclose = radeon_driver_postclose_kms, 638 .lastclose = radeon_driver_lastclose_kms, 639 .unload = radeon_driver_unload_kms, 640 .irq_preinstall = radeon_driver_irq_preinstall_kms, 641 .irq_postinstall = radeon_driver_irq_postinstall_kms, 642 .irq_uninstall = radeon_driver_irq_uninstall_kms, 643 .irq_handler = radeon_driver_irq_handler_kms, 644 .ioctls = radeon_ioctls_kms, 645 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), 646 .dumb_create = radeon_mode_dumb_create, 647 .dumb_map_offset = radeon_mode_dumb_mmap, 648 .fops = &radeon_driver_kms_fops, 649 650 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 651 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 652 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 653 654 .name = DRIVER_NAME, 655 .desc = DRIVER_DESC, 656 .date = DRIVER_DATE, 657 .major = KMS_DRIVER_MAJOR, 658 .minor = KMS_DRIVER_MINOR, 659 .patchlevel = KMS_DRIVER_PATCHLEVEL, 660 }; 661 662 static struct pci_driver radeon_kms_pci_driver = { 663 .name = DRIVER_NAME, 664 .id_table = pciidlist, 665 .probe = radeon_pci_probe, 666 .remove = radeon_pci_remove, 667 .shutdown = radeon_pci_shutdown, 668 .driver.pm = &radeon_pm_ops, 669 }; 670 671 static int __init radeon_module_init(void) 672 { 673 if (vgacon_text_force() && radeon_modeset == -1) { 674 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 675 radeon_modeset = 0; 676 } 677 678 if (radeon_modeset == 0) { 679 DRM_ERROR("No UMS support in radeon module!\n"); 680 return -EINVAL; 681 } 682 683 DRM_INFO("radeon kernel modesetting enabled.\n"); 684 radeon_register_atpx_handler(); 685 686 return pci_register_driver(&radeon_kms_pci_driver); 687 } 688 689 static void __exit radeon_module_exit(void) 690 { 691 pci_unregister_driver(&radeon_kms_pci_driver); 692 radeon_unregister_atpx_handler(); 693 mmu_notifier_synchronize(); 694 } 695 696 module_init(radeon_module_init); 697 module_exit(radeon_module_exit); 698 699 MODULE_AUTHOR(DRIVER_AUTHOR); 700 MODULE_DESCRIPTION(DRIVER_DESC); 701 MODULE_LICENSE("GPL and additional rights"); 702