1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 39 #include <drm/drm_crtc_helper.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_fb_helper.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_gem.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_pci.h> 46 #include <drm/drm_pciids.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_vblank.h> 49 #include <drm/radeon_drm.h> 50 51 #include "radeon_drv.h" 52 53 /* 54 * KMS wrapper. 55 * - 2.0.0 - initial interface 56 * - 2.1.0 - add square tiling interface 57 * - 2.2.0 - add r6xx/r7xx const buffer support 58 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 59 * - 2.4.0 - add crtc id query 60 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 61 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 62 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 63 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 64 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 65 * 2.10.0 - fusion 2D tiling 66 * 2.11.0 - backend map, initial compute support for the CS checker 67 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 68 * 2.13.0 - virtual memory support, streamout 69 * 2.14.0 - add evergreen tiling informations 70 * 2.15.0 - add max_pipes query 71 * 2.16.0 - fix evergreen 2D tiled surface calculation 72 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 73 * 2.18.0 - r600-eg: allow "invalid" DB formats 74 * 2.19.0 - r600-eg: MSAA textures 75 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 76 * 2.21.0 - r600-r700: FMASK and CMASK 77 * 2.22.0 - r600 only: RESOLVE_BOX allowed 78 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 79 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 80 * 2.25.0 - eg+: new info request for num SE and num SH 81 * 2.26.0 - r600-eg: fix htile size computation 82 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 83 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 84 * 2.29.0 - R500 FP16 color clear registers 85 * 2.30.0 - fix for FMASK texturing 86 * 2.31.0 - Add fastfb support for rs690 87 * 2.32.0 - new info request for rings working 88 * 2.33.0 - Add SI tiling mode array query 89 * 2.34.0 - Add CIK tiling mode array query 90 * 2.35.0 - Add CIK macrotile mode array query 91 * 2.36.0 - Fix CIK DCE tiling setup 92 * 2.37.0 - allow GS ring setup on r6xx/r7xx 93 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 94 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 95 * 2.39.0 - Add INFO query for number of active CUs 96 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 97 * CS to GPU on >= r600 98 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 99 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 100 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 101 * 2.44.0 - SET_APPEND_CNT packet3 support 102 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 103 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 104 * 2.47.0 - Add UVD_NO_OP register support 105 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 106 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 107 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 108 */ 109 #define KMS_DRIVER_MAJOR 2 110 #define KMS_DRIVER_MINOR 50 111 #define KMS_DRIVER_PATCHLEVEL 0 112 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 113 void radeon_driver_unload_kms(struct drm_device *dev); 114 void radeon_driver_lastclose_kms(struct drm_device *dev); 115 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 116 void radeon_driver_postclose_kms(struct drm_device *dev, 117 struct drm_file *file_priv); 118 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 119 bool fbcon, bool freeze); 120 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 121 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 122 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 123 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 124 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 125 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 126 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 127 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 128 void radeon_gem_object_free(struct drm_gem_object *obj); 129 int radeon_gem_object_open(struct drm_gem_object *obj, 130 struct drm_file *file_priv); 131 void radeon_gem_object_close(struct drm_gem_object *obj, 132 struct drm_file *file_priv); 133 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj, 134 int flags); 135 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 136 unsigned int flags, int *vpos, int *hpos, 137 ktime_t *stime, ktime_t *etime, 138 const struct drm_display_mode *mode); 139 extern bool radeon_is_px(struct drm_device *dev); 140 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 141 extern int radeon_max_kms_ioctl; 142 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 143 int radeon_mode_dumb_mmap(struct drm_file *filp, 144 struct drm_device *dev, 145 uint32_t handle, uint64_t *offset_p); 146 int radeon_mode_dumb_create(struct drm_file *file_priv, 147 struct drm_device *dev, 148 struct drm_mode_create_dumb *args); 149 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 150 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 151 struct dma_buf_attachment *, 152 struct sg_table *sg); 153 int radeon_gem_prime_pin(struct drm_gem_object *obj); 154 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 155 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 156 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 157 158 /* atpx handler */ 159 #if defined(CONFIG_VGA_SWITCHEROO) 160 void radeon_register_atpx_handler(void); 161 void radeon_unregister_atpx_handler(void); 162 bool radeon_has_atpx_dgpu_power_cntl(void); 163 bool radeon_is_atpx_hybrid(void); 164 #else 165 static inline void radeon_register_atpx_handler(void) {} 166 static inline void radeon_unregister_atpx_handler(void) {} 167 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 168 static inline bool radeon_is_atpx_hybrid(void) { return false; } 169 #endif 170 171 int radeon_no_wb; 172 int radeon_modeset = -1; 173 int radeon_dynclks = -1; 174 int radeon_r4xx_atom = 0; 175 #ifdef __powerpc__ 176 /* Default to PCI on PowerPC (fdo #95017) */ 177 int radeon_agpmode = -1; 178 #else 179 int radeon_agpmode = 0; 180 #endif 181 int radeon_vram_limit = 0; 182 int radeon_gart_size = -1; /* auto */ 183 int radeon_benchmarking = 0; 184 int radeon_testing = 0; 185 int radeon_connector_table = 0; 186 int radeon_tv = 1; 187 int radeon_audio = -1; 188 int radeon_disp_priority = 0; 189 int radeon_hw_i2c = 0; 190 int radeon_pcie_gen2 = -1; 191 int radeon_msi = -1; 192 int radeon_lockup_timeout = 10000; 193 int radeon_fastfb = 0; 194 int radeon_dpm = -1; 195 int radeon_aspm = -1; 196 int radeon_runtime_pm = -1; 197 int radeon_hard_reset = 0; 198 int radeon_vm_size = 8; 199 int radeon_vm_block_size = -1; 200 int radeon_deep_color = 0; 201 int radeon_use_pflipirq = 2; 202 int radeon_bapm = -1; 203 int radeon_backlight = -1; 204 int radeon_auxch = -1; 205 int radeon_mst = 0; 206 int radeon_uvd = 1; 207 int radeon_vce = 1; 208 209 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 210 module_param_named(no_wb, radeon_no_wb, int, 0444); 211 212 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 213 module_param_named(modeset, radeon_modeset, int, 0400); 214 215 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 216 module_param_named(dynclks, radeon_dynclks, int, 0444); 217 218 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 219 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 220 221 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 222 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 223 224 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 225 module_param_named(agpmode, radeon_agpmode, int, 0444); 226 227 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 228 module_param_named(gartsize, radeon_gart_size, int, 0600); 229 230 MODULE_PARM_DESC(benchmark, "Run benchmark"); 231 module_param_named(benchmark, radeon_benchmarking, int, 0444); 232 233 MODULE_PARM_DESC(test, "Run tests"); 234 module_param_named(test, radeon_testing, int, 0444); 235 236 MODULE_PARM_DESC(connector_table, "Force connector table"); 237 module_param_named(connector_table, radeon_connector_table, int, 0444); 238 239 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 240 module_param_named(tv, radeon_tv, int, 0444); 241 242 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 243 module_param_named(audio, radeon_audio, int, 0444); 244 245 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 246 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 247 248 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 249 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 250 251 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 252 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 253 254 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 255 module_param_named(msi, radeon_msi, int, 0444); 256 257 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 258 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 259 260 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 261 module_param_named(fastfb, radeon_fastfb, int, 0444); 262 263 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 264 module_param_named(dpm, radeon_dpm, int, 0444); 265 266 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 267 module_param_named(aspm, radeon_aspm, int, 0444); 268 269 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 270 module_param_named(runpm, radeon_runtime_pm, int, 0444); 271 272 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 273 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 274 275 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 276 module_param_named(vm_size, radeon_vm_size, int, 0444); 277 278 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 279 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 280 281 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 282 module_param_named(deep_color, radeon_deep_color, int, 0444); 283 284 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 285 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 286 287 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 288 module_param_named(bapm, radeon_bapm, int, 0444); 289 290 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 291 module_param_named(backlight, radeon_backlight, int, 0444); 292 293 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 294 module_param_named(auxch, radeon_auxch, int, 0444); 295 296 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 297 module_param_named(mst, radeon_mst, int, 0444); 298 299 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 300 module_param_named(uvd, radeon_uvd, int, 0444); 301 302 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 303 module_param_named(vce, radeon_vce, int, 0444); 304 305 int radeon_si_support = 1; 306 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 307 module_param_named(si_support, radeon_si_support, int, 0444); 308 309 int radeon_cik_support = 1; 310 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 311 module_param_named(cik_support, radeon_cik_support, int, 0444); 312 313 static struct pci_device_id pciidlist[] = { 314 radeon_PCI_IDS 315 }; 316 317 MODULE_DEVICE_TABLE(pci, pciidlist); 318 319 static struct drm_driver kms_driver; 320 321 bool radeon_device_is_virtual(void); 322 323 static int radeon_pci_probe(struct pci_dev *pdev, 324 const struct pci_device_id *ent) 325 { 326 unsigned long flags = 0; 327 int ret; 328 329 if (!ent) 330 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 331 332 flags = ent->driver_data; 333 334 if (!radeon_si_support) { 335 switch (flags & RADEON_FAMILY_MASK) { 336 case CHIP_TAHITI: 337 case CHIP_PITCAIRN: 338 case CHIP_VERDE: 339 case CHIP_OLAND: 340 case CHIP_HAINAN: 341 dev_info(&pdev->dev, 342 "SI support disabled by module param\n"); 343 return -ENODEV; 344 } 345 } 346 if (!radeon_cik_support) { 347 switch (flags & RADEON_FAMILY_MASK) { 348 case CHIP_KAVERI: 349 case CHIP_BONAIRE: 350 case CHIP_HAWAII: 351 case CHIP_KABINI: 352 case CHIP_MULLINS: 353 dev_info(&pdev->dev, 354 "CIK support disabled by module param\n"); 355 return -ENODEV; 356 } 357 } 358 359 if (vga_switcheroo_client_probe_defer(pdev)) 360 return -EPROBE_DEFER; 361 362 /* Get rid of things like offb */ 363 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "radeondrmfb"); 364 if (ret) 365 return ret; 366 367 return drm_get_pci_dev(pdev, ent, &kms_driver); 368 } 369 370 static void 371 radeon_pci_remove(struct pci_dev *pdev) 372 { 373 struct drm_device *dev = pci_get_drvdata(pdev); 374 375 drm_put_dev(dev); 376 } 377 378 static void 379 radeon_pci_shutdown(struct pci_dev *pdev) 380 { 381 /* if we are running in a VM, make sure the device 382 * torn down properly on reboot/shutdown 383 */ 384 if (radeon_device_is_virtual()) 385 radeon_pci_remove(pdev); 386 } 387 388 static int radeon_pmops_suspend(struct device *dev) 389 { 390 struct drm_device *drm_dev = dev_get_drvdata(dev); 391 return radeon_suspend_kms(drm_dev, true, true, false); 392 } 393 394 static int radeon_pmops_resume(struct device *dev) 395 { 396 struct drm_device *drm_dev = dev_get_drvdata(dev); 397 398 /* GPU comes up enabled by the bios on resume */ 399 if (radeon_is_px(drm_dev)) { 400 pm_runtime_disable(dev); 401 pm_runtime_set_active(dev); 402 pm_runtime_enable(dev); 403 } 404 405 return radeon_resume_kms(drm_dev, true, true); 406 } 407 408 static int radeon_pmops_freeze(struct device *dev) 409 { 410 struct drm_device *drm_dev = dev_get_drvdata(dev); 411 return radeon_suspend_kms(drm_dev, false, true, true); 412 } 413 414 static int radeon_pmops_thaw(struct device *dev) 415 { 416 struct drm_device *drm_dev = dev_get_drvdata(dev); 417 return radeon_resume_kms(drm_dev, false, true); 418 } 419 420 static int radeon_pmops_runtime_suspend(struct device *dev) 421 { 422 struct pci_dev *pdev = to_pci_dev(dev); 423 struct drm_device *drm_dev = pci_get_drvdata(pdev); 424 int ret; 425 426 if (!radeon_is_px(drm_dev)) { 427 pm_runtime_forbid(dev); 428 return -EBUSY; 429 } 430 431 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 432 drm_kms_helper_poll_disable(drm_dev); 433 434 ret = radeon_suspend_kms(drm_dev, false, false, false); 435 pci_save_state(pdev); 436 pci_disable_device(pdev); 437 pci_ignore_hotplug(pdev); 438 if (radeon_is_atpx_hybrid()) 439 pci_set_power_state(pdev, PCI_D3cold); 440 else if (!radeon_has_atpx_dgpu_power_cntl()) 441 pci_set_power_state(pdev, PCI_D3hot); 442 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 443 444 return 0; 445 } 446 447 static int radeon_pmops_runtime_resume(struct device *dev) 448 { 449 struct pci_dev *pdev = to_pci_dev(dev); 450 struct drm_device *drm_dev = pci_get_drvdata(pdev); 451 int ret; 452 453 if (!radeon_is_px(drm_dev)) 454 return -EINVAL; 455 456 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 457 458 if (radeon_is_atpx_hybrid() || 459 !radeon_has_atpx_dgpu_power_cntl()) 460 pci_set_power_state(pdev, PCI_D0); 461 pci_restore_state(pdev); 462 ret = pci_enable_device(pdev); 463 if (ret) 464 return ret; 465 pci_set_master(pdev); 466 467 ret = radeon_resume_kms(drm_dev, false, false); 468 drm_kms_helper_poll_enable(drm_dev); 469 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 470 return 0; 471 } 472 473 static int radeon_pmops_runtime_idle(struct device *dev) 474 { 475 struct drm_device *drm_dev = dev_get_drvdata(dev); 476 struct drm_crtc *crtc; 477 478 if (!radeon_is_px(drm_dev)) { 479 pm_runtime_forbid(dev); 480 return -EBUSY; 481 } 482 483 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 484 if (crtc->enabled) { 485 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 486 return -EBUSY; 487 } 488 } 489 490 pm_runtime_mark_last_busy(dev); 491 pm_runtime_autosuspend(dev); 492 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 493 return 1; 494 } 495 496 long radeon_drm_ioctl(struct file *filp, 497 unsigned int cmd, unsigned long arg) 498 { 499 struct drm_file *file_priv = filp->private_data; 500 struct drm_device *dev; 501 long ret; 502 dev = file_priv->minor->dev; 503 ret = pm_runtime_get_sync(dev->dev); 504 if (ret < 0) 505 return ret; 506 507 ret = drm_ioctl(filp, cmd, arg); 508 509 pm_runtime_mark_last_busy(dev->dev); 510 pm_runtime_put_autosuspend(dev->dev); 511 return ret; 512 } 513 514 #ifdef CONFIG_COMPAT 515 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 516 { 517 unsigned int nr = DRM_IOCTL_NR(cmd); 518 int ret; 519 520 if (nr < DRM_COMMAND_BASE) 521 return drm_compat_ioctl(filp, cmd, arg); 522 523 ret = radeon_drm_ioctl(filp, cmd, arg); 524 525 return ret; 526 } 527 #endif 528 529 static const struct dev_pm_ops radeon_pm_ops = { 530 .suspend = radeon_pmops_suspend, 531 .resume = radeon_pmops_resume, 532 .freeze = radeon_pmops_freeze, 533 .thaw = radeon_pmops_thaw, 534 .poweroff = radeon_pmops_freeze, 535 .restore = radeon_pmops_resume, 536 .runtime_suspend = radeon_pmops_runtime_suspend, 537 .runtime_resume = radeon_pmops_runtime_resume, 538 .runtime_idle = radeon_pmops_runtime_idle, 539 }; 540 541 static const struct file_operations radeon_driver_kms_fops = { 542 .owner = THIS_MODULE, 543 .open = drm_open, 544 .release = drm_release, 545 .unlocked_ioctl = radeon_drm_ioctl, 546 .mmap = radeon_mmap, 547 .poll = drm_poll, 548 .read = drm_read, 549 #ifdef CONFIG_COMPAT 550 .compat_ioctl = radeon_kms_compat_ioctl, 551 #endif 552 }; 553 554 static bool 555 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 556 bool in_vblank_irq, int *vpos, int *hpos, 557 ktime_t *stime, ktime_t *etime, 558 const struct drm_display_mode *mode) 559 { 560 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 561 stime, etime, mode); 562 } 563 564 static struct drm_driver kms_driver = { 565 .driver_features = 566 DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER, 567 .load = radeon_driver_load_kms, 568 .open = radeon_driver_open_kms, 569 .postclose = radeon_driver_postclose_kms, 570 .lastclose = radeon_driver_lastclose_kms, 571 .unload = radeon_driver_unload_kms, 572 .get_vblank_counter = radeon_get_vblank_counter_kms, 573 .enable_vblank = radeon_enable_vblank_kms, 574 .disable_vblank = radeon_disable_vblank_kms, 575 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 576 .get_scanout_position = radeon_get_crtc_scanout_position, 577 .irq_preinstall = radeon_driver_irq_preinstall_kms, 578 .irq_postinstall = radeon_driver_irq_postinstall_kms, 579 .irq_uninstall = radeon_driver_irq_uninstall_kms, 580 .irq_handler = radeon_driver_irq_handler_kms, 581 .ioctls = radeon_ioctls_kms, 582 .gem_free_object_unlocked = radeon_gem_object_free, 583 .gem_open_object = radeon_gem_object_open, 584 .gem_close_object = radeon_gem_object_close, 585 .dumb_create = radeon_mode_dumb_create, 586 .dumb_map_offset = radeon_mode_dumb_mmap, 587 .fops = &radeon_driver_kms_fops, 588 589 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 590 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 591 .gem_prime_export = radeon_gem_prime_export, 592 .gem_prime_pin = radeon_gem_prime_pin, 593 .gem_prime_unpin = radeon_gem_prime_unpin, 594 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 595 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 596 .gem_prime_vmap = radeon_gem_prime_vmap, 597 .gem_prime_vunmap = radeon_gem_prime_vunmap, 598 599 .name = DRIVER_NAME, 600 .desc = DRIVER_DESC, 601 .date = DRIVER_DATE, 602 .major = KMS_DRIVER_MAJOR, 603 .minor = KMS_DRIVER_MINOR, 604 .patchlevel = KMS_DRIVER_PATCHLEVEL, 605 }; 606 607 static struct drm_driver *driver; 608 static struct pci_driver *pdriver; 609 610 static struct pci_driver radeon_kms_pci_driver = { 611 .name = DRIVER_NAME, 612 .id_table = pciidlist, 613 .probe = radeon_pci_probe, 614 .remove = radeon_pci_remove, 615 .shutdown = radeon_pci_shutdown, 616 .driver.pm = &radeon_pm_ops, 617 }; 618 619 static int __init radeon_init(void) 620 { 621 if (vgacon_text_force() && radeon_modeset == -1) { 622 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 623 radeon_modeset = 0; 624 } 625 /* set to modesetting by default if not nomodeset */ 626 if (radeon_modeset == -1) 627 radeon_modeset = 1; 628 629 if (radeon_modeset == 1) { 630 DRM_INFO("radeon kernel modesetting enabled.\n"); 631 driver = &kms_driver; 632 pdriver = &radeon_kms_pci_driver; 633 driver->driver_features |= DRIVER_MODESET; 634 driver->num_ioctls = radeon_max_kms_ioctl; 635 radeon_register_atpx_handler(); 636 637 } else { 638 DRM_ERROR("No UMS support in radeon module!\n"); 639 return -EINVAL; 640 } 641 642 return pci_register_driver(pdriver); 643 } 644 645 static void __exit radeon_exit(void) 646 { 647 pci_unregister_driver(pdriver); 648 radeon_unregister_atpx_handler(); 649 } 650 651 module_init(radeon_init); 652 module_exit(radeon_exit); 653 654 MODULE_AUTHOR(DRIVER_AUTHOR); 655 MODULE_DESCRIPTION(DRIVER_DESC); 656 MODULE_LICENSE("GPL and additional rights"); 657