1 /**
2  * \file radeon_drv.c
3  * ATI Radeon driver
4  *
5  * \author Gareth Hughes <gareth@valinux.com>
6  */
7 
8 /*
9  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice (including the next
20  * paragraph) shall be included in all copies or substantial portions of the
21  * Software.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
26  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29  * OTHER DEALINGS IN THE SOFTWARE.
30  */
31 
32 #include <drm/drmP.h>
33 #include <drm/radeon_drm.h>
34 #include "radeon_drv.h"
35 
36 #include <drm/drm_pciids.h>
37 #include <linux/apple-gmux.h>
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vgaarb.h>
42 #include <linux/vga_switcheroo.h>
43 #include <drm/drm_gem.h>
44 
45 #include "drm_crtc_helper.h"
46 #include "radeon_kfd.h"
47 
48 /*
49  * KMS wrapper.
50  * - 2.0.0 - initial interface
51  * - 2.1.0 - add square tiling interface
52  * - 2.2.0 - add r6xx/r7xx const buffer support
53  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
54  * - 2.4.0 - add crtc id query
55  * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
56  * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
57  *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58  *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
59  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
60  *   2.10.0 - fusion 2D tiling
61  *   2.11.0 - backend map, initial compute support for the CS checker
62  *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
63  *   2.13.0 - virtual memory support, streamout
64  *   2.14.0 - add evergreen tiling informations
65  *   2.15.0 - add max_pipes query
66  *   2.16.0 - fix evergreen 2D tiled surface calculation
67  *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
68  *   2.18.0 - r600-eg: allow "invalid" DB formats
69  *   2.19.0 - r600-eg: MSAA textures
70  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
71  *   2.21.0 - r600-r700: FMASK and CMASK
72  *   2.22.0 - r600 only: RESOLVE_BOX allowed
73  *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
74  *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
75  *   2.25.0 - eg+: new info request for num SE and num SH
76  *   2.26.0 - r600-eg: fix htile size computation
77  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
78  *   2.28.0 - r600-eg: Add MEM_WRITE packet support
79  *   2.29.0 - R500 FP16 color clear registers
80  *   2.30.0 - fix for FMASK texturing
81  *   2.31.0 - Add fastfb support for rs690
82  *   2.32.0 - new info request for rings working
83  *   2.33.0 - Add SI tiling mode array query
84  *   2.34.0 - Add CIK tiling mode array query
85  *   2.35.0 - Add CIK macrotile mode array query
86  *   2.36.0 - Fix CIK DCE tiling setup
87  *   2.37.0 - allow GS ring setup on r6xx/r7xx
88  *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
89  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
90  *   2.39.0 - Add INFO query for number of active CUs
91  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
92  *            CS to GPU on >= r600
93  *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
94  *   2.42.0 - Add VCE/VUI (Video Usability Information) support
95  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
96  *   2.44.0 - SET_APPEND_CNT packet3 support
97  *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
98  */
99 #define KMS_DRIVER_MAJOR	2
100 #define KMS_DRIVER_MINOR	45
101 #define KMS_DRIVER_PATCHLEVEL	0
102 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
103 int radeon_driver_unload_kms(struct drm_device *dev);
104 void radeon_driver_lastclose_kms(struct drm_device *dev);
105 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
106 void radeon_driver_postclose_kms(struct drm_device *dev,
107 				 struct drm_file *file_priv);
108 void radeon_driver_preclose_kms(struct drm_device *dev,
109 				struct drm_file *file_priv);
110 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
111 		       bool fbcon, bool freeze);
112 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
113 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
114 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
115 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
116 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
117 				    int *max_error,
118 				    struct timeval *vblank_time,
119 				    unsigned flags);
120 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
121 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
122 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
123 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
124 void radeon_gem_object_free(struct drm_gem_object *obj);
125 int radeon_gem_object_open(struct drm_gem_object *obj,
126 				struct drm_file *file_priv);
127 void radeon_gem_object_close(struct drm_gem_object *obj,
128 				struct drm_file *file_priv);
129 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
130 					struct drm_gem_object *gobj,
131 					int flags);
132 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
133 				      unsigned int flags, int *vpos, int *hpos,
134 				      ktime_t *stime, ktime_t *etime,
135 				      const struct drm_display_mode *mode);
136 extern bool radeon_is_px(struct drm_device *dev);
137 extern const struct drm_ioctl_desc radeon_ioctls_kms[];
138 extern int radeon_max_kms_ioctl;
139 int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
140 int radeon_mode_dumb_mmap(struct drm_file *filp,
141 			  struct drm_device *dev,
142 			  uint32_t handle, uint64_t *offset_p);
143 int radeon_mode_dumb_create(struct drm_file *file_priv,
144 			    struct drm_device *dev,
145 			    struct drm_mode_create_dumb *args);
146 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
147 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
148 							struct dma_buf_attachment *,
149 							struct sg_table *sg);
150 int radeon_gem_prime_pin(struct drm_gem_object *obj);
151 void radeon_gem_prime_unpin(struct drm_gem_object *obj);
152 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
153 void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
154 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
155 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
156 				    unsigned long arg);
157 
158 #if defined(CONFIG_DEBUG_FS)
159 int radeon_debugfs_init(struct drm_minor *minor);
160 void radeon_debugfs_cleanup(struct drm_minor *minor);
161 #endif
162 
163 /* atpx handler */
164 #if defined(CONFIG_VGA_SWITCHEROO)
165 void radeon_register_atpx_handler(void);
166 void radeon_unregister_atpx_handler(void);
167 #else
168 static inline void radeon_register_atpx_handler(void) {}
169 static inline void radeon_unregister_atpx_handler(void) {}
170 #endif
171 
172 int radeon_no_wb;
173 int radeon_modeset = -1;
174 int radeon_dynclks = -1;
175 int radeon_r4xx_atom = 0;
176 int radeon_agpmode = 0;
177 int radeon_vram_limit = 0;
178 int radeon_gart_size = -1; /* auto */
179 int radeon_benchmarking = 0;
180 int radeon_testing = 0;
181 int radeon_connector_table = 0;
182 int radeon_tv = 1;
183 int radeon_audio = -1;
184 int radeon_disp_priority = 0;
185 int radeon_hw_i2c = 0;
186 int radeon_pcie_gen2 = -1;
187 int radeon_msi = -1;
188 int radeon_lockup_timeout = 10000;
189 int radeon_fastfb = 0;
190 int radeon_dpm = -1;
191 int radeon_aspm = -1;
192 int radeon_runtime_pm = -1;
193 int radeon_hard_reset = 0;
194 int radeon_vm_size = 8;
195 int radeon_vm_block_size = -1;
196 int radeon_deep_color = 0;
197 int radeon_use_pflipirq = 2;
198 int radeon_bapm = -1;
199 int radeon_backlight = -1;
200 int radeon_auxch = -1;
201 int radeon_mst = 0;
202 int radeon_uvd = 1;
203 int radeon_vce = 1;
204 
205 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
206 module_param_named(no_wb, radeon_no_wb, int, 0444);
207 
208 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
209 module_param_named(modeset, radeon_modeset, int, 0400);
210 
211 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
212 module_param_named(dynclks, radeon_dynclks, int, 0444);
213 
214 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
215 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
216 
217 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
218 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
219 
220 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
221 module_param_named(agpmode, radeon_agpmode, int, 0444);
222 
223 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
224 module_param_named(gartsize, radeon_gart_size, int, 0600);
225 
226 MODULE_PARM_DESC(benchmark, "Run benchmark");
227 module_param_named(benchmark, radeon_benchmarking, int, 0444);
228 
229 MODULE_PARM_DESC(test, "Run tests");
230 module_param_named(test, radeon_testing, int, 0444);
231 
232 MODULE_PARM_DESC(connector_table, "Force connector table");
233 module_param_named(connector_table, radeon_connector_table, int, 0444);
234 
235 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
236 module_param_named(tv, radeon_tv, int, 0444);
237 
238 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
239 module_param_named(audio, radeon_audio, int, 0444);
240 
241 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
242 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
243 
244 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
245 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
246 
247 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
248 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
249 
250 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
251 module_param_named(msi, radeon_msi, int, 0444);
252 
253 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
254 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
255 
256 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
257 module_param_named(fastfb, radeon_fastfb, int, 0444);
258 
259 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
260 module_param_named(dpm, radeon_dpm, int, 0444);
261 
262 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
263 module_param_named(aspm, radeon_aspm, int, 0444);
264 
265 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
266 module_param_named(runpm, radeon_runtime_pm, int, 0444);
267 
268 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
269 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
270 
271 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
272 module_param_named(vm_size, radeon_vm_size, int, 0444);
273 
274 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
275 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
276 
277 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
278 module_param_named(deep_color, radeon_deep_color, int, 0444);
279 
280 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
281 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
282 
283 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
284 module_param_named(bapm, radeon_bapm, int, 0444);
285 
286 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
287 module_param_named(backlight, radeon_backlight, int, 0444);
288 
289 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
290 module_param_named(auxch, radeon_auxch, int, 0444);
291 
292 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
293 module_param_named(mst, radeon_mst, int, 0444);
294 
295 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
296 module_param_named(uvd, radeon_uvd, int, 0444);
297 
298 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
299 module_param_named(vce, radeon_vce, int, 0444);
300 
301 static struct pci_device_id pciidlist[] = {
302 	radeon_PCI_IDS
303 };
304 
305 MODULE_DEVICE_TABLE(pci, pciidlist);
306 
307 static struct drm_driver kms_driver;
308 
309 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
310 {
311 	struct apertures_struct *ap;
312 	bool primary = false;
313 
314 	ap = alloc_apertures(1);
315 	if (!ap)
316 		return -ENOMEM;
317 
318 	ap->ranges[0].base = pci_resource_start(pdev, 0);
319 	ap->ranges[0].size = pci_resource_len(pdev, 0);
320 
321 #ifdef CONFIG_X86
322 	primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
323 #endif
324 	remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
325 	kfree(ap);
326 
327 	return 0;
328 }
329 
330 static int radeon_pci_probe(struct pci_dev *pdev,
331 			    const struct pci_device_id *ent)
332 {
333 	int ret;
334 
335 	/*
336 	 * Initialize amdkfd before starting radeon. If it was not loaded yet,
337 	 * defer radeon probing
338 	 */
339 	ret = radeon_kfd_init();
340 	if (ret == -EPROBE_DEFER)
341 		return ret;
342 
343 	/*
344 	 * apple-gmux is needed on dual GPU MacBook Pro
345 	 * to probe the panel if we're the inactive GPU.
346 	 */
347 	if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
348 	    apple_gmux_present() && pdev != vga_default_device() &&
349 	    !vga_switcheroo_handler_flags())
350 		return -EPROBE_DEFER;
351 
352 	/* Get rid of things like offb */
353 	ret = radeon_kick_out_firmware_fb(pdev);
354 	if (ret)
355 		return ret;
356 
357 	return drm_get_pci_dev(pdev, ent, &kms_driver);
358 }
359 
360 static void
361 radeon_pci_remove(struct pci_dev *pdev)
362 {
363 	struct drm_device *dev = pci_get_drvdata(pdev);
364 
365 	drm_put_dev(dev);
366 }
367 
368 static int radeon_pmops_suspend(struct device *dev)
369 {
370 	struct pci_dev *pdev = to_pci_dev(dev);
371 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
372 	return radeon_suspend_kms(drm_dev, true, true, false);
373 }
374 
375 static int radeon_pmops_resume(struct device *dev)
376 {
377 	struct pci_dev *pdev = to_pci_dev(dev);
378 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
379 	return radeon_resume_kms(drm_dev, true, true);
380 }
381 
382 static int radeon_pmops_freeze(struct device *dev)
383 {
384 	struct pci_dev *pdev = to_pci_dev(dev);
385 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
386 	return radeon_suspend_kms(drm_dev, false, true, true);
387 }
388 
389 static int radeon_pmops_thaw(struct device *dev)
390 {
391 	struct pci_dev *pdev = to_pci_dev(dev);
392 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
393 	return radeon_resume_kms(drm_dev, false, true);
394 }
395 
396 static int radeon_pmops_runtime_suspend(struct device *dev)
397 {
398 	struct pci_dev *pdev = to_pci_dev(dev);
399 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
400 	int ret;
401 
402 	if (!radeon_is_px(drm_dev)) {
403 		pm_runtime_forbid(dev);
404 		return -EBUSY;
405 	}
406 
407 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
408 	drm_kms_helper_poll_disable(drm_dev);
409 	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
410 
411 	ret = radeon_suspend_kms(drm_dev, false, false, false);
412 	pci_save_state(pdev);
413 	pci_disable_device(pdev);
414 	pci_ignore_hotplug(pdev);
415 	pci_set_power_state(pdev, PCI_D3cold);
416 	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
417 
418 	return 0;
419 }
420 
421 static int radeon_pmops_runtime_resume(struct device *dev)
422 {
423 	struct pci_dev *pdev = to_pci_dev(dev);
424 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
425 	int ret;
426 
427 	if (!radeon_is_px(drm_dev))
428 		return -EINVAL;
429 
430 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
431 
432 	pci_set_power_state(pdev, PCI_D0);
433 	pci_restore_state(pdev);
434 	ret = pci_enable_device(pdev);
435 	if (ret)
436 		return ret;
437 	pci_set_master(pdev);
438 
439 	ret = radeon_resume_kms(drm_dev, false, false);
440 	drm_kms_helper_poll_enable(drm_dev);
441 	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
442 	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
443 	return 0;
444 }
445 
446 static int radeon_pmops_runtime_idle(struct device *dev)
447 {
448 	struct pci_dev *pdev = to_pci_dev(dev);
449 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
450 	struct drm_crtc *crtc;
451 
452 	if (!radeon_is_px(drm_dev)) {
453 		pm_runtime_forbid(dev);
454 		return -EBUSY;
455 	}
456 
457 	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
458 		if (crtc->enabled) {
459 			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
460 			return -EBUSY;
461 		}
462 	}
463 
464 	pm_runtime_mark_last_busy(dev);
465 	pm_runtime_autosuspend(dev);
466 	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
467 	return 1;
468 }
469 
470 long radeon_drm_ioctl(struct file *filp,
471 		      unsigned int cmd, unsigned long arg)
472 {
473 	struct drm_file *file_priv = filp->private_data;
474 	struct drm_device *dev;
475 	long ret;
476 	dev = file_priv->minor->dev;
477 	ret = pm_runtime_get_sync(dev->dev);
478 	if (ret < 0)
479 		return ret;
480 
481 	ret = drm_ioctl(filp, cmd, arg);
482 
483 	pm_runtime_mark_last_busy(dev->dev);
484 	pm_runtime_put_autosuspend(dev->dev);
485 	return ret;
486 }
487 
488 static const struct dev_pm_ops radeon_pm_ops = {
489 	.suspend = radeon_pmops_suspend,
490 	.resume = radeon_pmops_resume,
491 	.freeze = radeon_pmops_freeze,
492 	.thaw = radeon_pmops_thaw,
493 	.poweroff = radeon_pmops_freeze,
494 	.restore = radeon_pmops_resume,
495 	.runtime_suspend = radeon_pmops_runtime_suspend,
496 	.runtime_resume = radeon_pmops_runtime_resume,
497 	.runtime_idle = radeon_pmops_runtime_idle,
498 };
499 
500 static const struct file_operations radeon_driver_kms_fops = {
501 	.owner = THIS_MODULE,
502 	.open = drm_open,
503 	.release = drm_release,
504 	.unlocked_ioctl = radeon_drm_ioctl,
505 	.mmap = radeon_mmap,
506 	.poll = drm_poll,
507 	.read = drm_read,
508 #ifdef CONFIG_COMPAT
509 	.compat_ioctl = radeon_kms_compat_ioctl,
510 #endif
511 };
512 
513 static struct drm_driver kms_driver = {
514 	.driver_features =
515 	    DRIVER_USE_AGP |
516 	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
517 	    DRIVER_PRIME | DRIVER_RENDER,
518 	.load = radeon_driver_load_kms,
519 	.open = radeon_driver_open_kms,
520 	.preclose = radeon_driver_preclose_kms,
521 	.postclose = radeon_driver_postclose_kms,
522 	.lastclose = radeon_driver_lastclose_kms,
523 	.set_busid = drm_pci_set_busid,
524 	.unload = radeon_driver_unload_kms,
525 	.get_vblank_counter = radeon_get_vblank_counter_kms,
526 	.enable_vblank = radeon_enable_vblank_kms,
527 	.disable_vblank = radeon_disable_vblank_kms,
528 	.get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
529 	.get_scanout_position = radeon_get_crtc_scanoutpos,
530 #if defined(CONFIG_DEBUG_FS)
531 	.debugfs_init = radeon_debugfs_init,
532 	.debugfs_cleanup = radeon_debugfs_cleanup,
533 #endif
534 	.irq_preinstall = radeon_driver_irq_preinstall_kms,
535 	.irq_postinstall = radeon_driver_irq_postinstall_kms,
536 	.irq_uninstall = radeon_driver_irq_uninstall_kms,
537 	.irq_handler = radeon_driver_irq_handler_kms,
538 	.ioctls = radeon_ioctls_kms,
539 	.gem_free_object_unlocked = radeon_gem_object_free,
540 	.gem_open_object = radeon_gem_object_open,
541 	.gem_close_object = radeon_gem_object_close,
542 	.dumb_create = radeon_mode_dumb_create,
543 	.dumb_map_offset = radeon_mode_dumb_mmap,
544 	.dumb_destroy = drm_gem_dumb_destroy,
545 	.fops = &radeon_driver_kms_fops,
546 
547 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
548 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
549 	.gem_prime_export = radeon_gem_prime_export,
550 	.gem_prime_import = drm_gem_prime_import,
551 	.gem_prime_pin = radeon_gem_prime_pin,
552 	.gem_prime_unpin = radeon_gem_prime_unpin,
553 	.gem_prime_res_obj = radeon_gem_prime_res_obj,
554 	.gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
555 	.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
556 	.gem_prime_vmap = radeon_gem_prime_vmap,
557 	.gem_prime_vunmap = radeon_gem_prime_vunmap,
558 
559 	.name = DRIVER_NAME,
560 	.desc = DRIVER_DESC,
561 	.date = DRIVER_DATE,
562 	.major = KMS_DRIVER_MAJOR,
563 	.minor = KMS_DRIVER_MINOR,
564 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
565 };
566 
567 static struct drm_driver *driver;
568 static struct pci_driver *pdriver;
569 
570 static struct pci_driver radeon_kms_pci_driver = {
571 	.name = DRIVER_NAME,
572 	.id_table = pciidlist,
573 	.probe = radeon_pci_probe,
574 	.remove = radeon_pci_remove,
575 	.driver.pm = &radeon_pm_ops,
576 };
577 
578 static int __init radeon_init(void)
579 {
580 	if (vgacon_text_force() && radeon_modeset == -1) {
581 		DRM_INFO("VGACON disable radeon kernel modesetting.\n");
582 		radeon_modeset = 0;
583 	}
584 	/* set to modesetting by default if not nomodeset */
585 	if (radeon_modeset == -1)
586 		radeon_modeset = 1;
587 
588 	if (radeon_modeset == 1) {
589 		DRM_INFO("radeon kernel modesetting enabled.\n");
590 		driver = &kms_driver;
591 		pdriver = &radeon_kms_pci_driver;
592 		driver->driver_features |= DRIVER_MODESET;
593 		driver->num_ioctls = radeon_max_kms_ioctl;
594 		radeon_register_atpx_handler();
595 
596 	} else {
597 		DRM_ERROR("No UMS support in radeon module!\n");
598 		return -EINVAL;
599 	}
600 
601 	/* let modprobe override vga console setting */
602 	return drm_pci_init(driver, pdriver);
603 }
604 
605 static void __exit radeon_exit(void)
606 {
607 	radeon_kfd_fini();
608 	drm_pci_exit(driver, pdriver);
609 	radeon_unregister_atpx_handler();
610 }
611 
612 module_init(radeon_init);
613 module_exit(radeon_exit);
614 
615 MODULE_AUTHOR(DRIVER_AUTHOR);
616 MODULE_DESCRIPTION(DRIVER_DESC);
617 MODULE_LICENSE("GPL and additional rights");
618