1 /* 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pci.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_fb_helper.h> 45 #include <drm/drm_file.h> 46 #include <drm/drm_gem.h> 47 #include <drm/drm_ioctl.h> 48 #include <drm/drm_pciids.h> 49 #include <drm/drm_probe_helper.h> 50 #include <drm/drm_vblank.h> 51 #include <drm/radeon_drm.h> 52 53 #include "radeon_drv.h" 54 #include "radeon_kms.h" 55 #include "radeon_ttm.h" 56 #include "radeon_device.h" 57 #include "radeon_prime.h" 58 59 /* 60 * KMS wrapper. 61 * - 2.0.0 - initial interface 62 * - 2.1.0 - add square tiling interface 63 * - 2.2.0 - add r6xx/r7xx const buffer support 64 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 65 * - 2.4.0 - add crtc id query 66 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 67 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 68 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 69 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 70 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 71 * 2.10.0 - fusion 2D tiling 72 * 2.11.0 - backend map, initial compute support for the CS checker 73 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 74 * 2.13.0 - virtual memory support, streamout 75 * 2.14.0 - add evergreen tiling informations 76 * 2.15.0 - add max_pipes query 77 * 2.16.0 - fix evergreen 2D tiled surface calculation 78 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 79 * 2.18.0 - r600-eg: allow "invalid" DB formats 80 * 2.19.0 - r600-eg: MSAA textures 81 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 82 * 2.21.0 - r600-r700: FMASK and CMASK 83 * 2.22.0 - r600 only: RESOLVE_BOX allowed 84 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 85 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 86 * 2.25.0 - eg+: new info request for num SE and num SH 87 * 2.26.0 - r600-eg: fix htile size computation 88 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 89 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 90 * 2.29.0 - R500 FP16 color clear registers 91 * 2.30.0 - fix for FMASK texturing 92 * 2.31.0 - Add fastfb support for rs690 93 * 2.32.0 - new info request for rings working 94 * 2.33.0 - Add SI tiling mode array query 95 * 2.34.0 - Add CIK tiling mode array query 96 * 2.35.0 - Add CIK macrotile mode array query 97 * 2.36.0 - Fix CIK DCE tiling setup 98 * 2.37.0 - allow GS ring setup on r6xx/r7xx 99 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 100 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 101 * 2.39.0 - Add INFO query for number of active CUs 102 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 103 * CS to GPU on >= r600 104 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 105 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 106 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 107 * 2.44.0 - SET_APPEND_CNT packet3 support 108 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 109 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 110 * 2.47.0 - Add UVD_NO_OP register support 111 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 112 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 113 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 114 */ 115 #define KMS_DRIVER_MAJOR 2 116 #define KMS_DRIVER_MINOR 50 117 #define KMS_DRIVER_PATCHLEVEL 0 118 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 119 bool fbcon, bool freeze); 120 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 121 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 122 unsigned int flags, int *vpos, int *hpos, 123 ktime_t *stime, ktime_t *etime, 124 const struct drm_display_mode *mode); 125 extern bool radeon_is_px(struct drm_device *dev); 126 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 127 extern int radeon_max_kms_ioctl; 128 int radeon_mode_dumb_mmap(struct drm_file *filp, 129 struct drm_device *dev, 130 uint32_t handle, uint64_t *offset_p); 131 int radeon_mode_dumb_create(struct drm_file *file_priv, 132 struct drm_device *dev, 133 struct drm_mode_create_dumb *args); 134 135 /* atpx handler */ 136 #if defined(CONFIG_VGA_SWITCHEROO) 137 void radeon_register_atpx_handler(void); 138 void radeon_unregister_atpx_handler(void); 139 bool radeon_has_atpx_dgpu_power_cntl(void); 140 bool radeon_is_atpx_hybrid(void); 141 #else 142 static inline void radeon_register_atpx_handler(void) {} 143 static inline void radeon_unregister_atpx_handler(void) {} 144 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 145 static inline bool radeon_is_atpx_hybrid(void) { return false; } 146 #endif 147 148 int radeon_no_wb; 149 int radeon_modeset = -1; 150 int radeon_dynclks = -1; 151 int radeon_r4xx_atom = 0; 152 int radeon_agpmode = -1; 153 int radeon_vram_limit = 0; 154 int radeon_gart_size = -1; /* auto */ 155 int radeon_benchmarking = 0; 156 int radeon_testing = 0; 157 int radeon_connector_table = 0; 158 int radeon_tv = 1; 159 int radeon_audio = -1; 160 int radeon_disp_priority = 0; 161 int radeon_hw_i2c = 0; 162 int radeon_pcie_gen2 = -1; 163 int radeon_msi = -1; 164 int radeon_lockup_timeout = 10000; 165 int radeon_fastfb = 0; 166 int radeon_dpm = -1; 167 int radeon_aspm = -1; 168 int radeon_runtime_pm = -1; 169 int radeon_hard_reset = 0; 170 int radeon_vm_size = 8; 171 int radeon_vm_block_size = -1; 172 int radeon_deep_color = 0; 173 int radeon_use_pflipirq = 2; 174 int radeon_bapm = -1; 175 int radeon_backlight = -1; 176 int radeon_auxch = -1; 177 int radeon_mst = 0; 178 int radeon_uvd = 1; 179 int radeon_vce = 1; 180 181 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 182 module_param_named(no_wb, radeon_no_wb, int, 0444); 183 184 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 185 module_param_named(modeset, radeon_modeset, int, 0400); 186 187 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 188 module_param_named(dynclks, radeon_dynclks, int, 0444); 189 190 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 191 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 192 193 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 194 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 195 196 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 197 module_param_named(agpmode, radeon_agpmode, int, 0444); 198 199 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 200 module_param_named(gartsize, radeon_gart_size, int, 0600); 201 202 MODULE_PARM_DESC(benchmark, "Run benchmark"); 203 module_param_named(benchmark, radeon_benchmarking, int, 0444); 204 205 MODULE_PARM_DESC(test, "Run tests"); 206 module_param_named(test, radeon_testing, int, 0444); 207 208 MODULE_PARM_DESC(connector_table, "Force connector table"); 209 module_param_named(connector_table, radeon_connector_table, int, 0444); 210 211 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 212 module_param_named(tv, radeon_tv, int, 0444); 213 214 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 215 module_param_named(audio, radeon_audio, int, 0444); 216 217 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 218 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 219 220 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 221 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 222 223 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 224 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 225 226 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 227 module_param_named(msi, radeon_msi, int, 0444); 228 229 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 230 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 231 232 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 233 module_param_named(fastfb, radeon_fastfb, int, 0444); 234 235 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 236 module_param_named(dpm, radeon_dpm, int, 0444); 237 238 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 239 module_param_named(aspm, radeon_aspm, int, 0444); 240 241 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 242 module_param_named(runpm, radeon_runtime_pm, int, 0444); 243 244 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 245 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 246 247 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 248 module_param_named(vm_size, radeon_vm_size, int, 0444); 249 250 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 251 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 252 253 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 254 module_param_named(deep_color, radeon_deep_color, int, 0444); 255 256 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 257 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 258 259 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 260 module_param_named(bapm, radeon_bapm, int, 0444); 261 262 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 263 module_param_named(backlight, radeon_backlight, int, 0444); 264 265 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 266 module_param_named(auxch, radeon_auxch, int, 0444); 267 268 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 269 module_param_named(mst, radeon_mst, int, 0444); 270 271 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 272 module_param_named(uvd, radeon_uvd, int, 0444); 273 274 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 275 module_param_named(vce, radeon_vce, int, 0444); 276 277 int radeon_si_support = 1; 278 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 279 module_param_named(si_support, radeon_si_support, int, 0444); 280 281 int radeon_cik_support = 1; 282 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 283 module_param_named(cik_support, radeon_cik_support, int, 0444); 284 285 static struct pci_device_id pciidlist[] = { 286 radeon_PCI_IDS 287 }; 288 289 MODULE_DEVICE_TABLE(pci, pciidlist); 290 291 static struct drm_driver kms_driver; 292 293 static int radeon_pci_probe(struct pci_dev *pdev, 294 const struct pci_device_id *ent) 295 { 296 unsigned long flags = 0; 297 struct drm_device *dev; 298 int ret; 299 300 if (!ent) 301 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 302 303 flags = ent->driver_data; 304 305 if (!radeon_si_support) { 306 switch (flags & RADEON_FAMILY_MASK) { 307 case CHIP_TAHITI: 308 case CHIP_PITCAIRN: 309 case CHIP_VERDE: 310 case CHIP_OLAND: 311 case CHIP_HAINAN: 312 dev_info(&pdev->dev, 313 "SI support disabled by module param\n"); 314 return -ENODEV; 315 } 316 } 317 if (!radeon_cik_support) { 318 switch (flags & RADEON_FAMILY_MASK) { 319 case CHIP_KAVERI: 320 case CHIP_BONAIRE: 321 case CHIP_HAWAII: 322 case CHIP_KABINI: 323 case CHIP_MULLINS: 324 dev_info(&pdev->dev, 325 "CIK support disabled by module param\n"); 326 return -ENODEV; 327 } 328 } 329 330 if (vga_switcheroo_client_probe_defer(pdev)) 331 return -EPROBE_DEFER; 332 333 /* Get rid of things like offb */ 334 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 335 if (ret) 336 return ret; 337 338 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 339 if (IS_ERR(dev)) 340 return PTR_ERR(dev); 341 342 ret = pci_enable_device(pdev); 343 if (ret) 344 goto err_free; 345 346 dev->pdev = pdev; 347 #ifdef __alpha__ 348 dev->hose = pdev->sysdata; 349 #endif 350 351 pci_set_drvdata(pdev, dev); 352 353 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) 354 dev->agp = drm_agp_init(dev); 355 if (dev->agp) { 356 dev->agp->agp_mtrr = arch_phys_wc_add( 357 dev->agp->agp_info.aper_base, 358 dev->agp->agp_info.aper_size * 359 1024 * 1024); 360 } 361 362 ret = drm_dev_register(dev, ent->driver_data); 363 if (ret) 364 goto err_agp; 365 366 return 0; 367 368 err_agp: 369 if (dev->agp) 370 arch_phys_wc_del(dev->agp->agp_mtrr); 371 kfree(dev->agp); 372 pci_disable_device(pdev); 373 err_free: 374 drm_dev_put(dev); 375 return ret; 376 } 377 378 static void 379 radeon_pci_remove(struct pci_dev *pdev) 380 { 381 struct drm_device *dev = pci_get_drvdata(pdev); 382 383 drm_put_dev(dev); 384 } 385 386 static void 387 radeon_pci_shutdown(struct pci_dev *pdev) 388 { 389 /* if we are running in a VM, make sure the device 390 * torn down properly on reboot/shutdown 391 */ 392 if (radeon_device_is_virtual()) 393 radeon_pci_remove(pdev); 394 395 #ifdef CONFIG_PPC64 396 /* 397 * Some adapters need to be suspended before a 398 * shutdown occurs in order to prevent an error 399 * during kexec. 400 * Make this power specific becauase it breaks 401 * some non-power boards. 402 */ 403 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 404 #endif 405 } 406 407 static int radeon_pmops_suspend(struct device *dev) 408 { 409 struct drm_device *drm_dev = dev_get_drvdata(dev); 410 return radeon_suspend_kms(drm_dev, true, true, false); 411 } 412 413 static int radeon_pmops_resume(struct device *dev) 414 { 415 struct drm_device *drm_dev = dev_get_drvdata(dev); 416 417 /* GPU comes up enabled by the bios on resume */ 418 if (radeon_is_px(drm_dev)) { 419 pm_runtime_disable(dev); 420 pm_runtime_set_active(dev); 421 pm_runtime_enable(dev); 422 } 423 424 return radeon_resume_kms(drm_dev, true, true); 425 } 426 427 static int radeon_pmops_freeze(struct device *dev) 428 { 429 struct drm_device *drm_dev = dev_get_drvdata(dev); 430 return radeon_suspend_kms(drm_dev, false, true, true); 431 } 432 433 static int radeon_pmops_thaw(struct device *dev) 434 { 435 struct drm_device *drm_dev = dev_get_drvdata(dev); 436 return radeon_resume_kms(drm_dev, false, true); 437 } 438 439 static int radeon_pmops_runtime_suspend(struct device *dev) 440 { 441 struct pci_dev *pdev = to_pci_dev(dev); 442 struct drm_device *drm_dev = pci_get_drvdata(pdev); 443 444 if (!radeon_is_px(drm_dev)) { 445 pm_runtime_forbid(dev); 446 return -EBUSY; 447 } 448 449 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 450 drm_kms_helper_poll_disable(drm_dev); 451 452 radeon_suspend_kms(drm_dev, false, false, false); 453 pci_save_state(pdev); 454 pci_disable_device(pdev); 455 pci_ignore_hotplug(pdev); 456 if (radeon_is_atpx_hybrid()) 457 pci_set_power_state(pdev, PCI_D3cold); 458 else if (!radeon_has_atpx_dgpu_power_cntl()) 459 pci_set_power_state(pdev, PCI_D3hot); 460 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 461 462 return 0; 463 } 464 465 static int radeon_pmops_runtime_resume(struct device *dev) 466 { 467 struct pci_dev *pdev = to_pci_dev(dev); 468 struct drm_device *drm_dev = pci_get_drvdata(pdev); 469 int ret; 470 471 if (!radeon_is_px(drm_dev)) 472 return -EINVAL; 473 474 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 475 476 if (radeon_is_atpx_hybrid() || 477 !radeon_has_atpx_dgpu_power_cntl()) 478 pci_set_power_state(pdev, PCI_D0); 479 pci_restore_state(pdev); 480 ret = pci_enable_device(pdev); 481 if (ret) 482 return ret; 483 pci_set_master(pdev); 484 485 ret = radeon_resume_kms(drm_dev, false, false); 486 drm_kms_helper_poll_enable(drm_dev); 487 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 488 return 0; 489 } 490 491 static int radeon_pmops_runtime_idle(struct device *dev) 492 { 493 struct drm_device *drm_dev = dev_get_drvdata(dev); 494 struct drm_crtc *crtc; 495 496 if (!radeon_is_px(drm_dev)) { 497 pm_runtime_forbid(dev); 498 return -EBUSY; 499 } 500 501 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 502 if (crtc->enabled) { 503 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 504 return -EBUSY; 505 } 506 } 507 508 pm_runtime_mark_last_busy(dev); 509 pm_runtime_autosuspend(dev); 510 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 511 return 1; 512 } 513 514 long radeon_drm_ioctl(struct file *filp, 515 unsigned int cmd, unsigned long arg) 516 { 517 struct drm_file *file_priv = filp->private_data; 518 struct drm_device *dev; 519 long ret; 520 dev = file_priv->minor->dev; 521 ret = pm_runtime_get_sync(dev->dev); 522 if (ret < 0) { 523 pm_runtime_put_autosuspend(dev->dev); 524 return ret; 525 } 526 527 ret = drm_ioctl(filp, cmd, arg); 528 529 pm_runtime_mark_last_busy(dev->dev); 530 pm_runtime_put_autosuspend(dev->dev); 531 return ret; 532 } 533 534 #ifdef CONFIG_COMPAT 535 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 536 { 537 unsigned int nr = DRM_IOCTL_NR(cmd); 538 int ret; 539 540 if (nr < DRM_COMMAND_BASE) 541 return drm_compat_ioctl(filp, cmd, arg); 542 543 ret = radeon_drm_ioctl(filp, cmd, arg); 544 545 return ret; 546 } 547 #endif 548 549 static const struct dev_pm_ops radeon_pm_ops = { 550 .suspend = radeon_pmops_suspend, 551 .resume = radeon_pmops_resume, 552 .freeze = radeon_pmops_freeze, 553 .thaw = radeon_pmops_thaw, 554 .poweroff = radeon_pmops_freeze, 555 .restore = radeon_pmops_resume, 556 .runtime_suspend = radeon_pmops_runtime_suspend, 557 .runtime_resume = radeon_pmops_runtime_resume, 558 .runtime_idle = radeon_pmops_runtime_idle, 559 }; 560 561 static const struct file_operations radeon_driver_kms_fops = { 562 .owner = THIS_MODULE, 563 .open = drm_open, 564 .release = drm_release, 565 .unlocked_ioctl = radeon_drm_ioctl, 566 .mmap = radeon_mmap, 567 .poll = drm_poll, 568 .read = drm_read, 569 #ifdef CONFIG_COMPAT 570 .compat_ioctl = radeon_kms_compat_ioctl, 571 #endif 572 }; 573 574 static struct drm_driver kms_driver = { 575 .driver_features = 576 DRIVER_GEM | DRIVER_RENDER, 577 .load = radeon_driver_load_kms, 578 .open = radeon_driver_open_kms, 579 .postclose = radeon_driver_postclose_kms, 580 .lastclose = radeon_driver_lastclose_kms, 581 .unload = radeon_driver_unload_kms, 582 .irq_preinstall = radeon_driver_irq_preinstall_kms, 583 .irq_postinstall = radeon_driver_irq_postinstall_kms, 584 .irq_uninstall = radeon_driver_irq_uninstall_kms, 585 .irq_handler = radeon_driver_irq_handler_kms, 586 .ioctls = radeon_ioctls_kms, 587 .dumb_create = radeon_mode_dumb_create, 588 .dumb_map_offset = radeon_mode_dumb_mmap, 589 .fops = &radeon_driver_kms_fops, 590 591 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 592 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 593 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 594 595 .name = DRIVER_NAME, 596 .desc = DRIVER_DESC, 597 .date = DRIVER_DATE, 598 .major = KMS_DRIVER_MAJOR, 599 .minor = KMS_DRIVER_MINOR, 600 .patchlevel = KMS_DRIVER_PATCHLEVEL, 601 }; 602 603 static struct drm_driver *driver; 604 static struct pci_driver *pdriver; 605 606 static struct pci_driver radeon_kms_pci_driver = { 607 .name = DRIVER_NAME, 608 .id_table = pciidlist, 609 .probe = radeon_pci_probe, 610 .remove = radeon_pci_remove, 611 .shutdown = radeon_pci_shutdown, 612 .driver.pm = &radeon_pm_ops, 613 }; 614 615 static int __init radeon_init(void) 616 { 617 if (vgacon_text_force() && radeon_modeset == -1) { 618 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 619 radeon_modeset = 0; 620 } 621 /* set to modesetting by default if not nomodeset */ 622 if (radeon_modeset == -1) 623 radeon_modeset = 1; 624 625 if (radeon_modeset == 1) { 626 DRM_INFO("radeon kernel modesetting enabled.\n"); 627 driver = &kms_driver; 628 pdriver = &radeon_kms_pci_driver; 629 driver->driver_features |= DRIVER_MODESET; 630 driver->num_ioctls = radeon_max_kms_ioctl; 631 radeon_register_atpx_handler(); 632 633 } else { 634 DRM_ERROR("No UMS support in radeon module!\n"); 635 return -EINVAL; 636 } 637 638 return pci_register_driver(pdriver); 639 } 640 641 static void __exit radeon_exit(void) 642 { 643 pci_unregister_driver(pdriver); 644 radeon_unregister_atpx_handler(); 645 mmu_notifier_synchronize(); 646 } 647 648 module_init(radeon_init); 649 module_exit(radeon_exit); 650 651 MODULE_AUTHOR(DRIVER_AUTHOR); 652 MODULE_DESCRIPTION(DRIVER_DESC); 653 MODULE_LICENSE("GPL and additional rights"); 654