1 /*
2  * \file radeon_drv.c
3  * ATI Radeon driver
4  *
5  * \author Gareth Hughes <gareth@valinux.com>
6  */
7 
8 /*
9  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice (including the next
20  * paragraph) shall be included in all copies or substantial portions of the
21  * Software.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
26  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29  * OTHER DEALINGS IN THE SOFTWARE.
30  */
31 
32 
33 #include <linux/compat.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/mmu_notifier.h>
38 #include <linux/pci.h>
39 
40 #include <drm/drm_aperture.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_drv.h>
43 #include <drm/drm_fb_helper.h>
44 #include <drm/drm_file.h>
45 #include <drm/drm_gem.h>
46 #include <drm/drm_ioctl.h>
47 #include <drm/drm_pciids.h>
48 #include <drm/drm_probe_helper.h>
49 #include <drm/drm_vblank.h>
50 #include <drm/radeon_drm.h>
51 
52 #include "radeon_drv.h"
53 #include "radeon.h"
54 #include "radeon_kms.h"
55 #include "radeon_ttm.h"
56 #include "radeon_device.h"
57 #include "radeon_prime.h"
58 
59 /*
60  * KMS wrapper.
61  * - 2.0.0 - initial interface
62  * - 2.1.0 - add square tiling interface
63  * - 2.2.0 - add r6xx/r7xx const buffer support
64  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
65  * - 2.4.0 - add crtc id query
66  * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
67  * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
68  *   2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
69  *   2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
70  *   2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
71  *   2.10.0 - fusion 2D tiling
72  *   2.11.0 - backend map, initial compute support for the CS checker
73  *   2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
74  *   2.13.0 - virtual memory support, streamout
75  *   2.14.0 - add evergreen tiling informations
76  *   2.15.0 - add max_pipes query
77  *   2.16.0 - fix evergreen 2D tiled surface calculation
78  *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
79  *   2.18.0 - r600-eg: allow "invalid" DB formats
80  *   2.19.0 - r600-eg: MSAA textures
81  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
82  *   2.21.0 - r600-r700: FMASK and CMASK
83  *   2.22.0 - r600 only: RESOLVE_BOX allowed
84  *   2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
85  *   2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
86  *   2.25.0 - eg+: new info request for num SE and num SH
87  *   2.26.0 - r600-eg: fix htile size computation
88  *   2.27.0 - r600-SI: Add CS ioctl support for async DMA
89  *   2.28.0 - r600-eg: Add MEM_WRITE packet support
90  *   2.29.0 - R500 FP16 color clear registers
91  *   2.30.0 - fix for FMASK texturing
92  *   2.31.0 - Add fastfb support for rs690
93  *   2.32.0 - new info request for rings working
94  *   2.33.0 - Add SI tiling mode array query
95  *   2.34.0 - Add CIK tiling mode array query
96  *   2.35.0 - Add CIK macrotile mode array query
97  *   2.36.0 - Fix CIK DCE tiling setup
98  *   2.37.0 - allow GS ring setup on r6xx/r7xx
99  *   2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
100  *            CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
101  *   2.39.0 - Add INFO query for number of active CUs
102  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
103  *            CS to GPU on >= r600
104  *   2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
105  *   2.42.0 - Add VCE/VUI (Video Usability Information) support
106  *   2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
107  *   2.44.0 - SET_APPEND_CNT packet3 support
108  *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
109  *   2.46.0 - Add PFP_SYNC_ME support on evergreen
110  *   2.47.0 - Add UVD_NO_OP register support
111  *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
112  *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
113  *   2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
114  */
115 #define KMS_DRIVER_MAJOR	2
116 #define KMS_DRIVER_MINOR	50
117 #define KMS_DRIVER_PATCHLEVEL	0
118 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
119 		       bool fbcon, bool freeze);
120 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
121 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
122 				      unsigned int flags, int *vpos, int *hpos,
123 				      ktime_t *stime, ktime_t *etime,
124 				      const struct drm_display_mode *mode);
125 extern bool radeon_is_px(struct drm_device *dev);
126 int radeon_mode_dumb_mmap(struct drm_file *filp,
127 			  struct drm_device *dev,
128 			  uint32_t handle, uint64_t *offset_p);
129 int radeon_mode_dumb_create(struct drm_file *file_priv,
130 			    struct drm_device *dev,
131 			    struct drm_mode_create_dumb *args);
132 
133 /* atpx handler */
134 #if defined(CONFIG_VGA_SWITCHEROO)
135 void radeon_register_atpx_handler(void);
136 void radeon_unregister_atpx_handler(void);
137 bool radeon_has_atpx_dgpu_power_cntl(void);
138 bool radeon_is_atpx_hybrid(void);
139 #else
140 static inline void radeon_register_atpx_handler(void) {}
141 static inline void radeon_unregister_atpx_handler(void) {}
142 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
143 static inline bool radeon_is_atpx_hybrid(void) { return false; }
144 #endif
145 
146 int radeon_no_wb;
147 int radeon_modeset = -1;
148 int radeon_dynclks = -1;
149 int radeon_r4xx_atom = 0;
150 int radeon_agpmode = -1;
151 int radeon_vram_limit = 0;
152 int radeon_gart_size = -1; /* auto */
153 int radeon_benchmarking = 0;
154 int radeon_testing = 0;
155 int radeon_connector_table = 0;
156 int radeon_tv = 1;
157 int radeon_audio = -1;
158 int radeon_disp_priority = 0;
159 int radeon_hw_i2c = 0;
160 int radeon_pcie_gen2 = -1;
161 int radeon_msi = -1;
162 int radeon_lockup_timeout = 10000;
163 int radeon_fastfb = 0;
164 int radeon_dpm = -1;
165 int radeon_aspm = -1;
166 int radeon_runtime_pm = -1;
167 int radeon_hard_reset = 0;
168 int radeon_vm_size = 8;
169 int radeon_vm_block_size = -1;
170 int radeon_deep_color = 0;
171 int radeon_use_pflipirq = 2;
172 int radeon_bapm = -1;
173 int radeon_backlight = -1;
174 int radeon_auxch = -1;
175 int radeon_mst = 0;
176 int radeon_uvd = 1;
177 int radeon_vce = 1;
178 
179 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
180 module_param_named(no_wb, radeon_no_wb, int, 0444);
181 
182 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
183 module_param_named(modeset, radeon_modeset, int, 0400);
184 
185 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
186 module_param_named(dynclks, radeon_dynclks, int, 0444);
187 
188 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
189 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
190 
191 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
192 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
193 
194 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
195 module_param_named(agpmode, radeon_agpmode, int, 0444);
196 
197 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
198 module_param_named(gartsize, radeon_gart_size, int, 0600);
199 
200 MODULE_PARM_DESC(benchmark, "Run benchmark");
201 module_param_named(benchmark, radeon_benchmarking, int, 0444);
202 
203 MODULE_PARM_DESC(test, "Run tests");
204 module_param_named(test, radeon_testing, int, 0444);
205 
206 MODULE_PARM_DESC(connector_table, "Force connector table");
207 module_param_named(connector_table, radeon_connector_table, int, 0444);
208 
209 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
210 module_param_named(tv, radeon_tv, int, 0444);
211 
212 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
213 module_param_named(audio, radeon_audio, int, 0444);
214 
215 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
216 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
217 
218 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
219 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
220 
221 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
222 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
223 
224 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
225 module_param_named(msi, radeon_msi, int, 0444);
226 
227 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
228 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
229 
230 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
231 module_param_named(fastfb, radeon_fastfb, int, 0444);
232 
233 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
234 module_param_named(dpm, radeon_dpm, int, 0444);
235 
236 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
237 module_param_named(aspm, radeon_aspm, int, 0444);
238 
239 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
240 module_param_named(runpm, radeon_runtime_pm, int, 0444);
241 
242 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
243 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
244 
245 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
246 module_param_named(vm_size, radeon_vm_size, int, 0444);
247 
248 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
249 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
250 
251 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
252 module_param_named(deep_color, radeon_deep_color, int, 0444);
253 
254 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
255 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
256 
257 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
258 module_param_named(bapm, radeon_bapm, int, 0444);
259 
260 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
261 module_param_named(backlight, radeon_backlight, int, 0444);
262 
263 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
264 module_param_named(auxch, radeon_auxch, int, 0444);
265 
266 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
267 module_param_named(mst, radeon_mst, int, 0444);
268 
269 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
270 module_param_named(uvd, radeon_uvd, int, 0444);
271 
272 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
273 module_param_named(vce, radeon_vce, int, 0444);
274 
275 int radeon_si_support = 1;
276 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
277 module_param_named(si_support, radeon_si_support, int, 0444);
278 
279 int radeon_cik_support = 1;
280 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
281 module_param_named(cik_support, radeon_cik_support, int, 0444);
282 
283 static struct pci_device_id pciidlist[] = {
284 	radeon_PCI_IDS
285 };
286 
287 MODULE_DEVICE_TABLE(pci, pciidlist);
288 
289 static const struct drm_driver kms_driver;
290 
291 static int radeon_pci_probe(struct pci_dev *pdev,
292 			    const struct pci_device_id *ent)
293 {
294 	unsigned long flags = 0;
295 	struct drm_device *dev;
296 	int ret;
297 
298 	if (!ent)
299 		return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
300 
301 	flags = ent->driver_data;
302 
303 	if (!radeon_si_support) {
304 		switch (flags & RADEON_FAMILY_MASK) {
305 		case CHIP_TAHITI:
306 		case CHIP_PITCAIRN:
307 		case CHIP_VERDE:
308 		case CHIP_OLAND:
309 		case CHIP_HAINAN:
310 			dev_info(&pdev->dev,
311 				 "SI support disabled by module param\n");
312 			return -ENODEV;
313 		}
314 	}
315 	if (!radeon_cik_support) {
316 		switch (flags & RADEON_FAMILY_MASK) {
317 		case CHIP_KAVERI:
318 		case CHIP_BONAIRE:
319 		case CHIP_HAWAII:
320 		case CHIP_KABINI:
321 		case CHIP_MULLINS:
322 			dev_info(&pdev->dev,
323 				 "CIK support disabled by module param\n");
324 			return -ENODEV;
325 		}
326 	}
327 
328 	if (vga_switcheroo_client_probe_defer(pdev))
329 		return -EPROBE_DEFER;
330 
331 	/* Get rid of things like offb */
332 	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver);
333 	if (ret)
334 		return ret;
335 
336 	dev = drm_dev_alloc(&kms_driver, &pdev->dev);
337 	if (IS_ERR(dev))
338 		return PTR_ERR(dev);
339 
340 	ret = pci_enable_device(pdev);
341 	if (ret)
342 		goto err_free;
343 
344 	pci_set_drvdata(pdev, dev);
345 
346 	ret = drm_dev_register(dev, ent->driver_data);
347 	if (ret)
348 		goto err_agp;
349 
350 	return 0;
351 
352 err_agp:
353 	pci_disable_device(pdev);
354 err_free:
355 	drm_dev_put(dev);
356 	return ret;
357 }
358 
359 static void
360 radeon_pci_remove(struct pci_dev *pdev)
361 {
362 	struct drm_device *dev = pci_get_drvdata(pdev);
363 
364 	drm_put_dev(dev);
365 }
366 
367 static void
368 radeon_pci_shutdown(struct pci_dev *pdev)
369 {
370 	/* if we are running in a VM, make sure the device
371 	 * torn down properly on reboot/shutdown
372 	 */
373 	if (radeon_device_is_virtual())
374 		radeon_pci_remove(pdev);
375 
376 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
377 	/*
378 	 * Some adapters need to be suspended before a
379 	 * shutdown occurs in order to prevent an error
380 	 * during kexec, shutdown or reboot.
381 	 * Make this power and Loongson specific because
382 	 * it breaks some other boards.
383 	 */
384 	radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
385 #endif
386 }
387 
388 static int radeon_pmops_suspend(struct device *dev)
389 {
390 	struct drm_device *drm_dev = dev_get_drvdata(dev);
391 	return radeon_suspend_kms(drm_dev, true, true, false);
392 }
393 
394 static int radeon_pmops_resume(struct device *dev)
395 {
396 	struct drm_device *drm_dev = dev_get_drvdata(dev);
397 
398 	/* GPU comes up enabled by the bios on resume */
399 	if (radeon_is_px(drm_dev)) {
400 		pm_runtime_disable(dev);
401 		pm_runtime_set_active(dev);
402 		pm_runtime_enable(dev);
403 	}
404 
405 	return radeon_resume_kms(drm_dev, true, true);
406 }
407 
408 static int radeon_pmops_freeze(struct device *dev)
409 {
410 	struct drm_device *drm_dev = dev_get_drvdata(dev);
411 	return radeon_suspend_kms(drm_dev, false, true, true);
412 }
413 
414 static int radeon_pmops_thaw(struct device *dev)
415 {
416 	struct drm_device *drm_dev = dev_get_drvdata(dev);
417 	return radeon_resume_kms(drm_dev, false, true);
418 }
419 
420 static int radeon_pmops_runtime_suspend(struct device *dev)
421 {
422 	struct pci_dev *pdev = to_pci_dev(dev);
423 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
424 
425 	if (!radeon_is_px(drm_dev)) {
426 		pm_runtime_forbid(dev);
427 		return -EBUSY;
428 	}
429 
430 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
431 	drm_kms_helper_poll_disable(drm_dev);
432 
433 	radeon_suspend_kms(drm_dev, false, false, false);
434 	pci_save_state(pdev);
435 	pci_disable_device(pdev);
436 	pci_ignore_hotplug(pdev);
437 	if (radeon_is_atpx_hybrid())
438 		pci_set_power_state(pdev, PCI_D3cold);
439 	else if (!radeon_has_atpx_dgpu_power_cntl())
440 		pci_set_power_state(pdev, PCI_D3hot);
441 	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
442 
443 	return 0;
444 }
445 
446 static int radeon_pmops_runtime_resume(struct device *dev)
447 {
448 	struct pci_dev *pdev = to_pci_dev(dev);
449 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
450 	int ret;
451 
452 	if (!radeon_is_px(drm_dev))
453 		return -EINVAL;
454 
455 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
456 
457 	if (radeon_is_atpx_hybrid() ||
458 	    !radeon_has_atpx_dgpu_power_cntl())
459 		pci_set_power_state(pdev, PCI_D0);
460 	pci_restore_state(pdev);
461 	ret = pci_enable_device(pdev);
462 	if (ret)
463 		return ret;
464 	pci_set_master(pdev);
465 
466 	ret = radeon_resume_kms(drm_dev, false, false);
467 	drm_kms_helper_poll_enable(drm_dev);
468 	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
469 	return 0;
470 }
471 
472 static int radeon_pmops_runtime_idle(struct device *dev)
473 {
474 	struct drm_device *drm_dev = dev_get_drvdata(dev);
475 	struct drm_crtc *crtc;
476 
477 	if (!radeon_is_px(drm_dev)) {
478 		pm_runtime_forbid(dev);
479 		return -EBUSY;
480 	}
481 
482 	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
483 		if (crtc->enabled) {
484 			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
485 			return -EBUSY;
486 		}
487 	}
488 
489 	pm_runtime_mark_last_busy(dev);
490 	pm_runtime_autosuspend(dev);
491 	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
492 	return 1;
493 }
494 
495 long radeon_drm_ioctl(struct file *filp,
496 		      unsigned int cmd, unsigned long arg)
497 {
498 	struct drm_file *file_priv = filp->private_data;
499 	struct drm_device *dev;
500 	long ret;
501 	dev = file_priv->minor->dev;
502 	ret = pm_runtime_get_sync(dev->dev);
503 	if (ret < 0) {
504 		pm_runtime_put_autosuspend(dev->dev);
505 		return ret;
506 	}
507 
508 	ret = drm_ioctl(filp, cmd, arg);
509 
510 	pm_runtime_mark_last_busy(dev->dev);
511 	pm_runtime_put_autosuspend(dev->dev);
512 	return ret;
513 }
514 
515 #ifdef CONFIG_COMPAT
516 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
517 {
518 	unsigned int nr = DRM_IOCTL_NR(cmd);
519 	int ret;
520 
521 	if (nr < DRM_COMMAND_BASE)
522 		return drm_compat_ioctl(filp, cmd, arg);
523 
524 	ret = radeon_drm_ioctl(filp, cmd, arg);
525 
526 	return ret;
527 }
528 #endif
529 
530 static const struct dev_pm_ops radeon_pm_ops = {
531 	.suspend = radeon_pmops_suspend,
532 	.resume = radeon_pmops_resume,
533 	.freeze = radeon_pmops_freeze,
534 	.thaw = radeon_pmops_thaw,
535 	.poweroff = radeon_pmops_freeze,
536 	.restore = radeon_pmops_resume,
537 	.runtime_suspend = radeon_pmops_runtime_suspend,
538 	.runtime_resume = radeon_pmops_runtime_resume,
539 	.runtime_idle = radeon_pmops_runtime_idle,
540 };
541 
542 static const struct file_operations radeon_driver_kms_fops = {
543 	.owner = THIS_MODULE,
544 	.open = drm_open,
545 	.release = drm_release,
546 	.unlocked_ioctl = radeon_drm_ioctl,
547 	.mmap = drm_gem_mmap,
548 	.poll = drm_poll,
549 	.read = drm_read,
550 #ifdef CONFIG_COMPAT
551 	.compat_ioctl = radeon_kms_compat_ioctl,
552 #endif
553 };
554 
555 static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
556 	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
557 	DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
558 	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
559 	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
560 	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
561 	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
562 	DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
563 	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
564 	DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
565 	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
566 	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
567 	DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
568 	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
569 	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
570 	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
571 	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
572 	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
573 	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
574 	DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
575 	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
576 	DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
577 	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
578 	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
579 	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
580 	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
581 	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
582 	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
583 	/* KMS */
584 	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
585 	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
586 	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
587 	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
588 	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
589 	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
590 	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
591 	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
592 	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
593 	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
594 	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
595 	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
596 	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
597 	DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
598 	DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
599 };
600 
601 static const struct drm_driver kms_driver = {
602 	.driver_features =
603 	    DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
604 	.load = radeon_driver_load_kms,
605 	.open = radeon_driver_open_kms,
606 	.postclose = radeon_driver_postclose_kms,
607 	.lastclose = radeon_driver_lastclose_kms,
608 	.unload = radeon_driver_unload_kms,
609 	.ioctls = radeon_ioctls_kms,
610 	.num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
611 	.dumb_create = radeon_mode_dumb_create,
612 	.dumb_map_offset = radeon_mode_dumb_mmap,
613 	.fops = &radeon_driver_kms_fops,
614 
615 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
616 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
617 	.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
618 	.gem_prime_mmap = drm_gem_prime_mmap,
619 
620 	.name = DRIVER_NAME,
621 	.desc = DRIVER_DESC,
622 	.date = DRIVER_DATE,
623 	.major = KMS_DRIVER_MAJOR,
624 	.minor = KMS_DRIVER_MINOR,
625 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
626 };
627 
628 static struct pci_driver radeon_kms_pci_driver = {
629 	.name = DRIVER_NAME,
630 	.id_table = pciidlist,
631 	.probe = radeon_pci_probe,
632 	.remove = radeon_pci_remove,
633 	.shutdown = radeon_pci_shutdown,
634 	.driver.pm = &radeon_pm_ops,
635 };
636 
637 static int __init radeon_module_init(void)
638 {
639 	if (drm_firmware_drivers_only() && radeon_modeset == -1)
640 		radeon_modeset = 0;
641 
642 	if (radeon_modeset == 0)
643 		return -EINVAL;
644 
645 	DRM_INFO("radeon kernel modesetting enabled.\n");
646 	radeon_register_atpx_handler();
647 
648 	return pci_register_driver(&radeon_kms_pci_driver);
649 }
650 
651 static void __exit radeon_module_exit(void)
652 {
653 	pci_unregister_driver(&radeon_kms_pci_driver);
654 	radeon_unregister_atpx_handler();
655 	mmu_notifier_synchronize();
656 }
657 
658 module_init(radeon_module_init);
659 module_exit(radeon_module_exit);
660 
661 MODULE_AUTHOR(DRIVER_AUTHOR);
662 MODULE_DESCRIPTION(DRIVER_DESC);
663 MODULE_LICENSE("GPL and additional rights");
664