1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include "drm_crtc_helper.h" 34 #include "drm_edid.h" 35 36 static int radeon_ddc_dump(struct drm_connector *connector); 37 38 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 39 { 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 int i; 44 45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id); 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 47 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 51 52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 55 56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 57 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 59 60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 61 for (i = 0; i < 256; i++) { 62 WREG32(AVIVO_DC_LUT_30_COLOR, 63 (radeon_crtc->lut_r[i] << 20) | 64 (radeon_crtc->lut_g[i] << 10) | 65 (radeon_crtc->lut_b[i] << 0)); 66 } 67 68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 } 70 71 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 72 { 73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct radeon_device *rdev = dev->dev_private; 76 int i; 77 uint32_t dac2_cntl; 78 79 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 80 if (radeon_crtc->crtc_id == 0) 81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 82 else 83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 84 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 85 86 WREG8(RADEON_PALETTE_INDEX, 0); 87 for (i = 0; i < 256; i++) { 88 WREG32(RADEON_PALETTE_30_DATA, 89 (radeon_crtc->lut_r[i] << 20) | 90 (radeon_crtc->lut_g[i] << 10) | 91 (radeon_crtc->lut_b[i] << 0)); 92 } 93 } 94 95 void radeon_crtc_load_lut(struct drm_crtc *crtc) 96 { 97 struct drm_device *dev = crtc->dev; 98 struct radeon_device *rdev = dev->dev_private; 99 100 if (!crtc->enabled) 101 return; 102 103 if (ASIC_IS_AVIVO(rdev)) 104 avivo_crtc_load_lut(crtc); 105 else 106 legacy_crtc_load_lut(crtc); 107 } 108 109 /** Sets the color ramps on behalf of RandR */ 110 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 111 u16 blue, int regno) 112 { 113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 114 115 if (regno == 0) 116 DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id); 117 radeon_crtc->lut_r[regno] = red >> 6; 118 radeon_crtc->lut_g[regno] = green >> 6; 119 radeon_crtc->lut_b[regno] = blue >> 6; 120 } 121 122 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 123 u16 *blue, uint32_t size) 124 { 125 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 126 int i, j; 127 128 if (size != 256) { 129 return; 130 } 131 if (crtc->fb == NULL) { 132 return; 133 } 134 135 if (crtc->fb->depth == 16) { 136 for (i = 0; i < 64; i++) { 137 if (i <= 31) { 138 for (j = 0; j < 8; j++) { 139 radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6; 140 radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6; 141 } 142 } 143 for (j = 0; j < 4; j++) 144 radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6; 145 } 146 } else { 147 for (i = 0; i < 256; i++) { 148 radeon_crtc->lut_r[i] = red[i] >> 6; 149 radeon_crtc->lut_g[i] = green[i] >> 6; 150 radeon_crtc->lut_b[i] = blue[i] >> 6; 151 } 152 } 153 154 radeon_crtc_load_lut(crtc); 155 } 156 157 static void radeon_crtc_destroy(struct drm_crtc *crtc) 158 { 159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 160 161 drm_crtc_cleanup(crtc); 162 kfree(radeon_crtc); 163 } 164 165 static const struct drm_crtc_funcs radeon_crtc_funcs = { 166 .cursor_set = radeon_crtc_cursor_set, 167 .cursor_move = radeon_crtc_cursor_move, 168 .gamma_set = radeon_crtc_gamma_set, 169 .set_config = drm_crtc_helper_set_config, 170 .destroy = radeon_crtc_destroy, 171 }; 172 173 static void radeon_crtc_init(struct drm_device *dev, int index) 174 { 175 struct radeon_device *rdev = dev->dev_private; 176 struct radeon_crtc *radeon_crtc; 177 int i; 178 179 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 180 if (radeon_crtc == NULL) 181 return; 182 183 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 184 185 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 186 radeon_crtc->crtc_id = index; 187 rdev->mode_info.crtcs[index] = radeon_crtc; 188 189 #if 0 190 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 191 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 192 radeon_crtc->mode_set.num_connectors = 0; 193 #endif 194 195 for (i = 0; i < 256; i++) { 196 radeon_crtc->lut_r[i] = i << 2; 197 radeon_crtc->lut_g[i] = i << 2; 198 radeon_crtc->lut_b[i] = i << 2; 199 } 200 201 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 202 radeon_atombios_init_crtc(dev, radeon_crtc); 203 else 204 radeon_legacy_init_crtc(dev, radeon_crtc); 205 } 206 207 static const char *encoder_names[34] = { 208 "NONE", 209 "INTERNAL_LVDS", 210 "INTERNAL_TMDS1", 211 "INTERNAL_TMDS2", 212 "INTERNAL_DAC1", 213 "INTERNAL_DAC2", 214 "INTERNAL_SDVOA", 215 "INTERNAL_SDVOB", 216 "SI170B", 217 "CH7303", 218 "CH7301", 219 "INTERNAL_DVO1", 220 "EXTERNAL_SDVOA", 221 "EXTERNAL_SDVOB", 222 "TITFP513", 223 "INTERNAL_LVTM1", 224 "VT1623", 225 "HDMI_SI1930", 226 "HDMI_INTERNAL", 227 "INTERNAL_KLDSCP_TMDS1", 228 "INTERNAL_KLDSCP_DVO1", 229 "INTERNAL_KLDSCP_DAC1", 230 "INTERNAL_KLDSCP_DAC2", 231 "SI178", 232 "MVPU_FPGA", 233 "INTERNAL_DDI", 234 "VT1625", 235 "HDMI_SI1932", 236 "DP_AN9801", 237 "DP_DP501", 238 "INTERNAL_UNIPHY", 239 "INTERNAL_KLDSCP_LVTMA", 240 "INTERNAL_UNIPHY1", 241 "INTERNAL_UNIPHY2", 242 }; 243 244 static const char *connector_names[13] = { 245 "Unknown", 246 "VGA", 247 "DVI-I", 248 "DVI-D", 249 "DVI-A", 250 "Composite", 251 "S-video", 252 "LVDS", 253 "Component", 254 "DIN", 255 "DisplayPort", 256 "HDMI-A", 257 "HDMI-B", 258 }; 259 260 static void radeon_print_display_setup(struct drm_device *dev) 261 { 262 struct drm_connector *connector; 263 struct radeon_connector *radeon_connector; 264 struct drm_encoder *encoder; 265 struct radeon_encoder *radeon_encoder; 266 uint32_t devices; 267 int i = 0; 268 269 DRM_INFO("Radeon Display Connectors\n"); 270 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 271 radeon_connector = to_radeon_connector(connector); 272 DRM_INFO("Connector %d:\n", i); 273 DRM_INFO(" %s\n", connector_names[connector->connector_type]); 274 if (radeon_connector->ddc_bus) 275 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 276 radeon_connector->ddc_bus->rec.mask_clk_reg, 277 radeon_connector->ddc_bus->rec.mask_data_reg, 278 radeon_connector->ddc_bus->rec.a_clk_reg, 279 radeon_connector->ddc_bus->rec.a_data_reg, 280 radeon_connector->ddc_bus->rec.put_clk_reg, 281 radeon_connector->ddc_bus->rec.put_data_reg, 282 radeon_connector->ddc_bus->rec.get_clk_reg, 283 radeon_connector->ddc_bus->rec.get_data_reg); 284 DRM_INFO(" Encoders:\n"); 285 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 286 radeon_encoder = to_radeon_encoder(encoder); 287 devices = radeon_encoder->devices & radeon_connector->devices; 288 if (devices) { 289 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 290 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 291 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 292 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 293 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 294 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 295 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 296 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 297 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 298 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 299 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 300 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 301 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 302 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 303 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 304 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 305 if (devices & ATOM_DEVICE_TV1_SUPPORT) 306 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 307 if (devices & ATOM_DEVICE_CV_SUPPORT) 308 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 309 } 310 } 311 i++; 312 } 313 } 314 315 static bool radeon_setup_enc_conn(struct drm_device *dev) 316 { 317 struct radeon_device *rdev = dev->dev_private; 318 struct drm_connector *drm_connector; 319 bool ret = false; 320 321 if (rdev->bios) { 322 if (rdev->is_atom_bios) { 323 if (rdev->family >= CHIP_R600) 324 ret = radeon_get_atom_connector_info_from_object_table(dev); 325 else 326 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 327 } else 328 ret = radeon_get_legacy_connector_info_from_bios(dev); 329 } else { 330 if (!ASIC_IS_AVIVO(rdev)) 331 ret = radeon_get_legacy_connector_info_from_table(dev); 332 } 333 if (ret) { 334 radeon_print_display_setup(dev); 335 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) 336 radeon_ddc_dump(drm_connector); 337 } 338 339 return ret; 340 } 341 342 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 343 { 344 struct edid *edid; 345 int ret = 0; 346 347 if (!radeon_connector->ddc_bus) 348 return -1; 349 if (!radeon_connector->edid) { 350 radeon_i2c_do_lock(radeon_connector, 1); 351 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 352 radeon_i2c_do_lock(radeon_connector, 0); 353 } else 354 edid = radeon_connector->edid; 355 356 if (edid) { 357 /* update digital bits here */ 358 if (edid->input & DRM_EDID_INPUT_DIGITAL) 359 radeon_connector->use_digital = 1; 360 else 361 radeon_connector->use_digital = 0; 362 drm_mode_connector_update_edid_property(&radeon_connector->base, edid); 363 ret = drm_add_edid_modes(&radeon_connector->base, edid); 364 kfree(edid); 365 return ret; 366 } 367 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 368 return 0; 369 } 370 371 static int radeon_ddc_dump(struct drm_connector *connector) 372 { 373 struct edid *edid; 374 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 375 int ret = 0; 376 377 if (!radeon_connector->ddc_bus) 378 return -1; 379 radeon_i2c_do_lock(radeon_connector, 1); 380 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); 381 radeon_i2c_do_lock(radeon_connector, 0); 382 if (edid) { 383 kfree(edid); 384 } 385 return ret; 386 } 387 388 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 389 { 390 uint64_t mod; 391 392 n += d / 2; 393 394 mod = do_div(n, d); 395 return n; 396 } 397 398 void radeon_compute_pll(struct radeon_pll *pll, 399 uint64_t freq, 400 uint32_t *dot_clock_p, 401 uint32_t *fb_div_p, 402 uint32_t *frac_fb_div_p, 403 uint32_t *ref_div_p, 404 uint32_t *post_div_p, 405 int flags) 406 { 407 uint32_t min_ref_div = pll->min_ref_div; 408 uint32_t max_ref_div = pll->max_ref_div; 409 uint32_t min_fractional_feed_div = 0; 410 uint32_t max_fractional_feed_div = 0; 411 uint32_t best_vco = pll->best_vco; 412 uint32_t best_post_div = 1; 413 uint32_t best_ref_div = 1; 414 uint32_t best_feedback_div = 1; 415 uint32_t best_frac_feedback_div = 0; 416 uint32_t best_freq = -1; 417 uint32_t best_error = 0xffffffff; 418 uint32_t best_vco_diff = 1; 419 uint32_t post_div; 420 421 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 422 freq = freq * 1000; 423 424 if (flags & RADEON_PLL_USE_REF_DIV) 425 min_ref_div = max_ref_div = pll->reference_div; 426 else { 427 while (min_ref_div < max_ref_div-1) { 428 uint32_t mid = (min_ref_div + max_ref_div) / 2; 429 uint32_t pll_in = pll->reference_freq / mid; 430 if (pll_in < pll->pll_in_min) 431 max_ref_div = mid; 432 else if (pll_in > pll->pll_in_max) 433 min_ref_div = mid; 434 else 435 break; 436 } 437 } 438 439 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 440 min_fractional_feed_div = pll->min_frac_feedback_div; 441 max_fractional_feed_div = pll->max_frac_feedback_div; 442 } 443 444 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { 445 uint32_t ref_div; 446 447 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 448 continue; 449 450 /* legacy radeons only have a few post_divs */ 451 if (flags & RADEON_PLL_LEGACY) { 452 if ((post_div == 5) || 453 (post_div == 7) || 454 (post_div == 9) || 455 (post_div == 10) || 456 (post_div == 11) || 457 (post_div == 13) || 458 (post_div == 14) || 459 (post_div == 15)) 460 continue; 461 } 462 463 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 464 uint32_t feedback_div, current_freq = 0, error, vco_diff; 465 uint32_t pll_in = pll->reference_freq / ref_div; 466 uint32_t min_feed_div = pll->min_feedback_div; 467 uint32_t max_feed_div = pll->max_feedback_div + 1; 468 469 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 470 continue; 471 472 while (min_feed_div < max_feed_div) { 473 uint32_t vco; 474 uint32_t min_frac_feed_div = min_fractional_feed_div; 475 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 476 uint32_t frac_feedback_div; 477 uint64_t tmp; 478 479 feedback_div = (min_feed_div + max_feed_div) / 2; 480 481 tmp = (uint64_t)pll->reference_freq * feedback_div; 482 vco = radeon_div(tmp, ref_div); 483 484 if (vco < pll->pll_out_min) { 485 min_feed_div = feedback_div + 1; 486 continue; 487 } else if (vco > pll->pll_out_max) { 488 max_feed_div = feedback_div; 489 continue; 490 } 491 492 while (min_frac_feed_div < max_frac_feed_div) { 493 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 494 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 495 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 496 current_freq = radeon_div(tmp, ref_div * post_div); 497 498 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 499 error = freq - current_freq; 500 error = error < 0 ? 0xffffffff : error; 501 } else 502 error = abs(current_freq - freq); 503 vco_diff = abs(vco - best_vco); 504 505 if ((best_vco == 0 && error < best_error) || 506 (best_vco != 0 && 507 (error < best_error - 100 || 508 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 509 best_post_div = post_div; 510 best_ref_div = ref_div; 511 best_feedback_div = feedback_div; 512 best_frac_feedback_div = frac_feedback_div; 513 best_freq = current_freq; 514 best_error = error; 515 best_vco_diff = vco_diff; 516 } else if (current_freq == freq) { 517 if (best_freq == -1) { 518 best_post_div = post_div; 519 best_ref_div = ref_div; 520 best_feedback_div = feedback_div; 521 best_frac_feedback_div = frac_feedback_div; 522 best_freq = current_freq; 523 best_error = error; 524 best_vco_diff = vco_diff; 525 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 526 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 527 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 528 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 529 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 530 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 531 best_post_div = post_div; 532 best_ref_div = ref_div; 533 best_feedback_div = feedback_div; 534 best_frac_feedback_div = frac_feedback_div; 535 best_freq = current_freq; 536 best_error = error; 537 best_vco_diff = vco_diff; 538 } 539 } 540 if (current_freq < freq) 541 min_frac_feed_div = frac_feedback_div + 1; 542 else 543 max_frac_feed_div = frac_feedback_div; 544 } 545 if (current_freq < freq) 546 min_feed_div = feedback_div + 1; 547 else 548 max_feed_div = feedback_div; 549 } 550 } 551 } 552 553 *dot_clock_p = best_freq / 10000; 554 *fb_div_p = best_feedback_div; 555 *frac_fb_div_p = best_frac_feedback_div; 556 *ref_div_p = best_ref_div; 557 *post_div_p = best_post_div; 558 } 559 560 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 561 { 562 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 563 struct drm_device *dev = fb->dev; 564 565 if (fb->fbdev) 566 radeonfb_remove(dev, fb); 567 568 if (radeon_fb->obj) { 569 radeon_gem_object_unpin(radeon_fb->obj); 570 mutex_lock(&dev->struct_mutex); 571 drm_gem_object_unreference(radeon_fb->obj); 572 mutex_unlock(&dev->struct_mutex); 573 } 574 drm_framebuffer_cleanup(fb); 575 kfree(radeon_fb); 576 } 577 578 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 579 struct drm_file *file_priv, 580 unsigned int *handle) 581 { 582 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 583 584 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 585 } 586 587 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 588 .destroy = radeon_user_framebuffer_destroy, 589 .create_handle = radeon_user_framebuffer_create_handle, 590 }; 591 592 struct drm_framebuffer * 593 radeon_framebuffer_create(struct drm_device *dev, 594 struct drm_mode_fb_cmd *mode_cmd, 595 struct drm_gem_object *obj) 596 { 597 struct radeon_framebuffer *radeon_fb; 598 599 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 600 if (radeon_fb == NULL) { 601 return NULL; 602 } 603 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); 604 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); 605 radeon_fb->obj = obj; 606 return &radeon_fb->base; 607 } 608 609 static struct drm_framebuffer * 610 radeon_user_framebuffer_create(struct drm_device *dev, 611 struct drm_file *file_priv, 612 struct drm_mode_fb_cmd *mode_cmd) 613 { 614 struct drm_gem_object *obj; 615 616 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 617 618 return radeon_framebuffer_create(dev, mode_cmd, obj); 619 } 620 621 static const struct drm_mode_config_funcs radeon_mode_funcs = { 622 .fb_create = radeon_user_framebuffer_create, 623 .fb_changed = radeonfb_probe, 624 }; 625 626 struct drm_prop_enum_list { 627 int type; 628 char *name; 629 }; 630 631 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 632 { { 0, "driver" }, 633 { 1, "bios" }, 634 }; 635 636 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 637 { { TV_STD_NTSC, "ntsc" }, 638 { TV_STD_PAL, "pal" }, 639 { TV_STD_PAL_M, "pal-m" }, 640 { TV_STD_PAL_60, "pal-60" }, 641 { TV_STD_NTSC_J, "ntsc-j" }, 642 { TV_STD_SCART_PAL, "scart-pal" }, 643 { TV_STD_PAL_CN, "pal-cn" }, 644 { TV_STD_SECAM, "secam" }, 645 }; 646 647 int radeon_modeset_create_props(struct radeon_device *rdev) 648 { 649 int i, sz; 650 651 if (rdev->is_atom_bios) { 652 rdev->mode_info.coherent_mode_property = 653 drm_property_create(rdev->ddev, 654 DRM_MODE_PROP_RANGE, 655 "coherent", 2); 656 if (!rdev->mode_info.coherent_mode_property) 657 return -ENOMEM; 658 659 rdev->mode_info.coherent_mode_property->values[0] = 0; 660 rdev->mode_info.coherent_mode_property->values[0] = 1; 661 } 662 663 if (!ASIC_IS_AVIVO(rdev)) { 664 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 665 rdev->mode_info.tmds_pll_property = 666 drm_property_create(rdev->ddev, 667 DRM_MODE_PROP_ENUM, 668 "tmds_pll", sz); 669 for (i = 0; i < sz; i++) { 670 drm_property_add_enum(rdev->mode_info.tmds_pll_property, 671 i, 672 radeon_tmds_pll_enum_list[i].type, 673 radeon_tmds_pll_enum_list[i].name); 674 } 675 } 676 677 rdev->mode_info.load_detect_property = 678 drm_property_create(rdev->ddev, 679 DRM_MODE_PROP_RANGE, 680 "load detection", 2); 681 if (!rdev->mode_info.load_detect_property) 682 return -ENOMEM; 683 rdev->mode_info.load_detect_property->values[0] = 0; 684 rdev->mode_info.load_detect_property->values[0] = 1; 685 686 drm_mode_create_scaling_mode_property(rdev->ddev); 687 688 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 689 rdev->mode_info.tv_std_property = 690 drm_property_create(rdev->ddev, 691 DRM_MODE_PROP_ENUM, 692 "tv standard", sz); 693 for (i = 0; i < sz; i++) { 694 drm_property_add_enum(rdev->mode_info.tv_std_property, 695 i, 696 radeon_tv_std_enum_list[i].type, 697 radeon_tv_std_enum_list[i].name); 698 } 699 700 return 0; 701 } 702 703 int radeon_modeset_init(struct radeon_device *rdev) 704 { 705 int num_crtc = 2, i; 706 int ret; 707 708 drm_mode_config_init(rdev->ddev); 709 rdev->mode_info.mode_config_initialized = true; 710 711 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; 712 713 if (ASIC_IS_AVIVO(rdev)) { 714 rdev->ddev->mode_config.max_width = 8192; 715 rdev->ddev->mode_config.max_height = 8192; 716 } else { 717 rdev->ddev->mode_config.max_width = 4096; 718 rdev->ddev->mode_config.max_height = 4096; 719 } 720 721 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 722 723 ret = radeon_modeset_create_props(rdev); 724 if (ret) { 725 return ret; 726 } 727 /* allocate crtcs - TODO single crtc */ 728 for (i = 0; i < num_crtc; i++) { 729 radeon_crtc_init(rdev->ddev, i); 730 } 731 732 /* okay we should have all the bios connectors */ 733 ret = radeon_setup_enc_conn(rdev->ddev); 734 if (!ret) { 735 return ret; 736 } 737 drm_helper_initial_config(rdev->ddev); 738 return 0; 739 } 740 741 void radeon_modeset_fini(struct radeon_device *rdev) 742 { 743 if (rdev->mode_info.mode_config_initialized) { 744 drm_mode_config_cleanup(rdev->ddev); 745 rdev->mode_info.mode_config_initialized = false; 746 } 747 } 748 749 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 750 struct drm_display_mode *mode, 751 struct drm_display_mode *adjusted_mode) 752 { 753 struct drm_device *dev = crtc->dev; 754 struct drm_encoder *encoder; 755 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 756 struct radeon_encoder *radeon_encoder; 757 bool first = true; 758 759 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 760 radeon_encoder = to_radeon_encoder(encoder); 761 if (encoder->crtc != crtc) 762 continue; 763 if (first) { 764 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 765 memcpy(&radeon_crtc->native_mode, 766 &radeon_encoder->native_mode, 767 sizeof(struct radeon_native_mode)); 768 first = false; 769 } else { 770 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 771 /* WARNING: Right now this can't happen but 772 * in the future we need to check that scaling 773 * are consistent accross different encoder 774 * (ie all encoder can work with the same 775 * scaling). 776 */ 777 DRM_ERROR("Scaling not consistent accross encoder.\n"); 778 return false; 779 } 780 } 781 } 782 if (radeon_crtc->rmx_type != RMX_OFF) { 783 fixed20_12 a, b; 784 a.full = rfixed_const(crtc->mode.vdisplay); 785 b.full = rfixed_const(radeon_crtc->native_mode.panel_xres); 786 radeon_crtc->vsc.full = rfixed_div(a, b); 787 a.full = rfixed_const(crtc->mode.hdisplay); 788 b.full = rfixed_const(radeon_crtc->native_mode.panel_yres); 789 radeon_crtc->hsc.full = rfixed_div(a, b); 790 } else { 791 radeon_crtc->vsc.full = rfixed_const(1); 792 radeon_crtc->hsc.full = rfixed_const(1); 793 } 794 return true; 795 } 796