1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "radeon_drm.h" 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include "drm_crtc_helper.h" 34 #include "drm_edid.h" 35 36 static int radeon_ddc_dump(struct drm_connector *connector); 37 38 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 39 { 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 struct drm_device *dev = crtc->dev; 42 struct radeon_device *rdev = dev->dev_private; 43 int i; 44 45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 47 48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 51 52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 55 56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 57 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 59 60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 61 for (i = 0; i < 256; i++) { 62 WREG32(AVIVO_DC_LUT_30_COLOR, 63 (radeon_crtc->lut_r[i] << 20) | 64 (radeon_crtc->lut_g[i] << 10) | 65 (radeon_crtc->lut_b[i] << 0)); 66 } 67 68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 } 70 71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc) 72 { 73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 74 struct drm_device *dev = crtc->dev; 75 struct radeon_device *rdev = dev->dev_private; 76 int i; 77 78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 80 81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 84 85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 88 89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 91 92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 93 for (i = 0; i < 256; i++) { 94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 95 (radeon_crtc->lut_r[i] << 20) | 96 (radeon_crtc->lut_g[i] << 10) | 97 (radeon_crtc->lut_b[i] << 0)); 98 } 99 } 100 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 102 { 103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 104 struct drm_device *dev = crtc->dev; 105 struct radeon_device *rdev = dev->dev_private; 106 int i; 107 uint32_t dac2_cntl; 108 109 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 110 if (radeon_crtc->crtc_id == 0) 111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 112 else 113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 114 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 115 116 WREG8(RADEON_PALETTE_INDEX, 0); 117 for (i = 0; i < 256; i++) { 118 WREG32(RADEON_PALETTE_30_DATA, 119 (radeon_crtc->lut_r[i] << 20) | 120 (radeon_crtc->lut_g[i] << 10) | 121 (radeon_crtc->lut_b[i] << 0)); 122 } 123 } 124 125 void radeon_crtc_load_lut(struct drm_crtc *crtc) 126 { 127 struct drm_device *dev = crtc->dev; 128 struct radeon_device *rdev = dev->dev_private; 129 130 if (!crtc->enabled) 131 return; 132 133 if (ASIC_IS_DCE4(rdev)) 134 evergreen_crtc_load_lut(crtc); 135 else if (ASIC_IS_AVIVO(rdev)) 136 avivo_crtc_load_lut(crtc); 137 else 138 legacy_crtc_load_lut(crtc); 139 } 140 141 /** Sets the color ramps on behalf of fbcon */ 142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 143 u16 blue, int regno) 144 { 145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 146 147 radeon_crtc->lut_r[regno] = red >> 6; 148 radeon_crtc->lut_g[regno] = green >> 6; 149 radeon_crtc->lut_b[regno] = blue >> 6; 150 } 151 152 /** Gets the color ramps on behalf of fbcon */ 153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 154 u16 *blue, int regno) 155 { 156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 157 158 *red = radeon_crtc->lut_r[regno] << 6; 159 *green = radeon_crtc->lut_g[regno] << 6; 160 *blue = radeon_crtc->lut_b[regno] << 6; 161 } 162 163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 164 u16 *blue, uint32_t start, uint32_t size) 165 { 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 167 int end = (start + size > 256) ? 256 : start + size, i; 168 169 /* userspace palettes are always correct as is */ 170 for (i = start; i < end; i++) { 171 radeon_crtc->lut_r[i] = red[i] >> 6; 172 radeon_crtc->lut_g[i] = green[i] >> 6; 173 radeon_crtc->lut_b[i] = blue[i] >> 6; 174 } 175 radeon_crtc_load_lut(crtc); 176 } 177 178 static void radeon_crtc_destroy(struct drm_crtc *crtc) 179 { 180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 181 182 drm_crtc_cleanup(crtc); 183 kfree(radeon_crtc); 184 } 185 186 static const struct drm_crtc_funcs radeon_crtc_funcs = { 187 .cursor_set = radeon_crtc_cursor_set, 188 .cursor_move = radeon_crtc_cursor_move, 189 .gamma_set = radeon_crtc_gamma_set, 190 .set_config = drm_crtc_helper_set_config, 191 .destroy = radeon_crtc_destroy, 192 }; 193 194 static void radeon_crtc_init(struct drm_device *dev, int index) 195 { 196 struct radeon_device *rdev = dev->dev_private; 197 struct radeon_crtc *radeon_crtc; 198 int i; 199 200 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 201 if (radeon_crtc == NULL) 202 return; 203 204 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 205 206 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 207 radeon_crtc->crtc_id = index; 208 rdev->mode_info.crtcs[index] = radeon_crtc; 209 210 #if 0 211 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 212 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 213 radeon_crtc->mode_set.num_connectors = 0; 214 #endif 215 216 for (i = 0; i < 256; i++) { 217 radeon_crtc->lut_r[i] = i << 2; 218 radeon_crtc->lut_g[i] = i << 2; 219 radeon_crtc->lut_b[i] = i << 2; 220 } 221 222 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 223 radeon_atombios_init_crtc(dev, radeon_crtc); 224 else 225 radeon_legacy_init_crtc(dev, radeon_crtc); 226 } 227 228 static const char *encoder_names[34] = { 229 "NONE", 230 "INTERNAL_LVDS", 231 "INTERNAL_TMDS1", 232 "INTERNAL_TMDS2", 233 "INTERNAL_DAC1", 234 "INTERNAL_DAC2", 235 "INTERNAL_SDVOA", 236 "INTERNAL_SDVOB", 237 "SI170B", 238 "CH7303", 239 "CH7301", 240 "INTERNAL_DVO1", 241 "EXTERNAL_SDVOA", 242 "EXTERNAL_SDVOB", 243 "TITFP513", 244 "INTERNAL_LVTM1", 245 "VT1623", 246 "HDMI_SI1930", 247 "HDMI_INTERNAL", 248 "INTERNAL_KLDSCP_TMDS1", 249 "INTERNAL_KLDSCP_DVO1", 250 "INTERNAL_KLDSCP_DAC1", 251 "INTERNAL_KLDSCP_DAC2", 252 "SI178", 253 "MVPU_FPGA", 254 "INTERNAL_DDI", 255 "VT1625", 256 "HDMI_SI1932", 257 "DP_AN9801", 258 "DP_DP501", 259 "INTERNAL_UNIPHY", 260 "INTERNAL_KLDSCP_LVTMA", 261 "INTERNAL_UNIPHY1", 262 "INTERNAL_UNIPHY2", 263 }; 264 265 static const char *connector_names[15] = { 266 "Unknown", 267 "VGA", 268 "DVI-I", 269 "DVI-D", 270 "DVI-A", 271 "Composite", 272 "S-video", 273 "LVDS", 274 "Component", 275 "DIN", 276 "DisplayPort", 277 "HDMI-A", 278 "HDMI-B", 279 "TV", 280 "eDP", 281 }; 282 283 static const char *hpd_names[6] = { 284 "HPD1", 285 "HPD2", 286 "HPD3", 287 "HPD4", 288 "HPD5", 289 "HPD6", 290 }; 291 292 static void radeon_print_display_setup(struct drm_device *dev) 293 { 294 struct drm_connector *connector; 295 struct radeon_connector *radeon_connector; 296 struct drm_encoder *encoder; 297 struct radeon_encoder *radeon_encoder; 298 uint32_t devices; 299 int i = 0; 300 301 DRM_INFO("Radeon Display Connectors\n"); 302 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 303 radeon_connector = to_radeon_connector(connector); 304 DRM_INFO("Connector %d:\n", i); 305 DRM_INFO(" %s\n", connector_names[connector->connector_type]); 306 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 307 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 308 if (radeon_connector->ddc_bus) { 309 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 310 radeon_connector->ddc_bus->rec.mask_clk_reg, 311 radeon_connector->ddc_bus->rec.mask_data_reg, 312 radeon_connector->ddc_bus->rec.a_clk_reg, 313 radeon_connector->ddc_bus->rec.a_data_reg, 314 radeon_connector->ddc_bus->rec.en_clk_reg, 315 radeon_connector->ddc_bus->rec.en_data_reg, 316 radeon_connector->ddc_bus->rec.y_clk_reg, 317 radeon_connector->ddc_bus->rec.y_data_reg); 318 if (radeon_connector->router.ddc_valid) 319 DRM_INFO(" DDC Router 0x%x/0x%x\n", 320 radeon_connector->router.ddc_mux_control_pin, 321 radeon_connector->router.ddc_mux_state); 322 if (radeon_connector->router.cd_valid) 323 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 324 radeon_connector->router.cd_mux_control_pin, 325 radeon_connector->router.cd_mux_state); 326 } else { 327 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 328 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 329 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 330 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 331 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 332 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 333 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 334 } 335 DRM_INFO(" Encoders:\n"); 336 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 337 radeon_encoder = to_radeon_encoder(encoder); 338 devices = radeon_encoder->devices & radeon_connector->devices; 339 if (devices) { 340 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 341 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 342 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 343 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 344 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 345 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 346 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 347 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 348 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 349 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 350 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 351 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 352 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 353 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 354 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 355 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 356 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 357 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 358 if (devices & ATOM_DEVICE_TV1_SUPPORT) 359 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 360 if (devices & ATOM_DEVICE_CV_SUPPORT) 361 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 362 } 363 } 364 i++; 365 } 366 } 367 368 static bool radeon_setup_enc_conn(struct drm_device *dev) 369 { 370 struct radeon_device *rdev = dev->dev_private; 371 struct drm_connector *drm_connector; 372 bool ret = false; 373 374 if (rdev->bios) { 375 if (rdev->is_atom_bios) { 376 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 377 if (ret == false) 378 ret = radeon_get_atom_connector_info_from_object_table(dev); 379 } else { 380 ret = radeon_get_legacy_connector_info_from_bios(dev); 381 if (ret == false) 382 ret = radeon_get_legacy_connector_info_from_table(dev); 383 } 384 } else { 385 if (!ASIC_IS_AVIVO(rdev)) 386 ret = radeon_get_legacy_connector_info_from_table(dev); 387 } 388 if (ret) { 389 radeon_setup_encoder_clones(dev); 390 radeon_print_display_setup(dev); 391 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) 392 radeon_ddc_dump(drm_connector); 393 } 394 395 return ret; 396 } 397 398 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 399 { 400 struct drm_device *dev = radeon_connector->base.dev; 401 struct radeon_device *rdev = dev->dev_private; 402 int ret = 0; 403 404 /* on hw with routers, select right port */ 405 if (radeon_connector->router.ddc_valid) 406 radeon_router_select_ddc_port(radeon_connector); 407 408 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 409 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 410 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 411 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 412 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) 413 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); 414 } 415 if (!radeon_connector->ddc_bus) 416 return -1; 417 if (!radeon_connector->edid) { 418 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 419 } 420 /* some servers provide a hardcoded edid in rom for KVMs */ 421 if (!radeon_connector->edid) 422 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev); 423 if (radeon_connector->edid) { 424 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); 425 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); 426 return ret; 427 } 428 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 429 return 0; 430 } 431 432 static int radeon_ddc_dump(struct drm_connector *connector) 433 { 434 struct edid *edid; 435 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 436 int ret = 0; 437 438 /* on hw with routers, select right port */ 439 if (radeon_connector->router.ddc_valid) 440 radeon_router_select_ddc_port(radeon_connector); 441 442 if (!radeon_connector->ddc_bus) 443 return -1; 444 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); 445 if (edid) { 446 kfree(edid); 447 } 448 return ret; 449 } 450 451 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 452 { 453 uint64_t mod; 454 455 n += d / 2; 456 457 mod = do_div(n, d); 458 return n; 459 } 460 461 void radeon_compute_pll(struct radeon_pll *pll, 462 uint64_t freq, 463 uint32_t *dot_clock_p, 464 uint32_t *fb_div_p, 465 uint32_t *frac_fb_div_p, 466 uint32_t *ref_div_p, 467 uint32_t *post_div_p) 468 { 469 uint32_t min_ref_div = pll->min_ref_div; 470 uint32_t max_ref_div = pll->max_ref_div; 471 uint32_t min_post_div = pll->min_post_div; 472 uint32_t max_post_div = pll->max_post_div; 473 uint32_t min_fractional_feed_div = 0; 474 uint32_t max_fractional_feed_div = 0; 475 uint32_t best_vco = pll->best_vco; 476 uint32_t best_post_div = 1; 477 uint32_t best_ref_div = 1; 478 uint32_t best_feedback_div = 1; 479 uint32_t best_frac_feedback_div = 0; 480 uint32_t best_freq = -1; 481 uint32_t best_error = 0xffffffff; 482 uint32_t best_vco_diff = 1; 483 uint32_t post_div; 484 u32 pll_out_min, pll_out_max; 485 486 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 487 freq = freq * 1000; 488 489 if (pll->flags & RADEON_PLL_IS_LCD) { 490 pll_out_min = pll->lcd_pll_out_min; 491 pll_out_max = pll->lcd_pll_out_max; 492 } else { 493 pll_out_min = pll->pll_out_min; 494 pll_out_max = pll->pll_out_max; 495 } 496 497 if (pll->flags & RADEON_PLL_USE_REF_DIV) 498 min_ref_div = max_ref_div = pll->reference_div; 499 else { 500 while (min_ref_div < max_ref_div-1) { 501 uint32_t mid = (min_ref_div + max_ref_div) / 2; 502 uint32_t pll_in = pll->reference_freq / mid; 503 if (pll_in < pll->pll_in_min) 504 max_ref_div = mid; 505 else if (pll_in > pll->pll_in_max) 506 min_ref_div = mid; 507 else 508 break; 509 } 510 } 511 512 if (pll->flags & RADEON_PLL_USE_POST_DIV) 513 min_post_div = max_post_div = pll->post_div; 514 515 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 516 min_fractional_feed_div = pll->min_frac_feedback_div; 517 max_fractional_feed_div = pll->max_frac_feedback_div; 518 } 519 520 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 521 uint32_t ref_div; 522 523 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 524 continue; 525 526 /* legacy radeons only have a few post_divs */ 527 if (pll->flags & RADEON_PLL_LEGACY) { 528 if ((post_div == 5) || 529 (post_div == 7) || 530 (post_div == 9) || 531 (post_div == 10) || 532 (post_div == 11) || 533 (post_div == 13) || 534 (post_div == 14) || 535 (post_div == 15)) 536 continue; 537 } 538 539 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 540 uint32_t feedback_div, current_freq = 0, error, vco_diff; 541 uint32_t pll_in = pll->reference_freq / ref_div; 542 uint32_t min_feed_div = pll->min_feedback_div; 543 uint32_t max_feed_div = pll->max_feedback_div + 1; 544 545 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 546 continue; 547 548 while (min_feed_div < max_feed_div) { 549 uint32_t vco; 550 uint32_t min_frac_feed_div = min_fractional_feed_div; 551 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 552 uint32_t frac_feedback_div; 553 uint64_t tmp; 554 555 feedback_div = (min_feed_div + max_feed_div) / 2; 556 557 tmp = (uint64_t)pll->reference_freq * feedback_div; 558 vco = radeon_div(tmp, ref_div); 559 560 if (vco < pll_out_min) { 561 min_feed_div = feedback_div + 1; 562 continue; 563 } else if (vco > pll_out_max) { 564 max_feed_div = feedback_div; 565 continue; 566 } 567 568 while (min_frac_feed_div < max_frac_feed_div) { 569 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 570 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 571 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 572 current_freq = radeon_div(tmp, ref_div * post_div); 573 574 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 575 if (freq < current_freq) 576 error = 0xffffffff; 577 else 578 error = freq - current_freq; 579 } else 580 error = abs(current_freq - freq); 581 vco_diff = abs(vco - best_vco); 582 583 if ((best_vco == 0 && error < best_error) || 584 (best_vco != 0 && 585 ((best_error > 100 && error < best_error - 100) || 586 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 587 best_post_div = post_div; 588 best_ref_div = ref_div; 589 best_feedback_div = feedback_div; 590 best_frac_feedback_div = frac_feedback_div; 591 best_freq = current_freq; 592 best_error = error; 593 best_vco_diff = vco_diff; 594 } else if (current_freq == freq) { 595 if (best_freq == -1) { 596 best_post_div = post_div; 597 best_ref_div = ref_div; 598 best_feedback_div = feedback_div; 599 best_frac_feedback_div = frac_feedback_div; 600 best_freq = current_freq; 601 best_error = error; 602 best_vco_diff = vco_diff; 603 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 604 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 605 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 606 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 607 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 608 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 609 best_post_div = post_div; 610 best_ref_div = ref_div; 611 best_feedback_div = feedback_div; 612 best_frac_feedback_div = frac_feedback_div; 613 best_freq = current_freq; 614 best_error = error; 615 best_vco_diff = vco_diff; 616 } 617 } 618 if (current_freq < freq) 619 min_frac_feed_div = frac_feedback_div + 1; 620 else 621 max_frac_feed_div = frac_feedback_div; 622 } 623 if (current_freq < freq) 624 min_feed_div = feedback_div + 1; 625 else 626 max_feed_div = feedback_div; 627 } 628 } 629 } 630 631 *dot_clock_p = best_freq / 10000; 632 *fb_div_p = best_feedback_div; 633 *frac_fb_div_p = best_frac_feedback_div; 634 *ref_div_p = best_ref_div; 635 *post_div_p = best_post_div; 636 } 637 638 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 639 { 640 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 641 642 if (radeon_fb->obj) { 643 drm_gem_object_unreference_unlocked(radeon_fb->obj); 644 } 645 drm_framebuffer_cleanup(fb); 646 kfree(radeon_fb); 647 } 648 649 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 650 struct drm_file *file_priv, 651 unsigned int *handle) 652 { 653 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 654 655 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 656 } 657 658 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 659 .destroy = radeon_user_framebuffer_destroy, 660 .create_handle = radeon_user_framebuffer_create_handle, 661 }; 662 663 void 664 radeon_framebuffer_init(struct drm_device *dev, 665 struct radeon_framebuffer *rfb, 666 struct drm_mode_fb_cmd *mode_cmd, 667 struct drm_gem_object *obj) 668 { 669 rfb->obj = obj; 670 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 671 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 672 } 673 674 static struct drm_framebuffer * 675 radeon_user_framebuffer_create(struct drm_device *dev, 676 struct drm_file *file_priv, 677 struct drm_mode_fb_cmd *mode_cmd) 678 { 679 struct drm_gem_object *obj; 680 struct radeon_framebuffer *radeon_fb; 681 682 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 683 if (obj == NULL) { 684 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 685 "can't create framebuffer\n", mode_cmd->handle); 686 return ERR_PTR(-ENOENT); 687 } 688 689 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 690 if (radeon_fb == NULL) 691 return ERR_PTR(-ENOMEM); 692 693 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 694 695 return &radeon_fb->base; 696 } 697 698 static void radeon_output_poll_changed(struct drm_device *dev) 699 { 700 struct radeon_device *rdev = dev->dev_private; 701 radeon_fb_output_poll_changed(rdev); 702 } 703 704 static const struct drm_mode_config_funcs radeon_mode_funcs = { 705 .fb_create = radeon_user_framebuffer_create, 706 .output_poll_changed = radeon_output_poll_changed 707 }; 708 709 struct drm_prop_enum_list { 710 int type; 711 char *name; 712 }; 713 714 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 715 { { 0, "driver" }, 716 { 1, "bios" }, 717 }; 718 719 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 720 { { TV_STD_NTSC, "ntsc" }, 721 { TV_STD_PAL, "pal" }, 722 { TV_STD_PAL_M, "pal-m" }, 723 { TV_STD_PAL_60, "pal-60" }, 724 { TV_STD_NTSC_J, "ntsc-j" }, 725 { TV_STD_SCART_PAL, "scart-pal" }, 726 { TV_STD_PAL_CN, "pal-cn" }, 727 { TV_STD_SECAM, "secam" }, 728 }; 729 730 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 731 { { UNDERSCAN_OFF, "off" }, 732 { UNDERSCAN_ON, "on" }, 733 { UNDERSCAN_AUTO, "auto" }, 734 }; 735 736 static int radeon_modeset_create_props(struct radeon_device *rdev) 737 { 738 int i, sz; 739 740 if (rdev->is_atom_bios) { 741 rdev->mode_info.coherent_mode_property = 742 drm_property_create(rdev->ddev, 743 DRM_MODE_PROP_RANGE, 744 "coherent", 2); 745 if (!rdev->mode_info.coherent_mode_property) 746 return -ENOMEM; 747 748 rdev->mode_info.coherent_mode_property->values[0] = 0; 749 rdev->mode_info.coherent_mode_property->values[1] = 1; 750 } 751 752 if (!ASIC_IS_AVIVO(rdev)) { 753 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 754 rdev->mode_info.tmds_pll_property = 755 drm_property_create(rdev->ddev, 756 DRM_MODE_PROP_ENUM, 757 "tmds_pll", sz); 758 for (i = 0; i < sz; i++) { 759 drm_property_add_enum(rdev->mode_info.tmds_pll_property, 760 i, 761 radeon_tmds_pll_enum_list[i].type, 762 radeon_tmds_pll_enum_list[i].name); 763 } 764 } 765 766 rdev->mode_info.load_detect_property = 767 drm_property_create(rdev->ddev, 768 DRM_MODE_PROP_RANGE, 769 "load detection", 2); 770 if (!rdev->mode_info.load_detect_property) 771 return -ENOMEM; 772 rdev->mode_info.load_detect_property->values[0] = 0; 773 rdev->mode_info.load_detect_property->values[1] = 1; 774 775 drm_mode_create_scaling_mode_property(rdev->ddev); 776 777 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 778 rdev->mode_info.tv_std_property = 779 drm_property_create(rdev->ddev, 780 DRM_MODE_PROP_ENUM, 781 "tv standard", sz); 782 for (i = 0; i < sz; i++) { 783 drm_property_add_enum(rdev->mode_info.tv_std_property, 784 i, 785 radeon_tv_std_enum_list[i].type, 786 radeon_tv_std_enum_list[i].name); 787 } 788 789 sz = ARRAY_SIZE(radeon_underscan_enum_list); 790 rdev->mode_info.underscan_property = 791 drm_property_create(rdev->ddev, 792 DRM_MODE_PROP_ENUM, 793 "underscan", sz); 794 for (i = 0; i < sz; i++) { 795 drm_property_add_enum(rdev->mode_info.underscan_property, 796 i, 797 radeon_underscan_enum_list[i].type, 798 radeon_underscan_enum_list[i].name); 799 } 800 801 rdev->mode_info.underscan_hborder_property = 802 drm_property_create(rdev->ddev, 803 DRM_MODE_PROP_RANGE, 804 "underscan hborder", 2); 805 if (!rdev->mode_info.underscan_hborder_property) 806 return -ENOMEM; 807 rdev->mode_info.underscan_hborder_property->values[0] = 0; 808 rdev->mode_info.underscan_hborder_property->values[1] = 128; 809 810 rdev->mode_info.underscan_vborder_property = 811 drm_property_create(rdev->ddev, 812 DRM_MODE_PROP_RANGE, 813 "underscan vborder", 2); 814 if (!rdev->mode_info.underscan_vborder_property) 815 return -ENOMEM; 816 rdev->mode_info.underscan_vborder_property->values[0] = 0; 817 rdev->mode_info.underscan_vborder_property->values[1] = 128; 818 819 return 0; 820 } 821 822 void radeon_update_display_priority(struct radeon_device *rdev) 823 { 824 /* adjustment options for the display watermarks */ 825 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 826 /* set display priority to high for r3xx, rv515 chips 827 * this avoids flickering due to underflow to the 828 * display controllers during heavy acceleration. 829 * Don't force high on rs4xx igp chips as it seems to 830 * affect the sound card. See kernel bug 15982. 831 */ 832 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 833 !(rdev->flags & RADEON_IS_IGP)) 834 rdev->disp_priority = 2; 835 else 836 rdev->disp_priority = 0; 837 } else 838 rdev->disp_priority = radeon_disp_priority; 839 840 } 841 842 int radeon_modeset_init(struct radeon_device *rdev) 843 { 844 int i; 845 int ret; 846 847 drm_mode_config_init(rdev->ddev); 848 rdev->mode_info.mode_config_initialized = true; 849 850 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; 851 852 if (ASIC_IS_AVIVO(rdev)) { 853 rdev->ddev->mode_config.max_width = 8192; 854 rdev->ddev->mode_config.max_height = 8192; 855 } else { 856 rdev->ddev->mode_config.max_width = 4096; 857 rdev->ddev->mode_config.max_height = 4096; 858 } 859 860 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 861 862 ret = radeon_modeset_create_props(rdev); 863 if (ret) { 864 return ret; 865 } 866 867 /* init i2c buses */ 868 radeon_i2c_init(rdev); 869 870 /* check combios for a valid hardcoded EDID - Sun servers */ 871 if (!rdev->is_atom_bios) { 872 /* check for hardcoded EDID in BIOS */ 873 radeon_combios_check_hardcoded_edid(rdev); 874 } 875 876 /* allocate crtcs */ 877 for (i = 0; i < rdev->num_crtc; i++) { 878 radeon_crtc_init(rdev->ddev, i); 879 } 880 881 /* okay we should have all the bios connectors */ 882 ret = radeon_setup_enc_conn(rdev->ddev); 883 if (!ret) { 884 return ret; 885 } 886 /* initialize hpd */ 887 radeon_hpd_init(rdev); 888 889 /* Initialize power management */ 890 radeon_pm_init(rdev); 891 892 radeon_fbdev_init(rdev); 893 drm_kms_helper_poll_init(rdev->ddev); 894 895 return 0; 896 } 897 898 void radeon_modeset_fini(struct radeon_device *rdev) 899 { 900 radeon_fbdev_fini(rdev); 901 kfree(rdev->mode_info.bios_hardcoded_edid); 902 radeon_pm_fini(rdev); 903 904 if (rdev->mode_info.mode_config_initialized) { 905 drm_kms_helper_poll_fini(rdev->ddev); 906 radeon_hpd_fini(rdev); 907 drm_mode_config_cleanup(rdev->ddev); 908 rdev->mode_info.mode_config_initialized = false; 909 } 910 /* free i2c buses */ 911 radeon_i2c_fini(rdev); 912 } 913 914 static bool is_hdtv_mode(struct drm_display_mode *mode) 915 { 916 /* try and guess if this is a tv or a monitor */ 917 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 918 (mode->vdisplay == 576) || /* 576p */ 919 (mode->vdisplay == 720) || /* 720p */ 920 (mode->vdisplay == 1080)) /* 1080p */ 921 return true; 922 else 923 return false; 924 } 925 926 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 927 struct drm_display_mode *mode, 928 struct drm_display_mode *adjusted_mode) 929 { 930 struct drm_device *dev = crtc->dev; 931 struct radeon_device *rdev = dev->dev_private; 932 struct drm_encoder *encoder; 933 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 934 struct radeon_encoder *radeon_encoder; 935 struct drm_connector *connector; 936 struct radeon_connector *radeon_connector; 937 bool first = true; 938 u32 src_v = 1, dst_v = 1; 939 u32 src_h = 1, dst_h = 1; 940 941 radeon_crtc->h_border = 0; 942 radeon_crtc->v_border = 0; 943 944 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 945 if (encoder->crtc != crtc) 946 continue; 947 radeon_encoder = to_radeon_encoder(encoder); 948 connector = radeon_get_connector_for_encoder(encoder); 949 radeon_connector = to_radeon_connector(connector); 950 951 if (first) { 952 /* set scaling */ 953 if (radeon_encoder->rmx_type == RMX_OFF) 954 radeon_crtc->rmx_type = RMX_OFF; 955 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 956 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 957 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 958 else 959 radeon_crtc->rmx_type = RMX_OFF; 960 /* copy native mode */ 961 memcpy(&radeon_crtc->native_mode, 962 &radeon_encoder->native_mode, 963 sizeof(struct drm_display_mode)); 964 src_v = crtc->mode.vdisplay; 965 dst_v = radeon_crtc->native_mode.vdisplay; 966 src_h = crtc->mode.hdisplay; 967 dst_h = radeon_crtc->native_mode.hdisplay; 968 969 /* fix up for overscan on hdmi */ 970 if (ASIC_IS_AVIVO(rdev) && 971 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 972 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 973 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 974 drm_detect_hdmi_monitor(radeon_connector->edid) && 975 is_hdtv_mode(mode)))) { 976 if (radeon_encoder->underscan_hborder != 0) 977 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 978 else 979 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 980 if (radeon_encoder->underscan_vborder != 0) 981 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 982 else 983 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 984 radeon_crtc->rmx_type = RMX_FULL; 985 src_v = crtc->mode.vdisplay; 986 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 987 src_h = crtc->mode.hdisplay; 988 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 989 } 990 first = false; 991 } else { 992 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 993 /* WARNING: Right now this can't happen but 994 * in the future we need to check that scaling 995 * are consistent across different encoder 996 * (ie all encoder can work with the same 997 * scaling). 998 */ 999 DRM_ERROR("Scaling not consistent across encoder.\n"); 1000 return false; 1001 } 1002 } 1003 } 1004 if (radeon_crtc->rmx_type != RMX_OFF) { 1005 fixed20_12 a, b; 1006 a.full = dfixed_const(src_v); 1007 b.full = dfixed_const(dst_v); 1008 radeon_crtc->vsc.full = dfixed_div(a, b); 1009 a.full = dfixed_const(src_h); 1010 b.full = dfixed_const(dst_h); 1011 radeon_crtc->hsc.full = dfixed_div(a, b); 1012 } else { 1013 radeon_crtc->vsc.full = dfixed_const(1); 1014 radeon_crtc->hsc.full = dfixed_const(1); 1015 } 1016 return true; 1017 } 1018 1019 /* 1020 * Retrieve current video scanout position of crtc on a given gpu. 1021 * 1022 * \param rdev Device to query. 1023 * \param crtc Crtc to query. 1024 * \param *vpos Location where vertical scanout position should be stored. 1025 * \param *hpos Location where horizontal scanout position should go. 1026 * 1027 * Returns vpos as a positive number while in active scanout area. 1028 * Returns vpos as a negative number inside vblank, counting the number 1029 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1030 * until start of active scanout / end of vblank." 1031 * 1032 * \return Flags, or'ed together as follows: 1033 * 1034 * RADEON_SCANOUTPOS_VALID = Query successfull. 1035 * RADEON_SCANOUTPOS_INVBL = Inside vblank. 1036 * RADEON_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1037 * this flag means that returned position may be offset by a constant but 1038 * unknown small number of scanlines wrt. real scanout position. 1039 * 1040 */ 1041 int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos) 1042 { 1043 u32 stat_crtc = 0, vbl = 0, position = 0; 1044 int vbl_start, vbl_end, vtotal, ret = 0; 1045 bool in_vbl = true; 1046 1047 if (ASIC_IS_DCE4(rdev)) { 1048 if (crtc == 0) { 1049 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1050 EVERGREEN_CRTC0_REGISTER_OFFSET); 1051 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1052 EVERGREEN_CRTC0_REGISTER_OFFSET); 1053 ret |= RADEON_SCANOUTPOS_VALID; 1054 } 1055 if (crtc == 1) { 1056 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1057 EVERGREEN_CRTC1_REGISTER_OFFSET); 1058 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1059 EVERGREEN_CRTC1_REGISTER_OFFSET); 1060 ret |= RADEON_SCANOUTPOS_VALID; 1061 } 1062 if (crtc == 2) { 1063 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1064 EVERGREEN_CRTC2_REGISTER_OFFSET); 1065 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1066 EVERGREEN_CRTC2_REGISTER_OFFSET); 1067 ret |= RADEON_SCANOUTPOS_VALID; 1068 } 1069 if (crtc == 3) { 1070 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1071 EVERGREEN_CRTC3_REGISTER_OFFSET); 1072 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1073 EVERGREEN_CRTC3_REGISTER_OFFSET); 1074 ret |= RADEON_SCANOUTPOS_VALID; 1075 } 1076 if (crtc == 4) { 1077 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1078 EVERGREEN_CRTC4_REGISTER_OFFSET); 1079 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1080 EVERGREEN_CRTC4_REGISTER_OFFSET); 1081 ret |= RADEON_SCANOUTPOS_VALID; 1082 } 1083 if (crtc == 5) { 1084 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1085 EVERGREEN_CRTC5_REGISTER_OFFSET); 1086 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1087 EVERGREEN_CRTC5_REGISTER_OFFSET); 1088 ret |= RADEON_SCANOUTPOS_VALID; 1089 } 1090 } else if (ASIC_IS_AVIVO(rdev)) { 1091 if (crtc == 0) { 1092 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1093 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1094 ret |= RADEON_SCANOUTPOS_VALID; 1095 } 1096 if (crtc == 1) { 1097 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1098 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1099 ret |= RADEON_SCANOUTPOS_VALID; 1100 } 1101 } else { 1102 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1103 if (crtc == 0) { 1104 /* Assume vbl_end == 0, get vbl_start from 1105 * upper 16 bits. 1106 */ 1107 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1108 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1109 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1110 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1111 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1112 if (!(stat_crtc & 1)) 1113 in_vbl = false; 1114 1115 ret |= RADEON_SCANOUTPOS_VALID; 1116 } 1117 if (crtc == 1) { 1118 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1119 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1120 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1121 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1122 if (!(stat_crtc & 1)) 1123 in_vbl = false; 1124 1125 ret |= RADEON_SCANOUTPOS_VALID; 1126 } 1127 } 1128 1129 /* Decode into vertical and horizontal scanout position. */ 1130 *vpos = position & 0x1fff; 1131 *hpos = (position >> 16) & 0x1fff; 1132 1133 /* Valid vblank area boundaries from gpu retrieved? */ 1134 if (vbl > 0) { 1135 /* Yes: Decode. */ 1136 ret |= RADEON_SCANOUTPOS_ACCURATE; 1137 vbl_start = vbl & 0x1fff; 1138 vbl_end = (vbl >> 16) & 0x1fff; 1139 } 1140 else { 1141 /* No: Fake something reasonable which gives at least ok results. */ 1142 vbl_start = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vdisplay; 1143 vbl_end = 0; 1144 } 1145 1146 /* Test scanout position against vblank region. */ 1147 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1148 in_vbl = false; 1149 1150 /* Check if inside vblank area and apply corrective offsets: 1151 * vpos will then be >=0 in video scanout area, but negative 1152 * within vblank area, counting down the number of lines until 1153 * start of scanout. 1154 */ 1155 1156 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1157 if (in_vbl && (*vpos >= vbl_start)) { 1158 vtotal = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vtotal; 1159 *vpos = *vpos - vtotal; 1160 } 1161 1162 /* Correct for shifted end of vbl at vbl_end. */ 1163 *vpos = *vpos - vbl_end; 1164 1165 /* In vblank? */ 1166 if (in_vbl) 1167 ret |= RADEON_SCANOUTPOS_INVBL; 1168 1169 return ret; 1170 } 1171