1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/pci.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/gcd.h> 30 31 #include <asm/div64.h> 32 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_device.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_gem_framebuffer_helper.h> 40 #include <drm/drm_plane_helper.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/drm_vblank.h> 43 #include <drm/radeon_drm.h> 44 45 #include "atom.h" 46 #include "radeon.h" 47 48 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc); 49 int radeon_enable_vblank_kms(struct drm_crtc *crtc); 50 void radeon_disable_vblank_kms(struct drm_crtc *crtc); 51 52 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 53 { 54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 55 struct drm_device *dev = crtc->dev; 56 struct radeon_device *rdev = dev->dev_private; 57 u16 *r, *g, *b; 58 int i; 59 60 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 61 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 62 63 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 64 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 65 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 66 67 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 68 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 69 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 70 71 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 72 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 73 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 74 75 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 76 r = crtc->gamma_store; 77 g = r + crtc->gamma_size; 78 b = g + crtc->gamma_size; 79 for (i = 0; i < 256; i++) { 80 WREG32(AVIVO_DC_LUT_30_COLOR, 81 ((*r++ & 0xffc0) << 14) | 82 ((*g++ & 0xffc0) << 4) | 83 (*b++ >> 6)); 84 } 85 86 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 87 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 88 } 89 90 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 91 { 92 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 93 struct drm_device *dev = crtc->dev; 94 struct radeon_device *rdev = dev->dev_private; 95 u16 *r, *g, *b; 96 int i; 97 98 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 99 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 100 101 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 102 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 103 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 104 105 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 106 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 107 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 108 109 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 110 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 111 112 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 113 r = crtc->gamma_store; 114 g = r + crtc->gamma_size; 115 b = g + crtc->gamma_size; 116 for (i = 0; i < 256; i++) { 117 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 118 ((*r++ & 0xffc0) << 14) | 119 ((*g++ & 0xffc0) << 4) | 120 (*b++ >> 6)); 121 } 122 } 123 124 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 125 { 126 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 127 struct drm_device *dev = crtc->dev; 128 struct radeon_device *rdev = dev->dev_private; 129 u16 *r, *g, *b; 130 int i; 131 132 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 133 134 msleep(10); 135 136 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 137 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 138 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 139 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 140 NI_GRPH_PRESCALE_BYPASS); 141 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 142 NI_OVL_PRESCALE_BYPASS); 143 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 144 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 145 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 146 147 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 148 149 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 150 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 151 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 152 153 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 154 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 155 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 156 157 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 158 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 159 160 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 161 r = crtc->gamma_store; 162 g = r + crtc->gamma_size; 163 b = g + crtc->gamma_size; 164 for (i = 0; i < 256; i++) { 165 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 166 ((*r++ & 0xffc0) << 14) | 167 ((*g++ & 0xffc0) << 4) | 168 (*b++ >> 6)); 169 } 170 171 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 172 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 173 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 174 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 175 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 176 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 177 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 178 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 179 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 180 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 181 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 182 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 183 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 184 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 185 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 186 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 187 if (ASIC_IS_DCE8(rdev)) { 188 /* XXX this only needs to be programmed once per crtc at startup, 189 * not sure where the best place for it is 190 */ 191 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 192 CIK_CURSOR_ALPHA_BLND_ENA); 193 } 194 } 195 196 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 197 { 198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 199 struct drm_device *dev = crtc->dev; 200 struct radeon_device *rdev = dev->dev_private; 201 u16 *r, *g, *b; 202 int i; 203 uint32_t dac2_cntl; 204 205 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 206 if (radeon_crtc->crtc_id == 0) 207 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 208 else 209 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 210 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 211 212 WREG8(RADEON_PALETTE_INDEX, 0); 213 r = crtc->gamma_store; 214 g = r + crtc->gamma_size; 215 b = g + crtc->gamma_size; 216 for (i = 0; i < 256; i++) { 217 WREG32(RADEON_PALETTE_30_DATA, 218 ((*r++ & 0xffc0) << 14) | 219 ((*g++ & 0xffc0) << 4) | 220 (*b++ >> 6)); 221 } 222 } 223 224 void radeon_crtc_load_lut(struct drm_crtc *crtc) 225 { 226 struct drm_device *dev = crtc->dev; 227 struct radeon_device *rdev = dev->dev_private; 228 229 if (!crtc->enabled) 230 return; 231 232 if (ASIC_IS_DCE5(rdev)) 233 dce5_crtc_load_lut(crtc); 234 else if (ASIC_IS_DCE4(rdev)) 235 dce4_crtc_load_lut(crtc); 236 else if (ASIC_IS_AVIVO(rdev)) 237 avivo_crtc_load_lut(crtc); 238 else 239 legacy_crtc_load_lut(crtc); 240 } 241 242 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 243 u16 *blue, uint32_t size, 244 struct drm_modeset_acquire_ctx *ctx) 245 { 246 radeon_crtc_load_lut(crtc); 247 248 return 0; 249 } 250 251 static void radeon_crtc_destroy(struct drm_crtc *crtc) 252 { 253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 254 255 drm_crtc_cleanup(crtc); 256 destroy_workqueue(radeon_crtc->flip_queue); 257 kfree(radeon_crtc); 258 } 259 260 /** 261 * radeon_unpin_work_func - unpin old buffer object 262 * 263 * @__work - kernel work item 264 * 265 * Unpin the old frame buffer object outside of the interrupt handler 266 */ 267 static void radeon_unpin_work_func(struct work_struct *__work) 268 { 269 struct radeon_flip_work *work = 270 container_of(__work, struct radeon_flip_work, unpin_work); 271 int r; 272 273 /* unpin of the old buffer */ 274 r = radeon_bo_reserve(work->old_rbo, false); 275 if (likely(r == 0)) { 276 r = radeon_bo_unpin(work->old_rbo); 277 if (unlikely(r != 0)) { 278 DRM_ERROR("failed to unpin buffer after flip\n"); 279 } 280 radeon_bo_unreserve(work->old_rbo); 281 } else 282 DRM_ERROR("failed to reserve buffer after flip\n"); 283 284 drm_gem_object_put_unlocked(&work->old_rbo->tbo.base); 285 kfree(work); 286 } 287 288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 289 { 290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 291 unsigned long flags; 292 u32 update_pending; 293 int vpos, hpos; 294 295 /* can happen during initialization */ 296 if (radeon_crtc == NULL) 297 return; 298 299 /* Skip the pageflip completion check below (based on polling) on 300 * asics which reliably support hw pageflip completion irqs. pflip 301 * irqs are a reliable and race-free method of handling pageflip 302 * completion detection. A use_pflipirq module parameter < 2 allows 303 * to override this in case of asics with faulty pflip irqs. 304 * A module parameter of 0 would only use this polling based path, 305 * a parameter of 1 would use pflip irq only as a backup to this 306 * path, as in Linux 3.16. 307 */ 308 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 309 return; 310 311 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 312 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 314 "RADEON_FLIP_SUBMITTED(%d)\n", 315 radeon_crtc->flip_status, 316 RADEON_FLIP_SUBMITTED); 317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 318 return; 319 } 320 321 update_pending = radeon_page_flip_pending(rdev, crtc_id); 322 323 /* Has the pageflip already completed in crtc, or is it certain 324 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 325 * distance to start of "fudged earlier" vblank in vpos, distance to 326 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 327 * the last few scanlines before start of real vblank, where the vblank 328 * irq can fire, so we have sampled update_pending a bit too early and 329 * know the flip will complete at leading edge of the upcoming real 330 * vblank. On pre-AVIVO hardware, flips also complete inside the real 331 * vblank, not only at leading edge, so if update_pending for hpos >= 0 332 * == inside real vblank, the flip will complete almost immediately. 333 * Note that this method of completion handling is still not 100% race 334 * free, as we could execute before the radeon_flip_work_func managed 335 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 336 * but the flip still gets programmed into hw and completed during 337 * vblank, leading to a delayed emission of the flip completion event. 338 * This applies at least to pre-AVIVO hardware, where flips are always 339 * completing inside vblank, not only at leading edge of vblank. 340 */ 341 if (update_pending && 342 (DRM_SCANOUTPOS_VALID & 343 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 344 GET_DISTANCE_TO_VBLANKSTART, 345 &vpos, &hpos, NULL, NULL, 346 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 347 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 348 /* crtc didn't flip in this target vblank interval, 349 * but flip is pending in crtc. Based on the current 350 * scanout position we know that the current frame is 351 * (nearly) complete and the flip will (likely) 352 * complete before the start of the next frame. 353 */ 354 update_pending = 0; 355 } 356 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 357 if (!update_pending) 358 radeon_crtc_handle_flip(rdev, crtc_id); 359 } 360 361 /** 362 * radeon_crtc_handle_flip - page flip completed 363 * 364 * @rdev: radeon device pointer 365 * @crtc_id: crtc number this event is for 366 * 367 * Called when we are sure that a page flip for this crtc is completed. 368 */ 369 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 370 { 371 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 372 struct radeon_flip_work *work; 373 unsigned long flags; 374 375 /* this can happen at init */ 376 if (radeon_crtc == NULL) 377 return; 378 379 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 380 work = radeon_crtc->flip_work; 381 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 382 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 383 "RADEON_FLIP_SUBMITTED(%d)\n", 384 radeon_crtc->flip_status, 385 RADEON_FLIP_SUBMITTED); 386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 387 return; 388 } 389 390 /* Pageflip completed. Clean up. */ 391 radeon_crtc->flip_status = RADEON_FLIP_NONE; 392 radeon_crtc->flip_work = NULL; 393 394 /* wakeup userspace */ 395 if (work->event) 396 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 397 398 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 399 400 drm_crtc_vblank_put(&radeon_crtc->base); 401 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 402 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 403 } 404 405 /** 406 * radeon_flip_work_func - page flip framebuffer 407 * 408 * @work - kernel work item 409 * 410 * Wait for the buffer object to become idle and do the actual page flip 411 */ 412 static void radeon_flip_work_func(struct work_struct *__work) 413 { 414 struct radeon_flip_work *work = 415 container_of(__work, struct radeon_flip_work, flip_work); 416 struct radeon_device *rdev = work->rdev; 417 struct drm_device *dev = rdev->ddev; 418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 419 420 struct drm_crtc *crtc = &radeon_crtc->base; 421 unsigned long flags; 422 int r; 423 int vpos, hpos; 424 425 down_read(&rdev->exclusive_lock); 426 if (work->fence) { 427 struct radeon_fence *fence; 428 429 fence = to_radeon_fence(work->fence); 430 if (fence && fence->rdev == rdev) { 431 r = radeon_fence_wait(fence, false); 432 if (r == -EDEADLK) { 433 up_read(&rdev->exclusive_lock); 434 do { 435 r = radeon_gpu_reset(rdev); 436 } while (r == -EAGAIN); 437 down_read(&rdev->exclusive_lock); 438 } 439 } else 440 r = dma_fence_wait(work->fence, false); 441 442 if (r) 443 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 444 445 /* We continue with the page flip even if we failed to wait on 446 * the fence, otherwise the DRM core and userspace will be 447 * confused about which BO the CRTC is scanning out 448 */ 449 450 dma_fence_put(work->fence); 451 work->fence = NULL; 452 } 453 454 /* Wait until we're out of the vertical blank period before the one 455 * targeted by the flip. Always wait on pre DCE4 to avoid races with 456 * flip completion handling from vblank irq, as these old asics don't 457 * have reliable pageflip completion interrupts. 458 */ 459 while (radeon_crtc->enabled && 460 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 461 &vpos, &hpos, NULL, NULL, 462 &crtc->hwmode) 463 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 464 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 465 (!ASIC_IS_AVIVO(rdev) || 466 ((int) (work->target_vblank - 467 crtc->funcs->get_vblank_counter(crtc)) > 0))) 468 usleep_range(1000, 2000); 469 470 /* We borrow the event spin lock for protecting flip_status */ 471 spin_lock_irqsave(&crtc->dev->event_lock, flags); 472 473 /* set the proper interrupt */ 474 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 475 476 /* do the flip (mmio) */ 477 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 478 479 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 481 up_read(&rdev->exclusive_lock); 482 } 483 484 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 485 struct drm_framebuffer *fb, 486 struct drm_pending_vblank_event *event, 487 uint32_t page_flip_flags, 488 uint32_t target, 489 struct drm_modeset_acquire_ctx *ctx) 490 { 491 struct drm_device *dev = crtc->dev; 492 struct radeon_device *rdev = dev->dev_private; 493 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 494 struct drm_gem_object *obj; 495 struct radeon_flip_work *work; 496 struct radeon_bo *new_rbo; 497 uint32_t tiling_flags, pitch_pixels; 498 uint64_t base; 499 unsigned long flags; 500 int r; 501 502 work = kzalloc(sizeof *work, GFP_KERNEL); 503 if (work == NULL) 504 return -ENOMEM; 505 506 INIT_WORK(&work->flip_work, radeon_flip_work_func); 507 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 508 509 work->rdev = rdev; 510 work->crtc_id = radeon_crtc->crtc_id; 511 work->event = event; 512 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 513 514 /* schedule unpin of the old buffer */ 515 obj = crtc->primary->fb->obj[0]; 516 517 /* take a reference to the old object */ 518 drm_gem_object_get(obj); 519 work->old_rbo = gem_to_radeon_bo(obj); 520 521 obj = fb->obj[0]; 522 new_rbo = gem_to_radeon_bo(obj); 523 524 /* pin the new buffer */ 525 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 526 work->old_rbo, new_rbo); 527 528 r = radeon_bo_reserve(new_rbo, false); 529 if (unlikely(r != 0)) { 530 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 531 goto cleanup; 532 } 533 /* Only 27 bit offset for legacy CRTC */ 534 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 535 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 536 if (unlikely(r != 0)) { 537 radeon_bo_unreserve(new_rbo); 538 r = -EINVAL; 539 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 540 goto cleanup; 541 } 542 work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv)); 543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 544 radeon_bo_unreserve(new_rbo); 545 546 if (!ASIC_IS_AVIVO(rdev)) { 547 /* crtc offset is from display base addr not FB location */ 548 base -= radeon_crtc->legacy_display_base_addr; 549 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 550 551 if (tiling_flags & RADEON_TILING_MACRO) { 552 if (ASIC_IS_R300(rdev)) { 553 base &= ~0x7ff; 554 } else { 555 int byteshift = fb->format->cpp[0] * 8 >> 4; 556 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 557 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 558 } 559 } else { 560 int offset = crtc->y * pitch_pixels + crtc->x; 561 switch (fb->format->cpp[0] * 8) { 562 case 8: 563 default: 564 offset *= 1; 565 break; 566 case 15: 567 case 16: 568 offset *= 2; 569 break; 570 case 24: 571 offset *= 3; 572 break; 573 case 32: 574 offset *= 4; 575 break; 576 } 577 base += offset; 578 } 579 base &= ~7; 580 } 581 work->base = base; 582 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 583 crtc->funcs->get_vblank_counter(crtc); 584 585 /* We borrow the event spin lock for protecting flip_work */ 586 spin_lock_irqsave(&crtc->dev->event_lock, flags); 587 588 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 589 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 590 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 591 r = -EBUSY; 592 goto pflip_cleanup; 593 } 594 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 595 radeon_crtc->flip_work = work; 596 597 /* update crtc fb */ 598 crtc->primary->fb = fb; 599 600 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 601 602 queue_work(radeon_crtc->flip_queue, &work->flip_work); 603 return 0; 604 605 pflip_cleanup: 606 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 607 DRM_ERROR("failed to reserve new rbo in error path\n"); 608 goto cleanup; 609 } 610 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 611 DRM_ERROR("failed to unpin new rbo in error path\n"); 612 } 613 radeon_bo_unreserve(new_rbo); 614 615 cleanup: 616 drm_gem_object_put_unlocked(&work->old_rbo->tbo.base); 617 dma_fence_put(work->fence); 618 kfree(work); 619 return r; 620 } 621 622 static int 623 radeon_crtc_set_config(struct drm_mode_set *set, 624 struct drm_modeset_acquire_ctx *ctx) 625 { 626 struct drm_device *dev; 627 struct radeon_device *rdev; 628 struct drm_crtc *crtc; 629 bool active = false; 630 int ret; 631 632 if (!set || !set->crtc) 633 return -EINVAL; 634 635 dev = set->crtc->dev; 636 637 ret = pm_runtime_get_sync(dev->dev); 638 if (ret < 0) { 639 pm_runtime_put_autosuspend(dev->dev); 640 return ret; 641 } 642 643 ret = drm_crtc_helper_set_config(set, ctx); 644 645 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 646 if (crtc->enabled) 647 active = true; 648 649 pm_runtime_mark_last_busy(dev->dev); 650 651 rdev = dev->dev_private; 652 /* if we have active crtcs and we don't have a power ref, 653 take the current one */ 654 if (active && !rdev->have_disp_power_ref) { 655 rdev->have_disp_power_ref = true; 656 return ret; 657 } 658 /* if we have no active crtcs, then drop the power ref 659 we got before */ 660 if (!active && rdev->have_disp_power_ref) { 661 pm_runtime_put_autosuspend(dev->dev); 662 rdev->have_disp_power_ref = false; 663 } 664 665 /* drop the power reference we got coming in here */ 666 pm_runtime_put_autosuspend(dev->dev); 667 return ret; 668 } 669 670 static const struct drm_crtc_funcs radeon_crtc_funcs = { 671 .cursor_set2 = radeon_crtc_cursor_set2, 672 .cursor_move = radeon_crtc_cursor_move, 673 .gamma_set = radeon_crtc_gamma_set, 674 .set_config = radeon_crtc_set_config, 675 .destroy = radeon_crtc_destroy, 676 .page_flip_target = radeon_crtc_page_flip_target, 677 .get_vblank_counter = radeon_get_vblank_counter_kms, 678 .enable_vblank = radeon_enable_vblank_kms, 679 .disable_vblank = radeon_disable_vblank_kms, 680 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 681 }; 682 683 static void radeon_crtc_init(struct drm_device *dev, int index) 684 { 685 struct radeon_device *rdev = dev->dev_private; 686 struct radeon_crtc *radeon_crtc; 687 688 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 689 if (radeon_crtc == NULL) 690 return; 691 692 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 693 694 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 695 radeon_crtc->crtc_id = index; 696 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 697 rdev->mode_info.crtcs[index] = radeon_crtc; 698 699 if (rdev->family >= CHIP_BONAIRE) { 700 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 701 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 702 } else { 703 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 704 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 705 } 706 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 707 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 708 709 #if 0 710 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 711 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 712 radeon_crtc->mode_set.num_connectors = 0; 713 #endif 714 715 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 716 radeon_atombios_init_crtc(dev, radeon_crtc); 717 else 718 radeon_legacy_init_crtc(dev, radeon_crtc); 719 } 720 721 static const char *encoder_names[38] = { 722 "NONE", 723 "INTERNAL_LVDS", 724 "INTERNAL_TMDS1", 725 "INTERNAL_TMDS2", 726 "INTERNAL_DAC1", 727 "INTERNAL_DAC2", 728 "INTERNAL_SDVOA", 729 "INTERNAL_SDVOB", 730 "SI170B", 731 "CH7303", 732 "CH7301", 733 "INTERNAL_DVO1", 734 "EXTERNAL_SDVOA", 735 "EXTERNAL_SDVOB", 736 "TITFP513", 737 "INTERNAL_LVTM1", 738 "VT1623", 739 "HDMI_SI1930", 740 "HDMI_INTERNAL", 741 "INTERNAL_KLDSCP_TMDS1", 742 "INTERNAL_KLDSCP_DVO1", 743 "INTERNAL_KLDSCP_DAC1", 744 "INTERNAL_KLDSCP_DAC2", 745 "SI178", 746 "MVPU_FPGA", 747 "INTERNAL_DDI", 748 "VT1625", 749 "HDMI_SI1932", 750 "DP_AN9801", 751 "DP_DP501", 752 "INTERNAL_UNIPHY", 753 "INTERNAL_KLDSCP_LVTMA", 754 "INTERNAL_UNIPHY1", 755 "INTERNAL_UNIPHY2", 756 "NUTMEG", 757 "TRAVIS", 758 "INTERNAL_VCE", 759 "INTERNAL_UNIPHY3", 760 }; 761 762 static const char *hpd_names[6] = { 763 "HPD1", 764 "HPD2", 765 "HPD3", 766 "HPD4", 767 "HPD5", 768 "HPD6", 769 }; 770 771 static void radeon_print_display_setup(struct drm_device *dev) 772 { 773 struct drm_connector *connector; 774 struct radeon_connector *radeon_connector; 775 struct drm_encoder *encoder; 776 struct radeon_encoder *radeon_encoder; 777 uint32_t devices; 778 int i = 0; 779 780 DRM_INFO("Radeon Display Connectors\n"); 781 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 782 radeon_connector = to_radeon_connector(connector); 783 DRM_INFO("Connector %d:\n", i); 784 DRM_INFO(" %s\n", connector->name); 785 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 786 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 787 if (radeon_connector->ddc_bus) { 788 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 789 radeon_connector->ddc_bus->rec.mask_clk_reg, 790 radeon_connector->ddc_bus->rec.mask_data_reg, 791 radeon_connector->ddc_bus->rec.a_clk_reg, 792 radeon_connector->ddc_bus->rec.a_data_reg, 793 radeon_connector->ddc_bus->rec.en_clk_reg, 794 radeon_connector->ddc_bus->rec.en_data_reg, 795 radeon_connector->ddc_bus->rec.y_clk_reg, 796 radeon_connector->ddc_bus->rec.y_data_reg); 797 if (radeon_connector->router.ddc_valid) 798 DRM_INFO(" DDC Router 0x%x/0x%x\n", 799 radeon_connector->router.ddc_mux_control_pin, 800 radeon_connector->router.ddc_mux_state); 801 if (radeon_connector->router.cd_valid) 802 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 803 radeon_connector->router.cd_mux_control_pin, 804 radeon_connector->router.cd_mux_state); 805 } else { 806 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 807 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 808 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 809 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 810 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 811 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 812 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 813 } 814 DRM_INFO(" Encoders:\n"); 815 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 816 radeon_encoder = to_radeon_encoder(encoder); 817 devices = radeon_encoder->devices & radeon_connector->devices; 818 if (devices) { 819 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 820 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 821 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 822 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 823 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 824 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 825 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 826 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 827 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 828 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 829 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 830 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 831 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 832 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 833 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 834 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 835 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 836 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 837 if (devices & ATOM_DEVICE_TV1_SUPPORT) 838 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 839 if (devices & ATOM_DEVICE_CV_SUPPORT) 840 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 841 } 842 } 843 i++; 844 } 845 } 846 847 static bool radeon_setup_enc_conn(struct drm_device *dev) 848 { 849 struct radeon_device *rdev = dev->dev_private; 850 bool ret = false; 851 852 if (rdev->bios) { 853 if (rdev->is_atom_bios) { 854 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 855 if (!ret) 856 ret = radeon_get_atom_connector_info_from_object_table(dev); 857 } else { 858 ret = radeon_get_legacy_connector_info_from_bios(dev); 859 if (!ret) 860 ret = radeon_get_legacy_connector_info_from_table(dev); 861 } 862 } else { 863 if (!ASIC_IS_AVIVO(rdev)) 864 ret = radeon_get_legacy_connector_info_from_table(dev); 865 } 866 if (ret) { 867 radeon_setup_encoder_clones(dev); 868 radeon_print_display_setup(dev); 869 } 870 871 return ret; 872 } 873 874 /* avivo */ 875 876 /** 877 * avivo_reduce_ratio - fractional number reduction 878 * 879 * @nom: nominator 880 * @den: denominator 881 * @nom_min: minimum value for nominator 882 * @den_min: minimum value for denominator 883 * 884 * Find the greatest common divisor and apply it on both nominator and 885 * denominator, but make nominator and denominator are at least as large 886 * as their minimum values. 887 */ 888 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 889 unsigned nom_min, unsigned den_min) 890 { 891 unsigned tmp; 892 893 /* reduce the numbers to a simpler ratio */ 894 tmp = gcd(*nom, *den); 895 *nom /= tmp; 896 *den /= tmp; 897 898 /* make sure nominator is large enough */ 899 if (*nom < nom_min) { 900 tmp = DIV_ROUND_UP(nom_min, *nom); 901 *nom *= tmp; 902 *den *= tmp; 903 } 904 905 /* make sure the denominator is large enough */ 906 if (*den < den_min) { 907 tmp = DIV_ROUND_UP(den_min, *den); 908 *nom *= tmp; 909 *den *= tmp; 910 } 911 } 912 913 /** 914 * avivo_get_fb_ref_div - feedback and ref divider calculation 915 * 916 * @nom: nominator 917 * @den: denominator 918 * @post_div: post divider 919 * @fb_div_max: feedback divider maximum 920 * @ref_div_max: reference divider maximum 921 * @fb_div: resulting feedback divider 922 * @ref_div: resulting reference divider 923 * 924 * Calculate feedback and reference divider for a given post divider. Makes 925 * sure we stay within the limits. 926 */ 927 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 928 unsigned fb_div_max, unsigned ref_div_max, 929 unsigned *fb_div, unsigned *ref_div) 930 { 931 /* limit reference * post divider to a maximum */ 932 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 933 934 /* get matching reference and feedback divider */ 935 *ref_div = min(max(den/post_div, 1u), ref_div_max); 936 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 937 938 /* limit fb divider to its maximum */ 939 if (*fb_div > fb_div_max) { 940 *ref_div = (*ref_div * fb_div_max)/(*fb_div); 941 *fb_div = fb_div_max; 942 } 943 } 944 945 /** 946 * radeon_compute_pll_avivo - compute PLL paramaters 947 * 948 * @pll: information about the PLL 949 * @dot_clock_p: resulting pixel clock 950 * fb_div_p: resulting feedback divider 951 * frac_fb_div_p: fractional part of the feedback divider 952 * ref_div_p: resulting reference divider 953 * post_div_p: resulting reference divider 954 * 955 * Try to calculate the PLL parameters to generate the given frequency: 956 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 957 */ 958 void radeon_compute_pll_avivo(struct radeon_pll *pll, 959 u32 freq, 960 u32 *dot_clock_p, 961 u32 *fb_div_p, 962 u32 *frac_fb_div_p, 963 u32 *ref_div_p, 964 u32 *post_div_p) 965 { 966 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 967 freq : freq / 10; 968 969 unsigned fb_div_min, fb_div_max, fb_div; 970 unsigned post_div_min, post_div_max, post_div; 971 unsigned ref_div_min, ref_div_max, ref_div; 972 unsigned post_div_best, diff_best; 973 unsigned nom, den; 974 975 /* determine allowed feedback divider range */ 976 fb_div_min = pll->min_feedback_div; 977 fb_div_max = pll->max_feedback_div; 978 979 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 980 fb_div_min *= 10; 981 fb_div_max *= 10; 982 } 983 984 /* determine allowed ref divider range */ 985 if (pll->flags & RADEON_PLL_USE_REF_DIV) 986 ref_div_min = pll->reference_div; 987 else 988 ref_div_min = pll->min_ref_div; 989 990 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 991 pll->flags & RADEON_PLL_USE_REF_DIV) 992 ref_div_max = pll->reference_div; 993 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 994 /* fix for problems on RS880 */ 995 ref_div_max = min(pll->max_ref_div, 7u); 996 else 997 ref_div_max = pll->max_ref_div; 998 999 /* determine allowed post divider range */ 1000 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1001 post_div_min = pll->post_div; 1002 post_div_max = pll->post_div; 1003 } else { 1004 unsigned vco_min, vco_max; 1005 1006 if (pll->flags & RADEON_PLL_IS_LCD) { 1007 vco_min = pll->lcd_pll_out_min; 1008 vco_max = pll->lcd_pll_out_max; 1009 } else { 1010 vco_min = pll->pll_out_min; 1011 vco_max = pll->pll_out_max; 1012 } 1013 1014 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1015 vco_min *= 10; 1016 vco_max *= 10; 1017 } 1018 1019 post_div_min = vco_min / target_clock; 1020 if ((target_clock * post_div_min) < vco_min) 1021 ++post_div_min; 1022 if (post_div_min < pll->min_post_div) 1023 post_div_min = pll->min_post_div; 1024 1025 post_div_max = vco_max / target_clock; 1026 if ((target_clock * post_div_max) > vco_max) 1027 --post_div_max; 1028 if (post_div_max > pll->max_post_div) 1029 post_div_max = pll->max_post_div; 1030 } 1031 1032 /* represent the searched ratio as fractional number */ 1033 nom = target_clock; 1034 den = pll->reference_freq; 1035 1036 /* reduce the numbers to a simpler ratio */ 1037 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1038 1039 /* now search for a post divider */ 1040 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1041 post_div_best = post_div_min; 1042 else 1043 post_div_best = post_div_max; 1044 diff_best = ~0; 1045 1046 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1047 unsigned diff; 1048 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1049 ref_div_max, &fb_div, &ref_div); 1050 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1051 (ref_div * post_div)); 1052 1053 if (diff < diff_best || (diff == diff_best && 1054 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1055 1056 post_div_best = post_div; 1057 diff_best = diff; 1058 } 1059 } 1060 post_div = post_div_best; 1061 1062 /* get the feedback and reference divider for the optimal value */ 1063 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1064 &fb_div, &ref_div); 1065 1066 /* reduce the numbers to a simpler ratio once more */ 1067 /* this also makes sure that the reference divider is large enough */ 1068 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1069 1070 /* avoid high jitter with small fractional dividers */ 1071 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1072 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1073 if (fb_div < fb_div_min) { 1074 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1075 fb_div *= tmp; 1076 ref_div *= tmp; 1077 } 1078 } 1079 1080 /* and finally save the result */ 1081 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1082 *fb_div_p = fb_div / 10; 1083 *frac_fb_div_p = fb_div % 10; 1084 } else { 1085 *fb_div_p = fb_div; 1086 *frac_fb_div_p = 0; 1087 } 1088 1089 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1090 (pll->reference_freq * *frac_fb_div_p)) / 1091 (ref_div * post_div * 10); 1092 *ref_div_p = ref_div; 1093 *post_div_p = post_div; 1094 1095 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1096 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1097 ref_div, post_div); 1098 } 1099 1100 /* pre-avivo */ 1101 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1102 { 1103 uint64_t mod; 1104 1105 n += d / 2; 1106 1107 mod = do_div(n, d); 1108 return n; 1109 } 1110 1111 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1112 uint64_t freq, 1113 uint32_t *dot_clock_p, 1114 uint32_t *fb_div_p, 1115 uint32_t *frac_fb_div_p, 1116 uint32_t *ref_div_p, 1117 uint32_t *post_div_p) 1118 { 1119 uint32_t min_ref_div = pll->min_ref_div; 1120 uint32_t max_ref_div = pll->max_ref_div; 1121 uint32_t min_post_div = pll->min_post_div; 1122 uint32_t max_post_div = pll->max_post_div; 1123 uint32_t min_fractional_feed_div = 0; 1124 uint32_t max_fractional_feed_div = 0; 1125 uint32_t best_vco = pll->best_vco; 1126 uint32_t best_post_div = 1; 1127 uint32_t best_ref_div = 1; 1128 uint32_t best_feedback_div = 1; 1129 uint32_t best_frac_feedback_div = 0; 1130 uint32_t best_freq = -1; 1131 uint32_t best_error = 0xffffffff; 1132 uint32_t best_vco_diff = 1; 1133 uint32_t post_div; 1134 u32 pll_out_min, pll_out_max; 1135 1136 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1137 freq = freq * 1000; 1138 1139 if (pll->flags & RADEON_PLL_IS_LCD) { 1140 pll_out_min = pll->lcd_pll_out_min; 1141 pll_out_max = pll->lcd_pll_out_max; 1142 } else { 1143 pll_out_min = pll->pll_out_min; 1144 pll_out_max = pll->pll_out_max; 1145 } 1146 1147 if (pll_out_min > 64800) 1148 pll_out_min = 64800; 1149 1150 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1151 min_ref_div = max_ref_div = pll->reference_div; 1152 else { 1153 while (min_ref_div < max_ref_div-1) { 1154 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1155 uint32_t pll_in = pll->reference_freq / mid; 1156 if (pll_in < pll->pll_in_min) 1157 max_ref_div = mid; 1158 else if (pll_in > pll->pll_in_max) 1159 min_ref_div = mid; 1160 else 1161 break; 1162 } 1163 } 1164 1165 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1166 min_post_div = max_post_div = pll->post_div; 1167 1168 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1169 min_fractional_feed_div = pll->min_frac_feedback_div; 1170 max_fractional_feed_div = pll->max_frac_feedback_div; 1171 } 1172 1173 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1174 uint32_t ref_div; 1175 1176 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1177 continue; 1178 1179 /* legacy radeons only have a few post_divs */ 1180 if (pll->flags & RADEON_PLL_LEGACY) { 1181 if ((post_div == 5) || 1182 (post_div == 7) || 1183 (post_div == 9) || 1184 (post_div == 10) || 1185 (post_div == 11) || 1186 (post_div == 13) || 1187 (post_div == 14) || 1188 (post_div == 15)) 1189 continue; 1190 } 1191 1192 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1193 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1194 uint32_t pll_in = pll->reference_freq / ref_div; 1195 uint32_t min_feed_div = pll->min_feedback_div; 1196 uint32_t max_feed_div = pll->max_feedback_div + 1; 1197 1198 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1199 continue; 1200 1201 while (min_feed_div < max_feed_div) { 1202 uint32_t vco; 1203 uint32_t min_frac_feed_div = min_fractional_feed_div; 1204 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1205 uint32_t frac_feedback_div; 1206 uint64_t tmp; 1207 1208 feedback_div = (min_feed_div + max_feed_div) / 2; 1209 1210 tmp = (uint64_t)pll->reference_freq * feedback_div; 1211 vco = radeon_div(tmp, ref_div); 1212 1213 if (vco < pll_out_min) { 1214 min_feed_div = feedback_div + 1; 1215 continue; 1216 } else if (vco > pll_out_max) { 1217 max_feed_div = feedback_div; 1218 continue; 1219 } 1220 1221 while (min_frac_feed_div < max_frac_feed_div) { 1222 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1223 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1224 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1225 current_freq = radeon_div(tmp, ref_div * post_div); 1226 1227 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1228 if (freq < current_freq) 1229 error = 0xffffffff; 1230 else 1231 error = freq - current_freq; 1232 } else 1233 error = abs(current_freq - freq); 1234 vco_diff = abs(vco - best_vco); 1235 1236 if ((best_vco == 0 && error < best_error) || 1237 (best_vco != 0 && 1238 ((best_error > 100 && error < best_error - 100) || 1239 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1240 best_post_div = post_div; 1241 best_ref_div = ref_div; 1242 best_feedback_div = feedback_div; 1243 best_frac_feedback_div = frac_feedback_div; 1244 best_freq = current_freq; 1245 best_error = error; 1246 best_vco_diff = vco_diff; 1247 } else if (current_freq == freq) { 1248 if (best_freq == -1) { 1249 best_post_div = post_div; 1250 best_ref_div = ref_div; 1251 best_feedback_div = feedback_div; 1252 best_frac_feedback_div = frac_feedback_div; 1253 best_freq = current_freq; 1254 best_error = error; 1255 best_vco_diff = vco_diff; 1256 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1257 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1258 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1259 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1260 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1261 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1262 best_post_div = post_div; 1263 best_ref_div = ref_div; 1264 best_feedback_div = feedback_div; 1265 best_frac_feedback_div = frac_feedback_div; 1266 best_freq = current_freq; 1267 best_error = error; 1268 best_vco_diff = vco_diff; 1269 } 1270 } 1271 if (current_freq < freq) 1272 min_frac_feed_div = frac_feedback_div + 1; 1273 else 1274 max_frac_feed_div = frac_feedback_div; 1275 } 1276 if (current_freq < freq) 1277 min_feed_div = feedback_div + 1; 1278 else 1279 max_feed_div = feedback_div; 1280 } 1281 } 1282 } 1283 1284 *dot_clock_p = best_freq / 10000; 1285 *fb_div_p = best_feedback_div; 1286 *frac_fb_div_p = best_frac_feedback_div; 1287 *ref_div_p = best_ref_div; 1288 *post_div_p = best_post_div; 1289 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1290 (long long)freq, 1291 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1292 best_ref_div, best_post_div); 1293 1294 } 1295 1296 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1297 .destroy = drm_gem_fb_destroy, 1298 .create_handle = drm_gem_fb_create_handle, 1299 }; 1300 1301 int 1302 radeon_framebuffer_init(struct drm_device *dev, 1303 struct drm_framebuffer *fb, 1304 const struct drm_mode_fb_cmd2 *mode_cmd, 1305 struct drm_gem_object *obj) 1306 { 1307 int ret; 1308 fb->obj[0] = obj; 1309 drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); 1310 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs); 1311 if (ret) { 1312 fb->obj[0] = NULL; 1313 return ret; 1314 } 1315 return 0; 1316 } 1317 1318 static struct drm_framebuffer * 1319 radeon_user_framebuffer_create(struct drm_device *dev, 1320 struct drm_file *file_priv, 1321 const struct drm_mode_fb_cmd2 *mode_cmd) 1322 { 1323 struct drm_gem_object *obj; 1324 struct drm_framebuffer *fb; 1325 int ret; 1326 1327 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1328 if (obj == NULL) { 1329 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1330 "can't create framebuffer\n", mode_cmd->handles[0]); 1331 return ERR_PTR(-ENOENT); 1332 } 1333 1334 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1335 if (obj->import_attach) { 1336 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1337 return ERR_PTR(-EINVAL); 1338 } 1339 1340 fb = kzalloc(sizeof(*fb), GFP_KERNEL); 1341 if (fb == NULL) { 1342 drm_gem_object_put_unlocked(obj); 1343 return ERR_PTR(-ENOMEM); 1344 } 1345 1346 ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj); 1347 if (ret) { 1348 kfree(fb); 1349 drm_gem_object_put_unlocked(obj); 1350 return ERR_PTR(ret); 1351 } 1352 1353 return fb; 1354 } 1355 1356 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1357 .fb_create = radeon_user_framebuffer_create, 1358 .output_poll_changed = drm_fb_helper_output_poll_changed, 1359 }; 1360 1361 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1362 { { 0, "driver" }, 1363 { 1, "bios" }, 1364 }; 1365 1366 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1367 { { TV_STD_NTSC, "ntsc" }, 1368 { TV_STD_PAL, "pal" }, 1369 { TV_STD_PAL_M, "pal-m" }, 1370 { TV_STD_PAL_60, "pal-60" }, 1371 { TV_STD_NTSC_J, "ntsc-j" }, 1372 { TV_STD_SCART_PAL, "scart-pal" }, 1373 { TV_STD_PAL_CN, "pal-cn" }, 1374 { TV_STD_SECAM, "secam" }, 1375 }; 1376 1377 static const struct drm_prop_enum_list radeon_underscan_enum_list[] = 1378 { { UNDERSCAN_OFF, "off" }, 1379 { UNDERSCAN_ON, "on" }, 1380 { UNDERSCAN_AUTO, "auto" }, 1381 }; 1382 1383 static const struct drm_prop_enum_list radeon_audio_enum_list[] = 1384 { { RADEON_AUDIO_DISABLE, "off" }, 1385 { RADEON_AUDIO_ENABLE, "on" }, 1386 { RADEON_AUDIO_AUTO, "auto" }, 1387 }; 1388 1389 /* XXX support different dither options? spatial, temporal, both, etc. */ 1390 static const struct drm_prop_enum_list radeon_dither_enum_list[] = 1391 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1392 { RADEON_FMT_DITHER_ENABLE, "on" }, 1393 }; 1394 1395 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1396 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1397 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1398 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1399 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1400 }; 1401 1402 static int radeon_modeset_create_props(struct radeon_device *rdev) 1403 { 1404 int sz; 1405 1406 if (rdev->is_atom_bios) { 1407 rdev->mode_info.coherent_mode_property = 1408 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1409 if (!rdev->mode_info.coherent_mode_property) 1410 return -ENOMEM; 1411 } 1412 1413 if (!ASIC_IS_AVIVO(rdev)) { 1414 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1415 rdev->mode_info.tmds_pll_property = 1416 drm_property_create_enum(rdev->ddev, 0, 1417 "tmds_pll", 1418 radeon_tmds_pll_enum_list, sz); 1419 } 1420 1421 rdev->mode_info.load_detect_property = 1422 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1423 if (!rdev->mode_info.load_detect_property) 1424 return -ENOMEM; 1425 1426 drm_mode_create_scaling_mode_property(rdev->ddev); 1427 1428 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1429 rdev->mode_info.tv_std_property = 1430 drm_property_create_enum(rdev->ddev, 0, 1431 "tv standard", 1432 radeon_tv_std_enum_list, sz); 1433 1434 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1435 rdev->mode_info.underscan_property = 1436 drm_property_create_enum(rdev->ddev, 0, 1437 "underscan", 1438 radeon_underscan_enum_list, sz); 1439 1440 rdev->mode_info.underscan_hborder_property = 1441 drm_property_create_range(rdev->ddev, 0, 1442 "underscan hborder", 0, 128); 1443 if (!rdev->mode_info.underscan_hborder_property) 1444 return -ENOMEM; 1445 1446 rdev->mode_info.underscan_vborder_property = 1447 drm_property_create_range(rdev->ddev, 0, 1448 "underscan vborder", 0, 128); 1449 if (!rdev->mode_info.underscan_vborder_property) 1450 return -ENOMEM; 1451 1452 sz = ARRAY_SIZE(radeon_audio_enum_list); 1453 rdev->mode_info.audio_property = 1454 drm_property_create_enum(rdev->ddev, 0, 1455 "audio", 1456 radeon_audio_enum_list, sz); 1457 1458 sz = ARRAY_SIZE(radeon_dither_enum_list); 1459 rdev->mode_info.dither_property = 1460 drm_property_create_enum(rdev->ddev, 0, 1461 "dither", 1462 radeon_dither_enum_list, sz); 1463 1464 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1465 rdev->mode_info.output_csc_property = 1466 drm_property_create_enum(rdev->ddev, 0, 1467 "output_csc", 1468 radeon_output_csc_enum_list, sz); 1469 1470 return 0; 1471 } 1472 1473 void radeon_update_display_priority(struct radeon_device *rdev) 1474 { 1475 /* adjustment options for the display watermarks */ 1476 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1477 /* set display priority to high for r3xx, rv515 chips 1478 * this avoids flickering due to underflow to the 1479 * display controllers during heavy acceleration. 1480 * Don't force high on rs4xx igp chips as it seems to 1481 * affect the sound card. See kernel bug 15982. 1482 */ 1483 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1484 !(rdev->flags & RADEON_IS_IGP)) 1485 rdev->disp_priority = 2; 1486 else 1487 rdev->disp_priority = 0; 1488 } else 1489 rdev->disp_priority = radeon_disp_priority; 1490 1491 } 1492 1493 /* 1494 * Allocate hdmi structs and determine register offsets 1495 */ 1496 static void radeon_afmt_init(struct radeon_device *rdev) 1497 { 1498 int i; 1499 1500 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1501 rdev->mode_info.afmt[i] = NULL; 1502 1503 if (ASIC_IS_NODCE(rdev)) { 1504 /* nothing to do */ 1505 } else if (ASIC_IS_DCE4(rdev)) { 1506 static uint32_t eg_offsets[] = { 1507 EVERGREEN_CRTC0_REGISTER_OFFSET, 1508 EVERGREEN_CRTC1_REGISTER_OFFSET, 1509 EVERGREEN_CRTC2_REGISTER_OFFSET, 1510 EVERGREEN_CRTC3_REGISTER_OFFSET, 1511 EVERGREEN_CRTC4_REGISTER_OFFSET, 1512 EVERGREEN_CRTC5_REGISTER_OFFSET, 1513 0x13830 - 0x7030, 1514 }; 1515 int num_afmt; 1516 1517 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1518 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1519 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1520 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1521 if (ASIC_IS_DCE8(rdev)) 1522 num_afmt = 7; 1523 else if (ASIC_IS_DCE6(rdev)) 1524 num_afmt = 6; 1525 else if (ASIC_IS_DCE5(rdev)) 1526 num_afmt = 6; 1527 else if (ASIC_IS_DCE41(rdev)) 1528 num_afmt = 2; 1529 else /* DCE4 */ 1530 num_afmt = 6; 1531 1532 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1533 for (i = 0; i < num_afmt; i++) { 1534 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1535 if (rdev->mode_info.afmt[i]) { 1536 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1537 rdev->mode_info.afmt[i]->id = i; 1538 } 1539 } 1540 } else if (ASIC_IS_DCE3(rdev)) { 1541 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1542 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1543 if (rdev->mode_info.afmt[0]) { 1544 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1545 rdev->mode_info.afmt[0]->id = 0; 1546 } 1547 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1548 if (rdev->mode_info.afmt[1]) { 1549 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1550 rdev->mode_info.afmt[1]->id = 1; 1551 } 1552 } else if (ASIC_IS_DCE2(rdev)) { 1553 /* DCE2 has at least 1 routable audio block */ 1554 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1555 if (rdev->mode_info.afmt[0]) { 1556 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1557 rdev->mode_info.afmt[0]->id = 0; 1558 } 1559 /* r6xx has 2 routable audio blocks */ 1560 if (rdev->family >= CHIP_R600) { 1561 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1562 if (rdev->mode_info.afmt[1]) { 1563 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1564 rdev->mode_info.afmt[1]->id = 1; 1565 } 1566 } 1567 } 1568 } 1569 1570 static void radeon_afmt_fini(struct radeon_device *rdev) 1571 { 1572 int i; 1573 1574 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1575 kfree(rdev->mode_info.afmt[i]); 1576 rdev->mode_info.afmt[i] = NULL; 1577 } 1578 } 1579 1580 int radeon_modeset_init(struct radeon_device *rdev) 1581 { 1582 int i; 1583 int ret; 1584 1585 drm_mode_config_init(rdev->ddev); 1586 rdev->mode_info.mode_config_initialized = true; 1587 1588 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1589 1590 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1591 rdev->ddev->mode_config.async_page_flip = true; 1592 1593 if (ASIC_IS_DCE5(rdev)) { 1594 rdev->ddev->mode_config.max_width = 16384; 1595 rdev->ddev->mode_config.max_height = 16384; 1596 } else if (ASIC_IS_AVIVO(rdev)) { 1597 rdev->ddev->mode_config.max_width = 8192; 1598 rdev->ddev->mode_config.max_height = 8192; 1599 } else { 1600 rdev->ddev->mode_config.max_width = 4096; 1601 rdev->ddev->mode_config.max_height = 4096; 1602 } 1603 1604 rdev->ddev->mode_config.preferred_depth = 24; 1605 rdev->ddev->mode_config.prefer_shadow = 1; 1606 1607 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1608 1609 ret = radeon_modeset_create_props(rdev); 1610 if (ret) { 1611 return ret; 1612 } 1613 1614 /* init i2c buses */ 1615 radeon_i2c_init(rdev); 1616 1617 /* check combios for a valid hardcoded EDID - Sun servers */ 1618 if (!rdev->is_atom_bios) { 1619 /* check for hardcoded EDID in BIOS */ 1620 radeon_combios_check_hardcoded_edid(rdev); 1621 } 1622 1623 /* allocate crtcs */ 1624 for (i = 0; i < rdev->num_crtc; i++) { 1625 radeon_crtc_init(rdev->ddev, i); 1626 } 1627 1628 /* okay we should have all the bios connectors */ 1629 ret = radeon_setup_enc_conn(rdev->ddev); 1630 if (!ret) { 1631 return ret; 1632 } 1633 1634 /* init dig PHYs, disp eng pll */ 1635 if (rdev->is_atom_bios) { 1636 radeon_atom_encoder_init(rdev); 1637 radeon_atom_disp_eng_pll_init(rdev); 1638 } 1639 1640 /* initialize hpd */ 1641 radeon_hpd_init(rdev); 1642 1643 /* setup afmt */ 1644 radeon_afmt_init(rdev); 1645 1646 radeon_fbdev_init(rdev); 1647 drm_kms_helper_poll_init(rdev->ddev); 1648 1649 /* do pm late init */ 1650 ret = radeon_pm_late_init(rdev); 1651 1652 return 0; 1653 } 1654 1655 void radeon_modeset_fini(struct radeon_device *rdev) 1656 { 1657 if (rdev->mode_info.mode_config_initialized) { 1658 drm_kms_helper_poll_fini(rdev->ddev); 1659 radeon_hpd_fini(rdev); 1660 drm_helper_force_disable_all(rdev->ddev); 1661 radeon_fbdev_fini(rdev); 1662 radeon_afmt_fini(rdev); 1663 drm_mode_config_cleanup(rdev->ddev); 1664 rdev->mode_info.mode_config_initialized = false; 1665 } 1666 1667 kfree(rdev->mode_info.bios_hardcoded_edid); 1668 1669 /* free i2c buses */ 1670 radeon_i2c_fini(rdev); 1671 } 1672 1673 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1674 { 1675 /* try and guess if this is a tv or a monitor */ 1676 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1677 (mode->vdisplay == 576) || /* 576p */ 1678 (mode->vdisplay == 720) || /* 720p */ 1679 (mode->vdisplay == 1080)) /* 1080p */ 1680 return true; 1681 else 1682 return false; 1683 } 1684 1685 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1686 const struct drm_display_mode *mode, 1687 struct drm_display_mode *adjusted_mode) 1688 { 1689 struct drm_device *dev = crtc->dev; 1690 struct radeon_device *rdev = dev->dev_private; 1691 struct drm_encoder *encoder; 1692 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1693 struct radeon_encoder *radeon_encoder; 1694 struct drm_connector *connector; 1695 bool first = true; 1696 u32 src_v = 1, dst_v = 1; 1697 u32 src_h = 1, dst_h = 1; 1698 1699 radeon_crtc->h_border = 0; 1700 radeon_crtc->v_border = 0; 1701 1702 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1703 if (encoder->crtc != crtc) 1704 continue; 1705 radeon_encoder = to_radeon_encoder(encoder); 1706 connector = radeon_get_connector_for_encoder(encoder); 1707 1708 if (first) { 1709 /* set scaling */ 1710 if (radeon_encoder->rmx_type == RMX_OFF) 1711 radeon_crtc->rmx_type = RMX_OFF; 1712 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1713 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1714 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1715 else 1716 radeon_crtc->rmx_type = RMX_OFF; 1717 /* copy native mode */ 1718 memcpy(&radeon_crtc->native_mode, 1719 &radeon_encoder->native_mode, 1720 sizeof(struct drm_display_mode)); 1721 src_v = crtc->mode.vdisplay; 1722 dst_v = radeon_crtc->native_mode.vdisplay; 1723 src_h = crtc->mode.hdisplay; 1724 dst_h = radeon_crtc->native_mode.hdisplay; 1725 1726 /* fix up for overscan on hdmi */ 1727 if (ASIC_IS_AVIVO(rdev) && 1728 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1729 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1730 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1731 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1732 is_hdtv_mode(mode)))) { 1733 if (radeon_encoder->underscan_hborder != 0) 1734 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1735 else 1736 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1737 if (radeon_encoder->underscan_vborder != 0) 1738 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1739 else 1740 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1741 radeon_crtc->rmx_type = RMX_FULL; 1742 src_v = crtc->mode.vdisplay; 1743 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1744 src_h = crtc->mode.hdisplay; 1745 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1746 } 1747 first = false; 1748 } else { 1749 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1750 /* WARNING: Right now this can't happen but 1751 * in the future we need to check that scaling 1752 * are consistent across different encoder 1753 * (ie all encoder can work with the same 1754 * scaling). 1755 */ 1756 DRM_ERROR("Scaling not consistent across encoder.\n"); 1757 return false; 1758 } 1759 } 1760 } 1761 if (radeon_crtc->rmx_type != RMX_OFF) { 1762 fixed20_12 a, b; 1763 a.full = dfixed_const(src_v); 1764 b.full = dfixed_const(dst_v); 1765 radeon_crtc->vsc.full = dfixed_div(a, b); 1766 a.full = dfixed_const(src_h); 1767 b.full = dfixed_const(dst_h); 1768 radeon_crtc->hsc.full = dfixed_div(a, b); 1769 } else { 1770 radeon_crtc->vsc.full = dfixed_const(1); 1771 radeon_crtc->hsc.full = dfixed_const(1); 1772 } 1773 return true; 1774 } 1775 1776 /* 1777 * Retrieve current video scanout position of crtc on a given gpu, and 1778 * an optional accurate timestamp of when query happened. 1779 * 1780 * \param dev Device to query. 1781 * \param crtc Crtc to query. 1782 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1783 * For driver internal use only also supports these flags: 1784 * 1785 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1786 * of a fudged earlier start of vblank. 1787 * 1788 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1789 * fudged earlier start of vblank in *vpos and the distance 1790 * to true start of vblank in *hpos. 1791 * 1792 * \param *vpos Location where vertical scanout position should be stored. 1793 * \param *hpos Location where horizontal scanout position should go. 1794 * \param *stime Target location for timestamp taken immediately before 1795 * scanout position query. Can be NULL to skip timestamp. 1796 * \param *etime Target location for timestamp taken immediately after 1797 * scanout position query. Can be NULL to skip timestamp. 1798 * 1799 * Returns vpos as a positive number while in active scanout area. 1800 * Returns vpos as a negative number inside vblank, counting the number 1801 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1802 * until start of active scanout / end of vblank." 1803 * 1804 * \return Flags, or'ed together as follows: 1805 * 1806 * DRM_SCANOUTPOS_VALID = Query successful. 1807 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1808 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1809 * this flag means that returned position may be offset by a constant but 1810 * unknown small number of scanlines wrt. real scanout position. 1811 * 1812 */ 1813 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1814 unsigned int flags, int *vpos, int *hpos, 1815 ktime_t *stime, ktime_t *etime, 1816 const struct drm_display_mode *mode) 1817 { 1818 u32 stat_crtc = 0, vbl = 0, position = 0; 1819 int vbl_start, vbl_end, vtotal, ret = 0; 1820 bool in_vbl = true; 1821 1822 struct radeon_device *rdev = dev->dev_private; 1823 1824 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1825 1826 /* Get optional system timestamp before query. */ 1827 if (stime) 1828 *stime = ktime_get(); 1829 1830 if (ASIC_IS_DCE4(rdev)) { 1831 if (pipe == 0) { 1832 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1833 EVERGREEN_CRTC0_REGISTER_OFFSET); 1834 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1835 EVERGREEN_CRTC0_REGISTER_OFFSET); 1836 ret |= DRM_SCANOUTPOS_VALID; 1837 } 1838 if (pipe == 1) { 1839 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1840 EVERGREEN_CRTC1_REGISTER_OFFSET); 1841 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1842 EVERGREEN_CRTC1_REGISTER_OFFSET); 1843 ret |= DRM_SCANOUTPOS_VALID; 1844 } 1845 if (pipe == 2) { 1846 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1847 EVERGREEN_CRTC2_REGISTER_OFFSET); 1848 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1849 EVERGREEN_CRTC2_REGISTER_OFFSET); 1850 ret |= DRM_SCANOUTPOS_VALID; 1851 } 1852 if (pipe == 3) { 1853 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1854 EVERGREEN_CRTC3_REGISTER_OFFSET); 1855 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1856 EVERGREEN_CRTC3_REGISTER_OFFSET); 1857 ret |= DRM_SCANOUTPOS_VALID; 1858 } 1859 if (pipe == 4) { 1860 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1861 EVERGREEN_CRTC4_REGISTER_OFFSET); 1862 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1863 EVERGREEN_CRTC4_REGISTER_OFFSET); 1864 ret |= DRM_SCANOUTPOS_VALID; 1865 } 1866 if (pipe == 5) { 1867 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1868 EVERGREEN_CRTC5_REGISTER_OFFSET); 1869 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1870 EVERGREEN_CRTC5_REGISTER_OFFSET); 1871 ret |= DRM_SCANOUTPOS_VALID; 1872 } 1873 } else if (ASIC_IS_AVIVO(rdev)) { 1874 if (pipe == 0) { 1875 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1876 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1877 ret |= DRM_SCANOUTPOS_VALID; 1878 } 1879 if (pipe == 1) { 1880 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1881 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1882 ret |= DRM_SCANOUTPOS_VALID; 1883 } 1884 } else { 1885 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1886 if (pipe == 0) { 1887 /* Assume vbl_end == 0, get vbl_start from 1888 * upper 16 bits. 1889 */ 1890 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1891 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1892 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1893 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1894 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1895 if (!(stat_crtc & 1)) 1896 in_vbl = false; 1897 1898 ret |= DRM_SCANOUTPOS_VALID; 1899 } 1900 if (pipe == 1) { 1901 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1902 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1903 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1904 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1905 if (!(stat_crtc & 1)) 1906 in_vbl = false; 1907 1908 ret |= DRM_SCANOUTPOS_VALID; 1909 } 1910 } 1911 1912 /* Get optional system timestamp after query. */ 1913 if (etime) 1914 *etime = ktime_get(); 1915 1916 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1917 1918 /* Decode into vertical and horizontal scanout position. */ 1919 *vpos = position & 0x1fff; 1920 *hpos = (position >> 16) & 0x1fff; 1921 1922 /* Valid vblank area boundaries from gpu retrieved? */ 1923 if (vbl > 0) { 1924 /* Yes: Decode. */ 1925 ret |= DRM_SCANOUTPOS_ACCURATE; 1926 vbl_start = vbl & 0x1fff; 1927 vbl_end = (vbl >> 16) & 0x1fff; 1928 } 1929 else { 1930 /* No: Fake something reasonable which gives at least ok results. */ 1931 vbl_start = mode->crtc_vdisplay; 1932 vbl_end = 0; 1933 } 1934 1935 /* Called from driver internal vblank counter query code? */ 1936 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1937 /* Caller wants distance from real vbl_start in *hpos */ 1938 *hpos = *vpos - vbl_start; 1939 } 1940 1941 /* Fudge vblank to start a few scanlines earlier to handle the 1942 * problem that vblank irqs fire a few scanlines before start 1943 * of vblank. Some driver internal callers need the true vblank 1944 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1945 * 1946 * The cause of the "early" vblank irq is that the irq is triggered 1947 * by the line buffer logic when the line buffer read position enters 1948 * the vblank, whereas our crtc scanout position naturally lags the 1949 * line buffer read position. 1950 */ 1951 if (!(flags & USE_REAL_VBLANKSTART)) 1952 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1953 1954 /* Test scanout position against vblank region. */ 1955 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1956 in_vbl = false; 1957 1958 /* In vblank? */ 1959 if (in_vbl) 1960 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1961 1962 /* Called from driver internal vblank counter query code? */ 1963 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1964 /* Caller wants distance from fudged earlier vbl_start */ 1965 *vpos -= vbl_start; 1966 return ret; 1967 } 1968 1969 /* Check if inside vblank area and apply corrective offsets: 1970 * vpos will then be >=0 in video scanout area, but negative 1971 * within vblank area, counting down the number of lines until 1972 * start of scanout. 1973 */ 1974 1975 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1976 if (in_vbl && (*vpos >= vbl_start)) { 1977 vtotal = mode->crtc_vtotal; 1978 *vpos = *vpos - vtotal; 1979 } 1980 1981 /* Correct for shifted end of vbl at vbl_end. */ 1982 *vpos = *vpos - vbl_end; 1983 1984 return ret; 1985 } 1986 1987 bool 1988 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, 1989 bool in_vblank_irq, int *vpos, int *hpos, 1990 ktime_t *stime, ktime_t *etime, 1991 const struct drm_display_mode *mode) 1992 { 1993 struct drm_device *dev = crtc->dev; 1994 unsigned int pipe = crtc->index; 1995 1996 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1997 stime, etime, mode); 1998 } 1999