1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include <linux/pm_runtime.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include <drm/drm_edid.h> 37 38 #include <linux/gcd.h> 39 40 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 41 { 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 struct drm_device *dev = crtc->dev; 44 struct radeon_device *rdev = dev->dev_private; 45 u16 *r, *g, *b; 46 int i; 47 48 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 49 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 50 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 53 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 54 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 57 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 58 59 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 60 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 61 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 62 63 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 64 r = crtc->gamma_store; 65 g = r + crtc->gamma_size; 66 b = g + crtc->gamma_size; 67 for (i = 0; i < 256; i++) { 68 WREG32(AVIVO_DC_LUT_30_COLOR, 69 ((*r++ & 0xffc0) << 14) | 70 ((*g++ & 0xffc0) << 4) | 71 (*b++ >> 6)); 72 } 73 74 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 75 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 76 } 77 78 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 79 { 80 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 81 struct drm_device *dev = crtc->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 u16 *r, *g, *b; 84 int i; 85 86 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 87 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 88 89 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 90 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 92 93 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 94 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 96 97 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 98 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 99 100 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 101 r = crtc->gamma_store; 102 g = r + crtc->gamma_size; 103 b = g + crtc->gamma_size; 104 for (i = 0; i < 256; i++) { 105 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 106 ((*r++ & 0xffc0) << 14) | 107 ((*g++ & 0xffc0) << 4) | 108 (*b++ >> 6)); 109 } 110 } 111 112 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 113 { 114 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 115 struct drm_device *dev = crtc->dev; 116 struct radeon_device *rdev = dev->dev_private; 117 u16 *r, *g, *b; 118 int i; 119 120 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 121 122 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 123 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 124 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 125 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 126 NI_GRPH_PRESCALE_BYPASS); 127 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 128 NI_OVL_PRESCALE_BYPASS); 129 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 130 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 131 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 132 133 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 134 135 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 136 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 137 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 138 139 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 140 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 141 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 142 143 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 144 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 145 146 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 147 r = crtc->gamma_store; 148 g = r + crtc->gamma_size; 149 b = g + crtc->gamma_size; 150 for (i = 0; i < 256; i++) { 151 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 152 ((*r++ & 0xffc0) << 14) | 153 ((*g++ & 0xffc0) << 4) | 154 (*b++ >> 6)); 155 } 156 157 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 158 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 159 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 160 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 161 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 162 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 163 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 164 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 165 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 166 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 167 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 168 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 169 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 170 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 171 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 172 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 173 if (ASIC_IS_DCE8(rdev)) { 174 /* XXX this only needs to be programmed once per crtc at startup, 175 * not sure where the best place for it is 176 */ 177 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 178 CIK_CURSOR_ALPHA_BLND_ENA); 179 } 180 } 181 182 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 183 { 184 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 185 struct drm_device *dev = crtc->dev; 186 struct radeon_device *rdev = dev->dev_private; 187 u16 *r, *g, *b; 188 int i; 189 uint32_t dac2_cntl; 190 191 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 192 if (radeon_crtc->crtc_id == 0) 193 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 194 else 195 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 196 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 197 198 WREG8(RADEON_PALETTE_INDEX, 0); 199 r = crtc->gamma_store; 200 g = r + crtc->gamma_size; 201 b = g + crtc->gamma_size; 202 for (i = 0; i < 256; i++) { 203 WREG32(RADEON_PALETTE_30_DATA, 204 ((*r++ & 0xffc0) << 14) | 205 ((*g++ & 0xffc0) << 4) | 206 (*b++ >> 6)); 207 } 208 } 209 210 void radeon_crtc_load_lut(struct drm_crtc *crtc) 211 { 212 struct drm_device *dev = crtc->dev; 213 struct radeon_device *rdev = dev->dev_private; 214 215 if (!crtc->enabled) 216 return; 217 218 if (ASIC_IS_DCE5(rdev)) 219 dce5_crtc_load_lut(crtc); 220 else if (ASIC_IS_DCE4(rdev)) 221 dce4_crtc_load_lut(crtc); 222 else if (ASIC_IS_AVIVO(rdev)) 223 avivo_crtc_load_lut(crtc); 224 else 225 legacy_crtc_load_lut(crtc); 226 } 227 228 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 229 u16 *blue, uint32_t size, 230 struct drm_modeset_acquire_ctx *ctx) 231 { 232 radeon_crtc_load_lut(crtc); 233 234 return 0; 235 } 236 237 static void radeon_crtc_destroy(struct drm_crtc *crtc) 238 { 239 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 240 241 drm_crtc_cleanup(crtc); 242 destroy_workqueue(radeon_crtc->flip_queue); 243 kfree(radeon_crtc); 244 } 245 246 /** 247 * radeon_unpin_work_func - unpin old buffer object 248 * 249 * @__work - kernel work item 250 * 251 * Unpin the old frame buffer object outside of the interrupt handler 252 */ 253 static void radeon_unpin_work_func(struct work_struct *__work) 254 { 255 struct radeon_flip_work *work = 256 container_of(__work, struct radeon_flip_work, unpin_work); 257 int r; 258 259 /* unpin of the old buffer */ 260 r = radeon_bo_reserve(work->old_rbo, false); 261 if (likely(r == 0)) { 262 r = radeon_bo_unpin(work->old_rbo); 263 if (unlikely(r != 0)) { 264 DRM_ERROR("failed to unpin buffer after flip\n"); 265 } 266 radeon_bo_unreserve(work->old_rbo); 267 } else 268 DRM_ERROR("failed to reserve buffer after flip\n"); 269 270 drm_gem_object_put_unlocked(&work->old_rbo->gem_base); 271 kfree(work); 272 } 273 274 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 275 { 276 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 277 unsigned long flags; 278 u32 update_pending; 279 int vpos, hpos; 280 281 /* can happen during initialization */ 282 if (radeon_crtc == NULL) 283 return; 284 285 /* Skip the pageflip completion check below (based on polling) on 286 * asics which reliably support hw pageflip completion irqs. pflip 287 * irqs are a reliable and race-free method of handling pageflip 288 * completion detection. A use_pflipirq module parameter < 2 allows 289 * to override this in case of asics with faulty pflip irqs. 290 * A module parameter of 0 would only use this polling based path, 291 * a parameter of 1 would use pflip irq only as a backup to this 292 * path, as in Linux 3.16. 293 */ 294 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 295 return; 296 297 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 298 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 299 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 300 "RADEON_FLIP_SUBMITTED(%d)\n", 301 radeon_crtc->flip_status, 302 RADEON_FLIP_SUBMITTED); 303 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 304 return; 305 } 306 307 update_pending = radeon_page_flip_pending(rdev, crtc_id); 308 309 /* Has the pageflip already completed in crtc, or is it certain 310 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 311 * distance to start of "fudged earlier" vblank in vpos, distance to 312 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 313 * the last few scanlines before start of real vblank, where the vblank 314 * irq can fire, so we have sampled update_pending a bit too early and 315 * know the flip will complete at leading edge of the upcoming real 316 * vblank. On pre-AVIVO hardware, flips also complete inside the real 317 * vblank, not only at leading edge, so if update_pending for hpos >= 0 318 * == inside real vblank, the flip will complete almost immediately. 319 * Note that this method of completion handling is still not 100% race 320 * free, as we could execute before the radeon_flip_work_func managed 321 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 322 * but the flip still gets programmed into hw and completed during 323 * vblank, leading to a delayed emission of the flip completion event. 324 * This applies at least to pre-AVIVO hardware, where flips are always 325 * completing inside vblank, not only at leading edge of vblank. 326 */ 327 if (update_pending && 328 (DRM_SCANOUTPOS_VALID & 329 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 330 GET_DISTANCE_TO_VBLANKSTART, 331 &vpos, &hpos, NULL, NULL, 332 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 333 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 334 /* crtc didn't flip in this target vblank interval, 335 * but flip is pending in crtc. Based on the current 336 * scanout position we know that the current frame is 337 * (nearly) complete and the flip will (likely) 338 * complete before the start of the next frame. 339 */ 340 update_pending = 0; 341 } 342 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 343 if (!update_pending) 344 radeon_crtc_handle_flip(rdev, crtc_id); 345 } 346 347 /** 348 * radeon_crtc_handle_flip - page flip completed 349 * 350 * @rdev: radeon device pointer 351 * @crtc_id: crtc number this event is for 352 * 353 * Called when we are sure that a page flip for this crtc is completed. 354 */ 355 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 356 { 357 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 358 struct radeon_flip_work *work; 359 unsigned long flags; 360 361 /* this can happen at init */ 362 if (radeon_crtc == NULL) 363 return; 364 365 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 366 work = radeon_crtc->flip_work; 367 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 368 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 369 "RADEON_FLIP_SUBMITTED(%d)\n", 370 radeon_crtc->flip_status, 371 RADEON_FLIP_SUBMITTED); 372 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 373 return; 374 } 375 376 /* Pageflip completed. Clean up. */ 377 radeon_crtc->flip_status = RADEON_FLIP_NONE; 378 radeon_crtc->flip_work = NULL; 379 380 /* wakeup userspace */ 381 if (work->event) 382 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 383 384 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 385 386 drm_crtc_vblank_put(&radeon_crtc->base); 387 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 388 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 389 } 390 391 /** 392 * radeon_flip_work_func - page flip framebuffer 393 * 394 * @work - kernel work item 395 * 396 * Wait for the buffer object to become idle and do the actual page flip 397 */ 398 static void radeon_flip_work_func(struct work_struct *__work) 399 { 400 struct radeon_flip_work *work = 401 container_of(__work, struct radeon_flip_work, flip_work); 402 struct radeon_device *rdev = work->rdev; 403 struct drm_device *dev = rdev->ddev; 404 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 405 406 struct drm_crtc *crtc = &radeon_crtc->base; 407 unsigned long flags; 408 int r; 409 int vpos, hpos; 410 411 down_read(&rdev->exclusive_lock); 412 if (work->fence) { 413 struct radeon_fence *fence; 414 415 fence = to_radeon_fence(work->fence); 416 if (fence && fence->rdev == rdev) { 417 r = radeon_fence_wait(fence, false); 418 if (r == -EDEADLK) { 419 up_read(&rdev->exclusive_lock); 420 do { 421 r = radeon_gpu_reset(rdev); 422 } while (r == -EAGAIN); 423 down_read(&rdev->exclusive_lock); 424 } 425 } else 426 r = dma_fence_wait(work->fence, false); 427 428 if (r) 429 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 430 431 /* We continue with the page flip even if we failed to wait on 432 * the fence, otherwise the DRM core and userspace will be 433 * confused about which BO the CRTC is scanning out 434 */ 435 436 dma_fence_put(work->fence); 437 work->fence = NULL; 438 } 439 440 /* Wait until we're out of the vertical blank period before the one 441 * targeted by the flip. Always wait on pre DCE4 to avoid races with 442 * flip completion handling from vblank irq, as these old asics don't 443 * have reliable pageflip completion interrupts. 444 */ 445 while (radeon_crtc->enabled && 446 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 447 &vpos, &hpos, NULL, NULL, 448 &crtc->hwmode) 449 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 450 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 451 (!ASIC_IS_AVIVO(rdev) || 452 ((int) (work->target_vblank - 453 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0))) 454 usleep_range(1000, 2000); 455 456 /* We borrow the event spin lock for protecting flip_status */ 457 spin_lock_irqsave(&crtc->dev->event_lock, flags); 458 459 /* set the proper interrupt */ 460 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 461 462 /* do the flip (mmio) */ 463 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 464 465 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 466 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 467 up_read(&rdev->exclusive_lock); 468 } 469 470 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 471 struct drm_framebuffer *fb, 472 struct drm_pending_vblank_event *event, 473 uint32_t page_flip_flags, 474 uint32_t target, 475 struct drm_modeset_acquire_ctx *ctx) 476 { 477 struct drm_device *dev = crtc->dev; 478 struct radeon_device *rdev = dev->dev_private; 479 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 480 struct radeon_framebuffer *old_radeon_fb; 481 struct radeon_framebuffer *new_radeon_fb; 482 struct drm_gem_object *obj; 483 struct radeon_flip_work *work; 484 struct radeon_bo *new_rbo; 485 uint32_t tiling_flags, pitch_pixels; 486 uint64_t base; 487 unsigned long flags; 488 int r; 489 490 work = kzalloc(sizeof *work, GFP_KERNEL); 491 if (work == NULL) 492 return -ENOMEM; 493 494 INIT_WORK(&work->flip_work, radeon_flip_work_func); 495 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 496 497 work->rdev = rdev; 498 work->crtc_id = radeon_crtc->crtc_id; 499 work->event = event; 500 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 501 502 /* schedule unpin of the old buffer */ 503 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 504 obj = old_radeon_fb->obj; 505 506 /* take a reference to the old object */ 507 drm_gem_object_get(obj); 508 work->old_rbo = gem_to_radeon_bo(obj); 509 510 new_radeon_fb = to_radeon_framebuffer(fb); 511 obj = new_radeon_fb->obj; 512 new_rbo = gem_to_radeon_bo(obj); 513 514 /* pin the new buffer */ 515 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 516 work->old_rbo, new_rbo); 517 518 r = radeon_bo_reserve(new_rbo, false); 519 if (unlikely(r != 0)) { 520 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 521 goto cleanup; 522 } 523 /* Only 27 bit offset for legacy CRTC */ 524 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 525 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 526 if (unlikely(r != 0)) { 527 radeon_bo_unreserve(new_rbo); 528 r = -EINVAL; 529 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 530 goto cleanup; 531 } 532 work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 533 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 534 radeon_bo_unreserve(new_rbo); 535 536 if (!ASIC_IS_AVIVO(rdev)) { 537 /* crtc offset is from display base addr not FB location */ 538 base -= radeon_crtc->legacy_display_base_addr; 539 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 540 541 if (tiling_flags & RADEON_TILING_MACRO) { 542 if (ASIC_IS_R300(rdev)) { 543 base &= ~0x7ff; 544 } else { 545 int byteshift = fb->format->cpp[0] * 8 >> 4; 546 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 547 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 548 } 549 } else { 550 int offset = crtc->y * pitch_pixels + crtc->x; 551 switch (fb->format->cpp[0] * 8) { 552 case 8: 553 default: 554 offset *= 1; 555 break; 556 case 15: 557 case 16: 558 offset *= 2; 559 break; 560 case 24: 561 offset *= 3; 562 break; 563 case 32: 564 offset *= 4; 565 break; 566 } 567 base += offset; 568 } 569 base &= ~7; 570 } 571 work->base = base; 572 work->target_vblank = target - drm_crtc_vblank_count(crtc) + 573 dev->driver->get_vblank_counter(dev, work->crtc_id); 574 575 /* We borrow the event spin lock for protecting flip_work */ 576 spin_lock_irqsave(&crtc->dev->event_lock, flags); 577 578 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 579 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 580 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 581 r = -EBUSY; 582 goto pflip_cleanup; 583 } 584 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 585 radeon_crtc->flip_work = work; 586 587 /* update crtc fb */ 588 crtc->primary->fb = fb; 589 590 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 591 592 queue_work(radeon_crtc->flip_queue, &work->flip_work); 593 return 0; 594 595 pflip_cleanup: 596 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 597 DRM_ERROR("failed to reserve new rbo in error path\n"); 598 goto cleanup; 599 } 600 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 601 DRM_ERROR("failed to unpin new rbo in error path\n"); 602 } 603 radeon_bo_unreserve(new_rbo); 604 605 cleanup: 606 drm_gem_object_put_unlocked(&work->old_rbo->gem_base); 607 dma_fence_put(work->fence); 608 kfree(work); 609 return r; 610 } 611 612 static int 613 radeon_crtc_set_config(struct drm_mode_set *set, 614 struct drm_modeset_acquire_ctx *ctx) 615 { 616 struct drm_device *dev; 617 struct radeon_device *rdev; 618 struct drm_crtc *crtc; 619 bool active = false; 620 int ret; 621 622 if (!set || !set->crtc) 623 return -EINVAL; 624 625 dev = set->crtc->dev; 626 627 ret = pm_runtime_get_sync(dev->dev); 628 if (ret < 0) 629 return ret; 630 631 ret = drm_crtc_helper_set_config(set, ctx); 632 633 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 634 if (crtc->enabled) 635 active = true; 636 637 pm_runtime_mark_last_busy(dev->dev); 638 639 rdev = dev->dev_private; 640 /* if we have active crtcs and we don't have a power ref, 641 take the current one */ 642 if (active && !rdev->have_disp_power_ref) { 643 rdev->have_disp_power_ref = true; 644 return ret; 645 } 646 /* if we have no active crtcs, then drop the power ref 647 we got before */ 648 if (!active && rdev->have_disp_power_ref) { 649 pm_runtime_put_autosuspend(dev->dev); 650 rdev->have_disp_power_ref = false; 651 } 652 653 /* drop the power reference we got coming in here */ 654 pm_runtime_put_autosuspend(dev->dev); 655 return ret; 656 } 657 658 static const struct drm_crtc_funcs radeon_crtc_funcs = { 659 .cursor_set2 = radeon_crtc_cursor_set2, 660 .cursor_move = radeon_crtc_cursor_move, 661 .gamma_set = radeon_crtc_gamma_set, 662 .set_config = radeon_crtc_set_config, 663 .destroy = radeon_crtc_destroy, 664 .page_flip_target = radeon_crtc_page_flip_target, 665 }; 666 667 static void radeon_crtc_init(struct drm_device *dev, int index) 668 { 669 struct radeon_device *rdev = dev->dev_private; 670 struct radeon_crtc *radeon_crtc; 671 int i; 672 673 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 674 if (radeon_crtc == NULL) 675 return; 676 677 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 678 679 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 680 radeon_crtc->crtc_id = index; 681 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 682 rdev->mode_info.crtcs[index] = radeon_crtc; 683 684 if (rdev->family >= CHIP_BONAIRE) { 685 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 686 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 687 } else { 688 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 689 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 690 } 691 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 692 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 693 694 #if 0 695 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 696 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 697 radeon_crtc->mode_set.num_connectors = 0; 698 #endif 699 700 for (i = 0; i < 256; i++) { 701 radeon_crtc->lut_r[i] = i << 2; 702 radeon_crtc->lut_g[i] = i << 2; 703 radeon_crtc->lut_b[i] = i << 2; 704 } 705 706 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 707 radeon_atombios_init_crtc(dev, radeon_crtc); 708 else 709 radeon_legacy_init_crtc(dev, radeon_crtc); 710 } 711 712 static const char *encoder_names[38] = { 713 "NONE", 714 "INTERNAL_LVDS", 715 "INTERNAL_TMDS1", 716 "INTERNAL_TMDS2", 717 "INTERNAL_DAC1", 718 "INTERNAL_DAC2", 719 "INTERNAL_SDVOA", 720 "INTERNAL_SDVOB", 721 "SI170B", 722 "CH7303", 723 "CH7301", 724 "INTERNAL_DVO1", 725 "EXTERNAL_SDVOA", 726 "EXTERNAL_SDVOB", 727 "TITFP513", 728 "INTERNAL_LVTM1", 729 "VT1623", 730 "HDMI_SI1930", 731 "HDMI_INTERNAL", 732 "INTERNAL_KLDSCP_TMDS1", 733 "INTERNAL_KLDSCP_DVO1", 734 "INTERNAL_KLDSCP_DAC1", 735 "INTERNAL_KLDSCP_DAC2", 736 "SI178", 737 "MVPU_FPGA", 738 "INTERNAL_DDI", 739 "VT1625", 740 "HDMI_SI1932", 741 "DP_AN9801", 742 "DP_DP501", 743 "INTERNAL_UNIPHY", 744 "INTERNAL_KLDSCP_LVTMA", 745 "INTERNAL_UNIPHY1", 746 "INTERNAL_UNIPHY2", 747 "NUTMEG", 748 "TRAVIS", 749 "INTERNAL_VCE", 750 "INTERNAL_UNIPHY3", 751 }; 752 753 static const char *hpd_names[6] = { 754 "HPD1", 755 "HPD2", 756 "HPD3", 757 "HPD4", 758 "HPD5", 759 "HPD6", 760 }; 761 762 static void radeon_print_display_setup(struct drm_device *dev) 763 { 764 struct drm_connector *connector; 765 struct radeon_connector *radeon_connector; 766 struct drm_encoder *encoder; 767 struct radeon_encoder *radeon_encoder; 768 uint32_t devices; 769 int i = 0; 770 771 DRM_INFO("Radeon Display Connectors\n"); 772 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 773 radeon_connector = to_radeon_connector(connector); 774 DRM_INFO("Connector %d:\n", i); 775 DRM_INFO(" %s\n", connector->name); 776 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 777 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 778 if (radeon_connector->ddc_bus) { 779 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 780 radeon_connector->ddc_bus->rec.mask_clk_reg, 781 radeon_connector->ddc_bus->rec.mask_data_reg, 782 radeon_connector->ddc_bus->rec.a_clk_reg, 783 radeon_connector->ddc_bus->rec.a_data_reg, 784 radeon_connector->ddc_bus->rec.en_clk_reg, 785 radeon_connector->ddc_bus->rec.en_data_reg, 786 radeon_connector->ddc_bus->rec.y_clk_reg, 787 radeon_connector->ddc_bus->rec.y_data_reg); 788 if (radeon_connector->router.ddc_valid) 789 DRM_INFO(" DDC Router 0x%x/0x%x\n", 790 radeon_connector->router.ddc_mux_control_pin, 791 radeon_connector->router.ddc_mux_state); 792 if (radeon_connector->router.cd_valid) 793 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 794 radeon_connector->router.cd_mux_control_pin, 795 radeon_connector->router.cd_mux_state); 796 } else { 797 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 798 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 799 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 800 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 801 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 802 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 803 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 804 } 805 DRM_INFO(" Encoders:\n"); 806 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 807 radeon_encoder = to_radeon_encoder(encoder); 808 devices = radeon_encoder->devices & radeon_connector->devices; 809 if (devices) { 810 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 811 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 812 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 813 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 814 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 815 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 816 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 817 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 818 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 819 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 820 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 821 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 822 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 823 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 824 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 825 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 826 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 827 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 828 if (devices & ATOM_DEVICE_TV1_SUPPORT) 829 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 830 if (devices & ATOM_DEVICE_CV_SUPPORT) 831 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 832 } 833 } 834 i++; 835 } 836 } 837 838 static bool radeon_setup_enc_conn(struct drm_device *dev) 839 { 840 struct radeon_device *rdev = dev->dev_private; 841 bool ret = false; 842 843 if (rdev->bios) { 844 if (rdev->is_atom_bios) { 845 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 846 if (ret == false) 847 ret = radeon_get_atom_connector_info_from_object_table(dev); 848 } else { 849 ret = radeon_get_legacy_connector_info_from_bios(dev); 850 if (ret == false) 851 ret = radeon_get_legacy_connector_info_from_table(dev); 852 } 853 } else { 854 if (!ASIC_IS_AVIVO(rdev)) 855 ret = radeon_get_legacy_connector_info_from_table(dev); 856 } 857 if (ret) { 858 radeon_setup_encoder_clones(dev); 859 radeon_print_display_setup(dev); 860 } 861 862 return ret; 863 } 864 865 /* avivo */ 866 867 /** 868 * avivo_reduce_ratio - fractional number reduction 869 * 870 * @nom: nominator 871 * @den: denominator 872 * @nom_min: minimum value for nominator 873 * @den_min: minimum value for denominator 874 * 875 * Find the greatest common divisor and apply it on both nominator and 876 * denominator, but make nominator and denominator are at least as large 877 * as their minimum values. 878 */ 879 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 880 unsigned nom_min, unsigned den_min) 881 { 882 unsigned tmp; 883 884 /* reduce the numbers to a simpler ratio */ 885 tmp = gcd(*nom, *den); 886 *nom /= tmp; 887 *den /= tmp; 888 889 /* make sure nominator is large enough */ 890 if (*nom < nom_min) { 891 tmp = DIV_ROUND_UP(nom_min, *nom); 892 *nom *= tmp; 893 *den *= tmp; 894 } 895 896 /* make sure the denominator is large enough */ 897 if (*den < den_min) { 898 tmp = DIV_ROUND_UP(den_min, *den); 899 *nom *= tmp; 900 *den *= tmp; 901 } 902 } 903 904 /** 905 * avivo_get_fb_ref_div - feedback and ref divider calculation 906 * 907 * @nom: nominator 908 * @den: denominator 909 * @post_div: post divider 910 * @fb_div_max: feedback divider maximum 911 * @ref_div_max: reference divider maximum 912 * @fb_div: resulting feedback divider 913 * @ref_div: resulting reference divider 914 * 915 * Calculate feedback and reference divider for a given post divider. Makes 916 * sure we stay within the limits. 917 */ 918 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 919 unsigned fb_div_max, unsigned ref_div_max, 920 unsigned *fb_div, unsigned *ref_div) 921 { 922 /* limit reference * post divider to a maximum */ 923 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 924 925 /* get matching reference and feedback divider */ 926 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 927 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 928 929 /* limit fb divider to its maximum */ 930 if (*fb_div > fb_div_max) { 931 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 932 *fb_div = fb_div_max; 933 } 934 } 935 936 /** 937 * radeon_compute_pll_avivo - compute PLL paramaters 938 * 939 * @pll: information about the PLL 940 * @dot_clock_p: resulting pixel clock 941 * fb_div_p: resulting feedback divider 942 * frac_fb_div_p: fractional part of the feedback divider 943 * ref_div_p: resulting reference divider 944 * post_div_p: resulting reference divider 945 * 946 * Try to calculate the PLL parameters to generate the given frequency: 947 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 948 */ 949 void radeon_compute_pll_avivo(struct radeon_pll *pll, 950 u32 freq, 951 u32 *dot_clock_p, 952 u32 *fb_div_p, 953 u32 *frac_fb_div_p, 954 u32 *ref_div_p, 955 u32 *post_div_p) 956 { 957 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 958 freq : freq / 10; 959 960 unsigned fb_div_min, fb_div_max, fb_div; 961 unsigned post_div_min, post_div_max, post_div; 962 unsigned ref_div_min, ref_div_max, ref_div; 963 unsigned post_div_best, diff_best; 964 unsigned nom, den; 965 966 /* determine allowed feedback divider range */ 967 fb_div_min = pll->min_feedback_div; 968 fb_div_max = pll->max_feedback_div; 969 970 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 971 fb_div_min *= 10; 972 fb_div_max *= 10; 973 } 974 975 /* determine allowed ref divider range */ 976 if (pll->flags & RADEON_PLL_USE_REF_DIV) 977 ref_div_min = pll->reference_div; 978 else 979 ref_div_min = pll->min_ref_div; 980 981 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 982 pll->flags & RADEON_PLL_USE_REF_DIV) 983 ref_div_max = pll->reference_div; 984 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 985 /* fix for problems on RS880 */ 986 ref_div_max = min(pll->max_ref_div, 7u); 987 else 988 ref_div_max = pll->max_ref_div; 989 990 /* determine allowed post divider range */ 991 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 992 post_div_min = pll->post_div; 993 post_div_max = pll->post_div; 994 } else { 995 unsigned vco_min, vco_max; 996 997 if (pll->flags & RADEON_PLL_IS_LCD) { 998 vco_min = pll->lcd_pll_out_min; 999 vco_max = pll->lcd_pll_out_max; 1000 } else { 1001 vco_min = pll->pll_out_min; 1002 vco_max = pll->pll_out_max; 1003 } 1004 1005 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1006 vco_min *= 10; 1007 vco_max *= 10; 1008 } 1009 1010 post_div_min = vco_min / target_clock; 1011 if ((target_clock * post_div_min) < vco_min) 1012 ++post_div_min; 1013 if (post_div_min < pll->min_post_div) 1014 post_div_min = pll->min_post_div; 1015 1016 post_div_max = vco_max / target_clock; 1017 if ((target_clock * post_div_max) > vco_max) 1018 --post_div_max; 1019 if (post_div_max > pll->max_post_div) 1020 post_div_max = pll->max_post_div; 1021 } 1022 1023 /* represent the searched ratio as fractional number */ 1024 nom = target_clock; 1025 den = pll->reference_freq; 1026 1027 /* reduce the numbers to a simpler ratio */ 1028 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1029 1030 /* now search for a post divider */ 1031 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1032 post_div_best = post_div_min; 1033 else 1034 post_div_best = post_div_max; 1035 diff_best = ~0; 1036 1037 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1038 unsigned diff; 1039 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1040 ref_div_max, &fb_div, &ref_div); 1041 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1042 (ref_div * post_div)); 1043 1044 if (diff < diff_best || (diff == diff_best && 1045 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1046 1047 post_div_best = post_div; 1048 diff_best = diff; 1049 } 1050 } 1051 post_div = post_div_best; 1052 1053 /* get the feedback and reference divider for the optimal value */ 1054 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1055 &fb_div, &ref_div); 1056 1057 /* reduce the numbers to a simpler ratio once more */ 1058 /* this also makes sure that the reference divider is large enough */ 1059 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1060 1061 /* avoid high jitter with small fractional dividers */ 1062 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1063 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1064 if (fb_div < fb_div_min) { 1065 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1066 fb_div *= tmp; 1067 ref_div *= tmp; 1068 } 1069 } 1070 1071 /* and finally save the result */ 1072 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1073 *fb_div_p = fb_div / 10; 1074 *frac_fb_div_p = fb_div % 10; 1075 } else { 1076 *fb_div_p = fb_div; 1077 *frac_fb_div_p = 0; 1078 } 1079 1080 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1081 (pll->reference_freq * *frac_fb_div_p)) / 1082 (ref_div * post_div * 10); 1083 *ref_div_p = ref_div; 1084 *post_div_p = post_div; 1085 1086 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1087 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1088 ref_div, post_div); 1089 } 1090 1091 /* pre-avivo */ 1092 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1093 { 1094 uint64_t mod; 1095 1096 n += d / 2; 1097 1098 mod = do_div(n, d); 1099 return n; 1100 } 1101 1102 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1103 uint64_t freq, 1104 uint32_t *dot_clock_p, 1105 uint32_t *fb_div_p, 1106 uint32_t *frac_fb_div_p, 1107 uint32_t *ref_div_p, 1108 uint32_t *post_div_p) 1109 { 1110 uint32_t min_ref_div = pll->min_ref_div; 1111 uint32_t max_ref_div = pll->max_ref_div; 1112 uint32_t min_post_div = pll->min_post_div; 1113 uint32_t max_post_div = pll->max_post_div; 1114 uint32_t min_fractional_feed_div = 0; 1115 uint32_t max_fractional_feed_div = 0; 1116 uint32_t best_vco = pll->best_vco; 1117 uint32_t best_post_div = 1; 1118 uint32_t best_ref_div = 1; 1119 uint32_t best_feedback_div = 1; 1120 uint32_t best_frac_feedback_div = 0; 1121 uint32_t best_freq = -1; 1122 uint32_t best_error = 0xffffffff; 1123 uint32_t best_vco_diff = 1; 1124 uint32_t post_div; 1125 u32 pll_out_min, pll_out_max; 1126 1127 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1128 freq = freq * 1000; 1129 1130 if (pll->flags & RADEON_PLL_IS_LCD) { 1131 pll_out_min = pll->lcd_pll_out_min; 1132 pll_out_max = pll->lcd_pll_out_max; 1133 } else { 1134 pll_out_min = pll->pll_out_min; 1135 pll_out_max = pll->pll_out_max; 1136 } 1137 1138 if (pll_out_min > 64800) 1139 pll_out_min = 64800; 1140 1141 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1142 min_ref_div = max_ref_div = pll->reference_div; 1143 else { 1144 while (min_ref_div < max_ref_div-1) { 1145 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1146 uint32_t pll_in = pll->reference_freq / mid; 1147 if (pll_in < pll->pll_in_min) 1148 max_ref_div = mid; 1149 else if (pll_in > pll->pll_in_max) 1150 min_ref_div = mid; 1151 else 1152 break; 1153 } 1154 } 1155 1156 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1157 min_post_div = max_post_div = pll->post_div; 1158 1159 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1160 min_fractional_feed_div = pll->min_frac_feedback_div; 1161 max_fractional_feed_div = pll->max_frac_feedback_div; 1162 } 1163 1164 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1165 uint32_t ref_div; 1166 1167 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1168 continue; 1169 1170 /* legacy radeons only have a few post_divs */ 1171 if (pll->flags & RADEON_PLL_LEGACY) { 1172 if ((post_div == 5) || 1173 (post_div == 7) || 1174 (post_div == 9) || 1175 (post_div == 10) || 1176 (post_div == 11) || 1177 (post_div == 13) || 1178 (post_div == 14) || 1179 (post_div == 15)) 1180 continue; 1181 } 1182 1183 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1184 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1185 uint32_t pll_in = pll->reference_freq / ref_div; 1186 uint32_t min_feed_div = pll->min_feedback_div; 1187 uint32_t max_feed_div = pll->max_feedback_div + 1; 1188 1189 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1190 continue; 1191 1192 while (min_feed_div < max_feed_div) { 1193 uint32_t vco; 1194 uint32_t min_frac_feed_div = min_fractional_feed_div; 1195 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1196 uint32_t frac_feedback_div; 1197 uint64_t tmp; 1198 1199 feedback_div = (min_feed_div + max_feed_div) / 2; 1200 1201 tmp = (uint64_t)pll->reference_freq * feedback_div; 1202 vco = radeon_div(tmp, ref_div); 1203 1204 if (vco < pll_out_min) { 1205 min_feed_div = feedback_div + 1; 1206 continue; 1207 } else if (vco > pll_out_max) { 1208 max_feed_div = feedback_div; 1209 continue; 1210 } 1211 1212 while (min_frac_feed_div < max_frac_feed_div) { 1213 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1214 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1215 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1216 current_freq = radeon_div(tmp, ref_div * post_div); 1217 1218 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1219 if (freq < current_freq) 1220 error = 0xffffffff; 1221 else 1222 error = freq - current_freq; 1223 } else 1224 error = abs(current_freq - freq); 1225 vco_diff = abs(vco - best_vco); 1226 1227 if ((best_vco == 0 && error < best_error) || 1228 (best_vco != 0 && 1229 ((best_error > 100 && error < best_error - 100) || 1230 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1231 best_post_div = post_div; 1232 best_ref_div = ref_div; 1233 best_feedback_div = feedback_div; 1234 best_frac_feedback_div = frac_feedback_div; 1235 best_freq = current_freq; 1236 best_error = error; 1237 best_vco_diff = vco_diff; 1238 } else if (current_freq == freq) { 1239 if (best_freq == -1) { 1240 best_post_div = post_div; 1241 best_ref_div = ref_div; 1242 best_feedback_div = feedback_div; 1243 best_frac_feedback_div = frac_feedback_div; 1244 best_freq = current_freq; 1245 best_error = error; 1246 best_vco_diff = vco_diff; 1247 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1248 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1249 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1250 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1251 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1252 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1253 best_post_div = post_div; 1254 best_ref_div = ref_div; 1255 best_feedback_div = feedback_div; 1256 best_frac_feedback_div = frac_feedback_div; 1257 best_freq = current_freq; 1258 best_error = error; 1259 best_vco_diff = vco_diff; 1260 } 1261 } 1262 if (current_freq < freq) 1263 min_frac_feed_div = frac_feedback_div + 1; 1264 else 1265 max_frac_feed_div = frac_feedback_div; 1266 } 1267 if (current_freq < freq) 1268 min_feed_div = feedback_div + 1; 1269 else 1270 max_feed_div = feedback_div; 1271 } 1272 } 1273 } 1274 1275 *dot_clock_p = best_freq / 10000; 1276 *fb_div_p = best_feedback_div; 1277 *frac_fb_div_p = best_frac_feedback_div; 1278 *ref_div_p = best_ref_div; 1279 *post_div_p = best_post_div; 1280 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1281 (long long)freq, 1282 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1283 best_ref_div, best_post_div); 1284 1285 } 1286 1287 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1288 { 1289 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1290 1291 drm_gem_object_put_unlocked(radeon_fb->obj); 1292 drm_framebuffer_cleanup(fb); 1293 kfree(radeon_fb); 1294 } 1295 1296 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1297 struct drm_file *file_priv, 1298 unsigned int *handle) 1299 { 1300 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1301 1302 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1303 } 1304 1305 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1306 .destroy = radeon_user_framebuffer_destroy, 1307 .create_handle = radeon_user_framebuffer_create_handle, 1308 }; 1309 1310 int 1311 radeon_framebuffer_init(struct drm_device *dev, 1312 struct radeon_framebuffer *rfb, 1313 const struct drm_mode_fb_cmd2 *mode_cmd, 1314 struct drm_gem_object *obj) 1315 { 1316 int ret; 1317 rfb->obj = obj; 1318 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1319 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1320 if (ret) { 1321 rfb->obj = NULL; 1322 return ret; 1323 } 1324 return 0; 1325 } 1326 1327 static struct drm_framebuffer * 1328 radeon_user_framebuffer_create(struct drm_device *dev, 1329 struct drm_file *file_priv, 1330 const struct drm_mode_fb_cmd2 *mode_cmd) 1331 { 1332 struct drm_gem_object *obj; 1333 struct radeon_framebuffer *radeon_fb; 1334 int ret; 1335 1336 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1337 if (obj == NULL) { 1338 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1339 "can't create framebuffer\n", mode_cmd->handles[0]); 1340 return ERR_PTR(-ENOENT); 1341 } 1342 1343 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1344 if (obj->import_attach) { 1345 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1346 return ERR_PTR(-EINVAL); 1347 } 1348 1349 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1350 if (radeon_fb == NULL) { 1351 drm_gem_object_put_unlocked(obj); 1352 return ERR_PTR(-ENOMEM); 1353 } 1354 1355 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1356 if (ret) { 1357 kfree(radeon_fb); 1358 drm_gem_object_put_unlocked(obj); 1359 return ERR_PTR(ret); 1360 } 1361 1362 return &radeon_fb->base; 1363 } 1364 1365 static void radeon_output_poll_changed(struct drm_device *dev) 1366 { 1367 struct radeon_device *rdev = dev->dev_private; 1368 radeon_fb_output_poll_changed(rdev); 1369 } 1370 1371 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1372 .fb_create = radeon_user_framebuffer_create, 1373 .output_poll_changed = radeon_output_poll_changed 1374 }; 1375 1376 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1377 { { 0, "driver" }, 1378 { 1, "bios" }, 1379 }; 1380 1381 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1382 { { TV_STD_NTSC, "ntsc" }, 1383 { TV_STD_PAL, "pal" }, 1384 { TV_STD_PAL_M, "pal-m" }, 1385 { TV_STD_PAL_60, "pal-60" }, 1386 { TV_STD_NTSC_J, "ntsc-j" }, 1387 { TV_STD_SCART_PAL, "scart-pal" }, 1388 { TV_STD_PAL_CN, "pal-cn" }, 1389 { TV_STD_SECAM, "secam" }, 1390 }; 1391 1392 static const struct drm_prop_enum_list radeon_underscan_enum_list[] = 1393 { { UNDERSCAN_OFF, "off" }, 1394 { UNDERSCAN_ON, "on" }, 1395 { UNDERSCAN_AUTO, "auto" }, 1396 }; 1397 1398 static const struct drm_prop_enum_list radeon_audio_enum_list[] = 1399 { { RADEON_AUDIO_DISABLE, "off" }, 1400 { RADEON_AUDIO_ENABLE, "on" }, 1401 { RADEON_AUDIO_AUTO, "auto" }, 1402 }; 1403 1404 /* XXX support different dither options? spatial, temporal, both, etc. */ 1405 static const struct drm_prop_enum_list radeon_dither_enum_list[] = 1406 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1407 { RADEON_FMT_DITHER_ENABLE, "on" }, 1408 }; 1409 1410 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1411 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1412 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1413 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1414 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1415 }; 1416 1417 static int radeon_modeset_create_props(struct radeon_device *rdev) 1418 { 1419 int sz; 1420 1421 if (rdev->is_atom_bios) { 1422 rdev->mode_info.coherent_mode_property = 1423 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1424 if (!rdev->mode_info.coherent_mode_property) 1425 return -ENOMEM; 1426 } 1427 1428 if (!ASIC_IS_AVIVO(rdev)) { 1429 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1430 rdev->mode_info.tmds_pll_property = 1431 drm_property_create_enum(rdev->ddev, 0, 1432 "tmds_pll", 1433 radeon_tmds_pll_enum_list, sz); 1434 } 1435 1436 rdev->mode_info.load_detect_property = 1437 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1438 if (!rdev->mode_info.load_detect_property) 1439 return -ENOMEM; 1440 1441 drm_mode_create_scaling_mode_property(rdev->ddev); 1442 1443 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1444 rdev->mode_info.tv_std_property = 1445 drm_property_create_enum(rdev->ddev, 0, 1446 "tv standard", 1447 radeon_tv_std_enum_list, sz); 1448 1449 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1450 rdev->mode_info.underscan_property = 1451 drm_property_create_enum(rdev->ddev, 0, 1452 "underscan", 1453 radeon_underscan_enum_list, sz); 1454 1455 rdev->mode_info.underscan_hborder_property = 1456 drm_property_create_range(rdev->ddev, 0, 1457 "underscan hborder", 0, 128); 1458 if (!rdev->mode_info.underscan_hborder_property) 1459 return -ENOMEM; 1460 1461 rdev->mode_info.underscan_vborder_property = 1462 drm_property_create_range(rdev->ddev, 0, 1463 "underscan vborder", 0, 128); 1464 if (!rdev->mode_info.underscan_vborder_property) 1465 return -ENOMEM; 1466 1467 sz = ARRAY_SIZE(radeon_audio_enum_list); 1468 rdev->mode_info.audio_property = 1469 drm_property_create_enum(rdev->ddev, 0, 1470 "audio", 1471 radeon_audio_enum_list, sz); 1472 1473 sz = ARRAY_SIZE(radeon_dither_enum_list); 1474 rdev->mode_info.dither_property = 1475 drm_property_create_enum(rdev->ddev, 0, 1476 "dither", 1477 radeon_dither_enum_list, sz); 1478 1479 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1480 rdev->mode_info.output_csc_property = 1481 drm_property_create_enum(rdev->ddev, 0, 1482 "output_csc", 1483 radeon_output_csc_enum_list, sz); 1484 1485 return 0; 1486 } 1487 1488 void radeon_update_display_priority(struct radeon_device *rdev) 1489 { 1490 /* adjustment options for the display watermarks */ 1491 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1492 /* set display priority to high for r3xx, rv515 chips 1493 * this avoids flickering due to underflow to the 1494 * display controllers during heavy acceleration. 1495 * Don't force high on rs4xx igp chips as it seems to 1496 * affect the sound card. See kernel bug 15982. 1497 */ 1498 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1499 !(rdev->flags & RADEON_IS_IGP)) 1500 rdev->disp_priority = 2; 1501 else 1502 rdev->disp_priority = 0; 1503 } else 1504 rdev->disp_priority = radeon_disp_priority; 1505 1506 } 1507 1508 /* 1509 * Allocate hdmi structs and determine register offsets 1510 */ 1511 static void radeon_afmt_init(struct radeon_device *rdev) 1512 { 1513 int i; 1514 1515 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1516 rdev->mode_info.afmt[i] = NULL; 1517 1518 if (ASIC_IS_NODCE(rdev)) { 1519 /* nothing to do */ 1520 } else if (ASIC_IS_DCE4(rdev)) { 1521 static uint32_t eg_offsets[] = { 1522 EVERGREEN_CRTC0_REGISTER_OFFSET, 1523 EVERGREEN_CRTC1_REGISTER_OFFSET, 1524 EVERGREEN_CRTC2_REGISTER_OFFSET, 1525 EVERGREEN_CRTC3_REGISTER_OFFSET, 1526 EVERGREEN_CRTC4_REGISTER_OFFSET, 1527 EVERGREEN_CRTC5_REGISTER_OFFSET, 1528 0x13830 - 0x7030, 1529 }; 1530 int num_afmt; 1531 1532 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1533 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1534 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1535 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1536 if (ASIC_IS_DCE8(rdev)) 1537 num_afmt = 7; 1538 else if (ASIC_IS_DCE6(rdev)) 1539 num_afmt = 6; 1540 else if (ASIC_IS_DCE5(rdev)) 1541 num_afmt = 6; 1542 else if (ASIC_IS_DCE41(rdev)) 1543 num_afmt = 2; 1544 else /* DCE4 */ 1545 num_afmt = 6; 1546 1547 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1548 for (i = 0; i < num_afmt; i++) { 1549 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1550 if (rdev->mode_info.afmt[i]) { 1551 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1552 rdev->mode_info.afmt[i]->id = i; 1553 } 1554 } 1555 } else if (ASIC_IS_DCE3(rdev)) { 1556 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1557 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1558 if (rdev->mode_info.afmt[0]) { 1559 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1560 rdev->mode_info.afmt[0]->id = 0; 1561 } 1562 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1563 if (rdev->mode_info.afmt[1]) { 1564 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1565 rdev->mode_info.afmt[1]->id = 1; 1566 } 1567 } else if (ASIC_IS_DCE2(rdev)) { 1568 /* DCE2 has at least 1 routable audio block */ 1569 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1570 if (rdev->mode_info.afmt[0]) { 1571 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1572 rdev->mode_info.afmt[0]->id = 0; 1573 } 1574 /* r6xx has 2 routable audio blocks */ 1575 if (rdev->family >= CHIP_R600) { 1576 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1577 if (rdev->mode_info.afmt[1]) { 1578 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1579 rdev->mode_info.afmt[1]->id = 1; 1580 } 1581 } 1582 } 1583 } 1584 1585 static void radeon_afmt_fini(struct radeon_device *rdev) 1586 { 1587 int i; 1588 1589 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1590 kfree(rdev->mode_info.afmt[i]); 1591 rdev->mode_info.afmt[i] = NULL; 1592 } 1593 } 1594 1595 int radeon_modeset_init(struct radeon_device *rdev) 1596 { 1597 int i; 1598 int ret; 1599 1600 drm_mode_config_init(rdev->ddev); 1601 rdev->mode_info.mode_config_initialized = true; 1602 1603 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1604 1605 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1606 rdev->ddev->mode_config.async_page_flip = true; 1607 1608 if (ASIC_IS_DCE5(rdev)) { 1609 rdev->ddev->mode_config.max_width = 16384; 1610 rdev->ddev->mode_config.max_height = 16384; 1611 } else if (ASIC_IS_AVIVO(rdev)) { 1612 rdev->ddev->mode_config.max_width = 8192; 1613 rdev->ddev->mode_config.max_height = 8192; 1614 } else { 1615 rdev->ddev->mode_config.max_width = 4096; 1616 rdev->ddev->mode_config.max_height = 4096; 1617 } 1618 1619 rdev->ddev->mode_config.preferred_depth = 24; 1620 rdev->ddev->mode_config.prefer_shadow = 1; 1621 1622 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1623 1624 ret = radeon_modeset_create_props(rdev); 1625 if (ret) { 1626 return ret; 1627 } 1628 1629 /* init i2c buses */ 1630 radeon_i2c_init(rdev); 1631 1632 /* check combios for a valid hardcoded EDID - Sun servers */ 1633 if (!rdev->is_atom_bios) { 1634 /* check for hardcoded EDID in BIOS */ 1635 radeon_combios_check_hardcoded_edid(rdev); 1636 } 1637 1638 /* allocate crtcs */ 1639 for (i = 0; i < rdev->num_crtc; i++) { 1640 radeon_crtc_init(rdev->ddev, i); 1641 } 1642 1643 /* okay we should have all the bios connectors */ 1644 ret = radeon_setup_enc_conn(rdev->ddev); 1645 if (!ret) { 1646 return ret; 1647 } 1648 1649 /* init dig PHYs, disp eng pll */ 1650 if (rdev->is_atom_bios) { 1651 radeon_atom_encoder_init(rdev); 1652 radeon_atom_disp_eng_pll_init(rdev); 1653 } 1654 1655 /* initialize hpd */ 1656 radeon_hpd_init(rdev); 1657 1658 /* setup afmt */ 1659 radeon_afmt_init(rdev); 1660 1661 radeon_fbdev_init(rdev); 1662 drm_kms_helper_poll_init(rdev->ddev); 1663 1664 /* do pm late init */ 1665 ret = radeon_pm_late_init(rdev); 1666 1667 return 0; 1668 } 1669 1670 void radeon_modeset_fini(struct radeon_device *rdev) 1671 { 1672 if (rdev->mode_info.mode_config_initialized) { 1673 drm_kms_helper_poll_fini(rdev->ddev); 1674 radeon_hpd_fini(rdev); 1675 drm_crtc_force_disable_all(rdev->ddev); 1676 radeon_fbdev_fini(rdev); 1677 radeon_afmt_fini(rdev); 1678 drm_mode_config_cleanup(rdev->ddev); 1679 rdev->mode_info.mode_config_initialized = false; 1680 } 1681 1682 kfree(rdev->mode_info.bios_hardcoded_edid); 1683 1684 /* free i2c buses */ 1685 radeon_i2c_fini(rdev); 1686 } 1687 1688 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1689 { 1690 /* try and guess if this is a tv or a monitor */ 1691 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1692 (mode->vdisplay == 576) || /* 576p */ 1693 (mode->vdisplay == 720) || /* 720p */ 1694 (mode->vdisplay == 1080)) /* 1080p */ 1695 return true; 1696 else 1697 return false; 1698 } 1699 1700 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1701 const struct drm_display_mode *mode, 1702 struct drm_display_mode *adjusted_mode) 1703 { 1704 struct drm_device *dev = crtc->dev; 1705 struct radeon_device *rdev = dev->dev_private; 1706 struct drm_encoder *encoder; 1707 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1708 struct radeon_encoder *radeon_encoder; 1709 struct drm_connector *connector; 1710 struct radeon_connector *radeon_connector; 1711 bool first = true; 1712 u32 src_v = 1, dst_v = 1; 1713 u32 src_h = 1, dst_h = 1; 1714 1715 radeon_crtc->h_border = 0; 1716 radeon_crtc->v_border = 0; 1717 1718 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1719 if (encoder->crtc != crtc) 1720 continue; 1721 radeon_encoder = to_radeon_encoder(encoder); 1722 connector = radeon_get_connector_for_encoder(encoder); 1723 radeon_connector = to_radeon_connector(connector); 1724 1725 if (first) { 1726 /* set scaling */ 1727 if (radeon_encoder->rmx_type == RMX_OFF) 1728 radeon_crtc->rmx_type = RMX_OFF; 1729 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1730 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1731 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1732 else 1733 radeon_crtc->rmx_type = RMX_OFF; 1734 /* copy native mode */ 1735 memcpy(&radeon_crtc->native_mode, 1736 &radeon_encoder->native_mode, 1737 sizeof(struct drm_display_mode)); 1738 src_v = crtc->mode.vdisplay; 1739 dst_v = radeon_crtc->native_mode.vdisplay; 1740 src_h = crtc->mode.hdisplay; 1741 dst_h = radeon_crtc->native_mode.hdisplay; 1742 1743 /* fix up for overscan on hdmi */ 1744 if (ASIC_IS_AVIVO(rdev) && 1745 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1746 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1747 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1748 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1749 is_hdtv_mode(mode)))) { 1750 if (radeon_encoder->underscan_hborder != 0) 1751 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1752 else 1753 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1754 if (radeon_encoder->underscan_vborder != 0) 1755 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1756 else 1757 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1758 radeon_crtc->rmx_type = RMX_FULL; 1759 src_v = crtc->mode.vdisplay; 1760 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1761 src_h = crtc->mode.hdisplay; 1762 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1763 } 1764 first = false; 1765 } else { 1766 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1767 /* WARNING: Right now this can't happen but 1768 * in the future we need to check that scaling 1769 * are consistent across different encoder 1770 * (ie all encoder can work with the same 1771 * scaling). 1772 */ 1773 DRM_ERROR("Scaling not consistent across encoder.\n"); 1774 return false; 1775 } 1776 } 1777 } 1778 if (radeon_crtc->rmx_type != RMX_OFF) { 1779 fixed20_12 a, b; 1780 a.full = dfixed_const(src_v); 1781 b.full = dfixed_const(dst_v); 1782 radeon_crtc->vsc.full = dfixed_div(a, b); 1783 a.full = dfixed_const(src_h); 1784 b.full = dfixed_const(dst_h); 1785 radeon_crtc->hsc.full = dfixed_div(a, b); 1786 } else { 1787 radeon_crtc->vsc.full = dfixed_const(1); 1788 radeon_crtc->hsc.full = dfixed_const(1); 1789 } 1790 return true; 1791 } 1792 1793 /* 1794 * Retrieve current video scanout position of crtc on a given gpu, and 1795 * an optional accurate timestamp of when query happened. 1796 * 1797 * \param dev Device to query. 1798 * \param crtc Crtc to query. 1799 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1800 * For driver internal use only also supports these flags: 1801 * 1802 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1803 * of a fudged earlier start of vblank. 1804 * 1805 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1806 * fudged earlier start of vblank in *vpos and the distance 1807 * to true start of vblank in *hpos. 1808 * 1809 * \param *vpos Location where vertical scanout position should be stored. 1810 * \param *hpos Location where horizontal scanout position should go. 1811 * \param *stime Target location for timestamp taken immediately before 1812 * scanout position query. Can be NULL to skip timestamp. 1813 * \param *etime Target location for timestamp taken immediately after 1814 * scanout position query. Can be NULL to skip timestamp. 1815 * 1816 * Returns vpos as a positive number while in active scanout area. 1817 * Returns vpos as a negative number inside vblank, counting the number 1818 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1819 * until start of active scanout / end of vblank." 1820 * 1821 * \return Flags, or'ed together as follows: 1822 * 1823 * DRM_SCANOUTPOS_VALID = Query successful. 1824 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1825 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1826 * this flag means that returned position may be offset by a constant but 1827 * unknown small number of scanlines wrt. real scanout position. 1828 * 1829 */ 1830 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1831 unsigned int flags, int *vpos, int *hpos, 1832 ktime_t *stime, ktime_t *etime, 1833 const struct drm_display_mode *mode) 1834 { 1835 u32 stat_crtc = 0, vbl = 0, position = 0; 1836 int vbl_start, vbl_end, vtotal, ret = 0; 1837 bool in_vbl = true; 1838 1839 struct radeon_device *rdev = dev->dev_private; 1840 1841 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1842 1843 /* Get optional system timestamp before query. */ 1844 if (stime) 1845 *stime = ktime_get(); 1846 1847 if (ASIC_IS_DCE4(rdev)) { 1848 if (pipe == 0) { 1849 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1850 EVERGREEN_CRTC0_REGISTER_OFFSET); 1851 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1852 EVERGREEN_CRTC0_REGISTER_OFFSET); 1853 ret |= DRM_SCANOUTPOS_VALID; 1854 } 1855 if (pipe == 1) { 1856 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1857 EVERGREEN_CRTC1_REGISTER_OFFSET); 1858 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1859 EVERGREEN_CRTC1_REGISTER_OFFSET); 1860 ret |= DRM_SCANOUTPOS_VALID; 1861 } 1862 if (pipe == 2) { 1863 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1864 EVERGREEN_CRTC2_REGISTER_OFFSET); 1865 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1866 EVERGREEN_CRTC2_REGISTER_OFFSET); 1867 ret |= DRM_SCANOUTPOS_VALID; 1868 } 1869 if (pipe == 3) { 1870 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1871 EVERGREEN_CRTC3_REGISTER_OFFSET); 1872 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1873 EVERGREEN_CRTC3_REGISTER_OFFSET); 1874 ret |= DRM_SCANOUTPOS_VALID; 1875 } 1876 if (pipe == 4) { 1877 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1878 EVERGREEN_CRTC4_REGISTER_OFFSET); 1879 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1880 EVERGREEN_CRTC4_REGISTER_OFFSET); 1881 ret |= DRM_SCANOUTPOS_VALID; 1882 } 1883 if (pipe == 5) { 1884 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1885 EVERGREEN_CRTC5_REGISTER_OFFSET); 1886 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1887 EVERGREEN_CRTC5_REGISTER_OFFSET); 1888 ret |= DRM_SCANOUTPOS_VALID; 1889 } 1890 } else if (ASIC_IS_AVIVO(rdev)) { 1891 if (pipe == 0) { 1892 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1893 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1894 ret |= DRM_SCANOUTPOS_VALID; 1895 } 1896 if (pipe == 1) { 1897 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1898 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1899 ret |= DRM_SCANOUTPOS_VALID; 1900 } 1901 } else { 1902 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1903 if (pipe == 0) { 1904 /* Assume vbl_end == 0, get vbl_start from 1905 * upper 16 bits. 1906 */ 1907 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1908 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1909 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1910 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1911 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1912 if (!(stat_crtc & 1)) 1913 in_vbl = false; 1914 1915 ret |= DRM_SCANOUTPOS_VALID; 1916 } 1917 if (pipe == 1) { 1918 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1919 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1920 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1921 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1922 if (!(stat_crtc & 1)) 1923 in_vbl = false; 1924 1925 ret |= DRM_SCANOUTPOS_VALID; 1926 } 1927 } 1928 1929 /* Get optional system timestamp after query. */ 1930 if (etime) 1931 *etime = ktime_get(); 1932 1933 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1934 1935 /* Decode into vertical and horizontal scanout position. */ 1936 *vpos = position & 0x1fff; 1937 *hpos = (position >> 16) & 0x1fff; 1938 1939 /* Valid vblank area boundaries from gpu retrieved? */ 1940 if (vbl > 0) { 1941 /* Yes: Decode. */ 1942 ret |= DRM_SCANOUTPOS_ACCURATE; 1943 vbl_start = vbl & 0x1fff; 1944 vbl_end = (vbl >> 16) & 0x1fff; 1945 } 1946 else { 1947 /* No: Fake something reasonable which gives at least ok results. */ 1948 vbl_start = mode->crtc_vdisplay; 1949 vbl_end = 0; 1950 } 1951 1952 /* Called from driver internal vblank counter query code? */ 1953 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1954 /* Caller wants distance from real vbl_start in *hpos */ 1955 *hpos = *vpos - vbl_start; 1956 } 1957 1958 /* Fudge vblank to start a few scanlines earlier to handle the 1959 * problem that vblank irqs fire a few scanlines before start 1960 * of vblank. Some driver internal callers need the true vblank 1961 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1962 * 1963 * The cause of the "early" vblank irq is that the irq is triggered 1964 * by the line buffer logic when the line buffer read position enters 1965 * the vblank, whereas our crtc scanout position naturally lags the 1966 * line buffer read position. 1967 */ 1968 if (!(flags & USE_REAL_VBLANKSTART)) 1969 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1970 1971 /* Test scanout position against vblank region. */ 1972 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1973 in_vbl = false; 1974 1975 /* In vblank? */ 1976 if (in_vbl) 1977 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1978 1979 /* Called from driver internal vblank counter query code? */ 1980 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1981 /* Caller wants distance from fudged earlier vbl_start */ 1982 *vpos -= vbl_start; 1983 return ret; 1984 } 1985 1986 /* Check if inside vblank area and apply corrective offsets: 1987 * vpos will then be >=0 in video scanout area, but negative 1988 * within vblank area, counting down the number of lines until 1989 * start of scanout. 1990 */ 1991 1992 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1993 if (in_vbl && (*vpos >= vbl_start)) { 1994 vtotal = mode->crtc_vtotal; 1995 *vpos = *vpos - vtotal; 1996 } 1997 1998 /* Correct for shifted end of vbl at vbl_end. */ 1999 *vpos = *vpos - vbl_end; 2000 2001 return ret; 2002 } 2003