1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include <linux/pm_runtime.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include <drm/drm_edid.h> 37 38 #include <linux/gcd.h> 39 40 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 41 { 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 43 struct drm_device *dev = crtc->dev; 44 struct radeon_device *rdev = dev->dev_private; 45 int i; 46 47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 49 50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 53 54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 57 58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 59 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 61 62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 63 for (i = 0; i < 256; i++) { 64 WREG32(AVIVO_DC_LUT_30_COLOR, 65 (radeon_crtc->lut_r[i] << 20) | 66 (radeon_crtc->lut_g[i] << 10) | 67 (radeon_crtc->lut_b[i] << 0)); 68 } 69 70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 72 } 73 74 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 75 { 76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 77 struct drm_device *dev = crtc->dev; 78 struct radeon_device *rdev = dev->dev_private; 79 int i; 80 81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 83 84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 87 88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 91 92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 94 95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 96 for (i = 0; i < 256; i++) { 97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 98 (radeon_crtc->lut_r[i] << 20) | 99 (radeon_crtc->lut_g[i] << 10) | 100 (radeon_crtc->lut_b[i] << 0)); 101 } 102 } 103 104 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 105 { 106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 107 struct drm_device *dev = crtc->dev; 108 struct radeon_device *rdev = dev->dev_private; 109 int i; 110 111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 112 113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 117 NI_GRPH_PRESCALE_BYPASS); 118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 119 NI_OVL_PRESCALE_BYPASS); 120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 123 124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 125 126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 129 130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 133 134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 136 137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 138 for (i = 0; i < 256; i++) { 139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 140 (radeon_crtc->lut_r[i] << 20) | 141 (radeon_crtc->lut_g[i] << 10) | 142 (radeon_crtc->lut_b[i] << 0)); 143 } 144 145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 161 if (ASIC_IS_DCE8(rdev)) { 162 /* XXX this only needs to be programmed once per crtc at startup, 163 * not sure where the best place for it is 164 */ 165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 166 CIK_CURSOR_ALPHA_BLND_ENA); 167 } 168 } 169 170 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 171 { 172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 173 struct drm_device *dev = crtc->dev; 174 struct radeon_device *rdev = dev->dev_private; 175 int i; 176 uint32_t dac2_cntl; 177 178 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 179 if (radeon_crtc->crtc_id == 0) 180 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 181 else 182 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 183 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 184 185 WREG8(RADEON_PALETTE_INDEX, 0); 186 for (i = 0; i < 256; i++) { 187 WREG32(RADEON_PALETTE_30_DATA, 188 (radeon_crtc->lut_r[i] << 20) | 189 (radeon_crtc->lut_g[i] << 10) | 190 (radeon_crtc->lut_b[i] << 0)); 191 } 192 } 193 194 void radeon_crtc_load_lut(struct drm_crtc *crtc) 195 { 196 struct drm_device *dev = crtc->dev; 197 struct radeon_device *rdev = dev->dev_private; 198 199 if (!crtc->enabled) 200 return; 201 202 if (ASIC_IS_DCE5(rdev)) 203 dce5_crtc_load_lut(crtc); 204 else if (ASIC_IS_DCE4(rdev)) 205 dce4_crtc_load_lut(crtc); 206 else if (ASIC_IS_AVIVO(rdev)) 207 avivo_crtc_load_lut(crtc); 208 else 209 legacy_crtc_load_lut(crtc); 210 } 211 212 /** Sets the color ramps on behalf of fbcon */ 213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 214 u16 blue, int regno) 215 { 216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 217 218 radeon_crtc->lut_r[regno] = red >> 6; 219 radeon_crtc->lut_g[regno] = green >> 6; 220 radeon_crtc->lut_b[regno] = blue >> 6; 221 } 222 223 /** Gets the color ramps on behalf of fbcon */ 224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 225 u16 *blue, int regno) 226 { 227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 228 229 *red = radeon_crtc->lut_r[regno] << 6; 230 *green = radeon_crtc->lut_g[regno] << 6; 231 *blue = radeon_crtc->lut_b[regno] << 6; 232 } 233 234 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 235 u16 *blue, uint32_t start, uint32_t size) 236 { 237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 238 int end = (start + size > 256) ? 256 : start + size, i; 239 240 /* userspace palettes are always correct as is */ 241 for (i = start; i < end; i++) { 242 radeon_crtc->lut_r[i] = red[i] >> 6; 243 radeon_crtc->lut_g[i] = green[i] >> 6; 244 radeon_crtc->lut_b[i] = blue[i] >> 6; 245 } 246 radeon_crtc_load_lut(crtc); 247 } 248 249 static void radeon_crtc_destroy(struct drm_crtc *crtc) 250 { 251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 252 253 drm_crtc_cleanup(crtc); 254 destroy_workqueue(radeon_crtc->flip_queue); 255 kfree(radeon_crtc); 256 } 257 258 /** 259 * radeon_unpin_work_func - unpin old buffer object 260 * 261 * @__work - kernel work item 262 * 263 * Unpin the old frame buffer object outside of the interrupt handler 264 */ 265 static void radeon_unpin_work_func(struct work_struct *__work) 266 { 267 struct radeon_flip_work *work = 268 container_of(__work, struct radeon_flip_work, unpin_work); 269 int r; 270 271 /* unpin of the old buffer */ 272 r = radeon_bo_reserve(work->old_rbo, false); 273 if (likely(r == 0)) { 274 r = radeon_bo_unpin(work->old_rbo); 275 if (unlikely(r != 0)) { 276 DRM_ERROR("failed to unpin buffer after flip\n"); 277 } 278 radeon_bo_unreserve(work->old_rbo); 279 } else 280 DRM_ERROR("failed to reserve buffer after flip\n"); 281 282 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 283 kfree(work); 284 } 285 286 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 287 { 288 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 289 unsigned long flags; 290 u32 update_pending; 291 int vpos, hpos; 292 293 /* can happen during initialization */ 294 if (radeon_crtc == NULL) 295 return; 296 297 /* Skip the pageflip completion check below (based on polling) on 298 * asics which reliably support hw pageflip completion irqs. pflip 299 * irqs are a reliable and race-free method of handling pageflip 300 * completion detection. A use_pflipirq module parameter < 2 allows 301 * to override this in case of asics with faulty pflip irqs. 302 * A module parameter of 0 would only use this polling based path, 303 * a parameter of 1 would use pflip irq only as a backup to this 304 * path, as in Linux 3.16. 305 */ 306 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 307 return; 308 309 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 310 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 311 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 312 "RADEON_FLIP_SUBMITTED(%d)\n", 313 radeon_crtc->flip_status, 314 RADEON_FLIP_SUBMITTED); 315 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 316 return; 317 } 318 319 update_pending = radeon_page_flip_pending(rdev, crtc_id); 320 321 /* Has the pageflip already completed in crtc, or is it certain 322 * to complete in this vblank? 323 */ 324 if (update_pending && 325 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, 326 crtc_id, 327 USE_REAL_VBLANKSTART, 328 &vpos, &hpos, NULL, NULL, 329 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 330 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || 331 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { 332 /* crtc didn't flip in this target vblank interval, 333 * but flip is pending in crtc. Based on the current 334 * scanout position we know that the current frame is 335 * (nearly) complete and the flip will (likely) 336 * complete before the start of the next frame. 337 */ 338 update_pending = 0; 339 } 340 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 341 if (!update_pending) 342 radeon_crtc_handle_flip(rdev, crtc_id); 343 } 344 345 /** 346 * radeon_crtc_handle_flip - page flip completed 347 * 348 * @rdev: radeon device pointer 349 * @crtc_id: crtc number this event is for 350 * 351 * Called when we are sure that a page flip for this crtc is completed. 352 */ 353 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 354 { 355 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 356 struct radeon_flip_work *work; 357 unsigned long flags; 358 359 /* this can happen at init */ 360 if (radeon_crtc == NULL) 361 return; 362 363 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 364 work = radeon_crtc->flip_work; 365 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 366 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 367 "RADEON_FLIP_SUBMITTED(%d)\n", 368 radeon_crtc->flip_status, 369 RADEON_FLIP_SUBMITTED); 370 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 371 return; 372 } 373 374 /* Pageflip completed. Clean up. */ 375 radeon_crtc->flip_status = RADEON_FLIP_NONE; 376 radeon_crtc->flip_work = NULL; 377 378 /* wakeup userspace */ 379 if (work->event) 380 drm_send_vblank_event(rdev->ddev, crtc_id, work->event); 381 382 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 383 384 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 385 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 386 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 387 } 388 389 /** 390 * radeon_flip_work_func - page flip framebuffer 391 * 392 * @work - kernel work item 393 * 394 * Wait for the buffer object to become idle and do the actual page flip 395 */ 396 static void radeon_flip_work_func(struct work_struct *__work) 397 { 398 struct radeon_flip_work *work = 399 container_of(__work, struct radeon_flip_work, flip_work); 400 struct radeon_device *rdev = work->rdev; 401 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 402 403 struct drm_crtc *crtc = &radeon_crtc->base; 404 unsigned long flags; 405 int r; 406 int vpos, hpos, stat, min_udelay = 0; 407 unsigned repcnt = 4; 408 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 409 410 down_read(&rdev->exclusive_lock); 411 if (work->fence) { 412 struct radeon_fence *fence; 413 414 fence = to_radeon_fence(work->fence); 415 if (fence && fence->rdev == rdev) { 416 r = radeon_fence_wait(fence, false); 417 if (r == -EDEADLK) { 418 up_read(&rdev->exclusive_lock); 419 do { 420 r = radeon_gpu_reset(rdev); 421 } while (r == -EAGAIN); 422 down_read(&rdev->exclusive_lock); 423 } 424 } else 425 r = fence_wait(work->fence, false); 426 427 if (r) 428 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 429 430 /* We continue with the page flip even if we failed to wait on 431 * the fence, otherwise the DRM core and userspace will be 432 * confused about which BO the CRTC is scanning out 433 */ 434 435 fence_put(work->fence); 436 work->fence = NULL; 437 } 438 439 /* We borrow the event spin lock for protecting flip_status */ 440 spin_lock_irqsave(&crtc->dev->event_lock, flags); 441 442 /* set the proper interrupt */ 443 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 444 445 /* If this happens to execute within the "virtually extended" vblank 446 * interval before the start of the real vblank interval then it needs 447 * to delay programming the mmio flip until the real vblank is entered. 448 * This prevents completing a flip too early due to the way we fudge 449 * our vblank counter and vblank timestamps in order to work around the 450 * problem that the hw fires vblank interrupts before actual start of 451 * vblank (when line buffer refilling is done for a frame). It 452 * complements the fudging logic in radeon_get_crtc_scanoutpos() for 453 * timestamping and radeon_get_vblank_counter_kms() for vblank counts. 454 * 455 * In practice this won't execute very often unless on very fast 456 * machines because the time window for this to happen is very small. 457 */ 458 while (radeon_crtc->enabled && --repcnt) { 459 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 460 * start in hpos, and to the "fudged earlier" vblank start in 461 * vpos. 462 */ 463 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id, 464 GET_DISTANCE_TO_VBLANKSTART, 465 &vpos, &hpos, NULL, NULL, 466 &crtc->hwmode); 467 468 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 469 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 470 !(vpos >= 0 && hpos <= 0)) 471 break; 472 473 /* Sleep at least until estimated real start of hw vblank */ 474 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 475 if (min_udelay > vblank->framedur_ns / 2000) { 476 /* Don't wait ridiculously long - something is wrong */ 477 repcnt = 0; 478 break; 479 } 480 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 481 usleep_range(min_udelay, 2 * min_udelay); 482 spin_lock_irqsave(&crtc->dev->event_lock, flags); 483 }; 484 485 if (!repcnt) 486 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 487 "framedur %d, linedur %d, stat %d, vpos %d, " 488 "hpos %d\n", work->crtc_id, min_udelay, 489 vblank->framedur_ns / 1000, 490 vblank->linedur_ns / 1000, stat, vpos, hpos); 491 492 /* do the flip (mmio) */ 493 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); 494 495 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 496 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 497 up_read(&rdev->exclusive_lock); 498 } 499 500 static int radeon_crtc_page_flip(struct drm_crtc *crtc, 501 struct drm_framebuffer *fb, 502 struct drm_pending_vblank_event *event, 503 uint32_t page_flip_flags) 504 { 505 struct drm_device *dev = crtc->dev; 506 struct radeon_device *rdev = dev->dev_private; 507 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 508 struct radeon_framebuffer *old_radeon_fb; 509 struct radeon_framebuffer *new_radeon_fb; 510 struct drm_gem_object *obj; 511 struct radeon_flip_work *work; 512 struct radeon_bo *new_rbo; 513 uint32_t tiling_flags, pitch_pixels; 514 uint64_t base; 515 unsigned long flags; 516 int r; 517 518 work = kzalloc(sizeof *work, GFP_KERNEL); 519 if (work == NULL) 520 return -ENOMEM; 521 522 INIT_WORK(&work->flip_work, radeon_flip_work_func); 523 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 524 525 work->rdev = rdev; 526 work->crtc_id = radeon_crtc->crtc_id; 527 work->event = event; 528 529 /* schedule unpin of the old buffer */ 530 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb); 531 obj = old_radeon_fb->obj; 532 533 /* take a reference to the old object */ 534 drm_gem_object_reference(obj); 535 work->old_rbo = gem_to_radeon_bo(obj); 536 537 new_radeon_fb = to_radeon_framebuffer(fb); 538 obj = new_radeon_fb->obj; 539 new_rbo = gem_to_radeon_bo(obj); 540 541 /* pin the new buffer */ 542 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 543 work->old_rbo, new_rbo); 544 545 r = radeon_bo_reserve(new_rbo, false); 546 if (unlikely(r != 0)) { 547 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 548 goto cleanup; 549 } 550 /* Only 27 bit offset for legacy CRTC */ 551 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 552 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 553 if (unlikely(r != 0)) { 554 radeon_bo_unreserve(new_rbo); 555 r = -EINVAL; 556 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 557 goto cleanup; 558 } 559 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 560 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 561 radeon_bo_unreserve(new_rbo); 562 563 if (!ASIC_IS_AVIVO(rdev)) { 564 /* crtc offset is from display base addr not FB location */ 565 base -= radeon_crtc->legacy_display_base_addr; 566 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8); 567 568 if (tiling_flags & RADEON_TILING_MACRO) { 569 if (ASIC_IS_R300(rdev)) { 570 base &= ~0x7ff; 571 } else { 572 int byteshift = fb->bits_per_pixel >> 4; 573 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 574 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 575 } 576 } else { 577 int offset = crtc->y * pitch_pixels + crtc->x; 578 switch (fb->bits_per_pixel) { 579 case 8: 580 default: 581 offset *= 1; 582 break; 583 case 15: 584 case 16: 585 offset *= 2; 586 break; 587 case 24: 588 offset *= 3; 589 break; 590 case 32: 591 offset *= 4; 592 break; 593 } 594 base += offset; 595 } 596 base &= ~7; 597 } 598 work->base = base; 599 600 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 601 if (r) { 602 DRM_ERROR("failed to get vblank before flip\n"); 603 goto pflip_cleanup; 604 } 605 606 /* We borrow the event spin lock for protecting flip_work */ 607 spin_lock_irqsave(&crtc->dev->event_lock, flags); 608 609 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 610 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 611 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 612 r = -EBUSY; 613 goto vblank_cleanup; 614 } 615 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 616 radeon_crtc->flip_work = work; 617 618 /* update crtc fb */ 619 crtc->primary->fb = fb; 620 621 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 622 623 queue_work(radeon_crtc->flip_queue, &work->flip_work); 624 return 0; 625 626 vblank_cleanup: 627 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); 628 629 pflip_cleanup: 630 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 631 DRM_ERROR("failed to reserve new rbo in error path\n"); 632 goto cleanup; 633 } 634 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 635 DRM_ERROR("failed to unpin new rbo in error path\n"); 636 } 637 radeon_bo_unreserve(new_rbo); 638 639 cleanup: 640 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 641 fence_put(work->fence); 642 kfree(work); 643 return r; 644 } 645 646 static int 647 radeon_crtc_set_config(struct drm_mode_set *set) 648 { 649 struct drm_device *dev; 650 struct radeon_device *rdev; 651 struct drm_crtc *crtc; 652 bool active = false; 653 int ret; 654 655 if (!set || !set->crtc) 656 return -EINVAL; 657 658 dev = set->crtc->dev; 659 660 ret = pm_runtime_get_sync(dev->dev); 661 if (ret < 0) 662 return ret; 663 664 ret = drm_crtc_helper_set_config(set); 665 666 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 667 if (crtc->enabled) 668 active = true; 669 670 pm_runtime_mark_last_busy(dev->dev); 671 672 rdev = dev->dev_private; 673 /* if we have active crtcs and we don't have a power ref, 674 take the current one */ 675 if (active && !rdev->have_disp_power_ref) { 676 rdev->have_disp_power_ref = true; 677 return ret; 678 } 679 /* if we have no active crtcs, then drop the power ref 680 we got before */ 681 if (!active && rdev->have_disp_power_ref) { 682 pm_runtime_put_autosuspend(dev->dev); 683 rdev->have_disp_power_ref = false; 684 } 685 686 /* drop the power reference we got coming in here */ 687 pm_runtime_put_autosuspend(dev->dev); 688 return ret; 689 } 690 static const struct drm_crtc_funcs radeon_crtc_funcs = { 691 .cursor_set2 = radeon_crtc_cursor_set2, 692 .cursor_move = radeon_crtc_cursor_move, 693 .gamma_set = radeon_crtc_gamma_set, 694 .set_config = radeon_crtc_set_config, 695 .destroy = radeon_crtc_destroy, 696 .page_flip = radeon_crtc_page_flip, 697 }; 698 699 static void radeon_crtc_init(struct drm_device *dev, int index) 700 { 701 struct radeon_device *rdev = dev->dev_private; 702 struct radeon_crtc *radeon_crtc; 703 int i; 704 705 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 706 if (radeon_crtc == NULL) 707 return; 708 709 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 710 711 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 712 radeon_crtc->crtc_id = index; 713 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); 714 rdev->mode_info.crtcs[index] = radeon_crtc; 715 716 if (rdev->family >= CHIP_BONAIRE) { 717 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 718 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 719 } else { 720 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 721 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 722 } 723 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 724 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 725 726 #if 0 727 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 728 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 729 radeon_crtc->mode_set.num_connectors = 0; 730 #endif 731 732 for (i = 0; i < 256; i++) { 733 radeon_crtc->lut_r[i] = i << 2; 734 radeon_crtc->lut_g[i] = i << 2; 735 radeon_crtc->lut_b[i] = i << 2; 736 } 737 738 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 739 radeon_atombios_init_crtc(dev, radeon_crtc); 740 else 741 radeon_legacy_init_crtc(dev, radeon_crtc); 742 } 743 744 static const char *encoder_names[38] = { 745 "NONE", 746 "INTERNAL_LVDS", 747 "INTERNAL_TMDS1", 748 "INTERNAL_TMDS2", 749 "INTERNAL_DAC1", 750 "INTERNAL_DAC2", 751 "INTERNAL_SDVOA", 752 "INTERNAL_SDVOB", 753 "SI170B", 754 "CH7303", 755 "CH7301", 756 "INTERNAL_DVO1", 757 "EXTERNAL_SDVOA", 758 "EXTERNAL_SDVOB", 759 "TITFP513", 760 "INTERNAL_LVTM1", 761 "VT1623", 762 "HDMI_SI1930", 763 "HDMI_INTERNAL", 764 "INTERNAL_KLDSCP_TMDS1", 765 "INTERNAL_KLDSCP_DVO1", 766 "INTERNAL_KLDSCP_DAC1", 767 "INTERNAL_KLDSCP_DAC2", 768 "SI178", 769 "MVPU_FPGA", 770 "INTERNAL_DDI", 771 "VT1625", 772 "HDMI_SI1932", 773 "DP_AN9801", 774 "DP_DP501", 775 "INTERNAL_UNIPHY", 776 "INTERNAL_KLDSCP_LVTMA", 777 "INTERNAL_UNIPHY1", 778 "INTERNAL_UNIPHY2", 779 "NUTMEG", 780 "TRAVIS", 781 "INTERNAL_VCE", 782 "INTERNAL_UNIPHY3", 783 }; 784 785 static const char *hpd_names[6] = { 786 "HPD1", 787 "HPD2", 788 "HPD3", 789 "HPD4", 790 "HPD5", 791 "HPD6", 792 }; 793 794 static void radeon_print_display_setup(struct drm_device *dev) 795 { 796 struct drm_connector *connector; 797 struct radeon_connector *radeon_connector; 798 struct drm_encoder *encoder; 799 struct radeon_encoder *radeon_encoder; 800 uint32_t devices; 801 int i = 0; 802 803 DRM_INFO("Radeon Display Connectors\n"); 804 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 805 radeon_connector = to_radeon_connector(connector); 806 DRM_INFO("Connector %d:\n", i); 807 DRM_INFO(" %s\n", connector->name); 808 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 809 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 810 if (radeon_connector->ddc_bus) { 811 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 812 radeon_connector->ddc_bus->rec.mask_clk_reg, 813 radeon_connector->ddc_bus->rec.mask_data_reg, 814 radeon_connector->ddc_bus->rec.a_clk_reg, 815 radeon_connector->ddc_bus->rec.a_data_reg, 816 radeon_connector->ddc_bus->rec.en_clk_reg, 817 radeon_connector->ddc_bus->rec.en_data_reg, 818 radeon_connector->ddc_bus->rec.y_clk_reg, 819 radeon_connector->ddc_bus->rec.y_data_reg); 820 if (radeon_connector->router.ddc_valid) 821 DRM_INFO(" DDC Router 0x%x/0x%x\n", 822 radeon_connector->router.ddc_mux_control_pin, 823 radeon_connector->router.ddc_mux_state); 824 if (radeon_connector->router.cd_valid) 825 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 826 radeon_connector->router.cd_mux_control_pin, 827 radeon_connector->router.cd_mux_state); 828 } else { 829 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 830 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 831 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 832 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 833 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 834 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 835 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 836 } 837 DRM_INFO(" Encoders:\n"); 838 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 839 radeon_encoder = to_radeon_encoder(encoder); 840 devices = radeon_encoder->devices & radeon_connector->devices; 841 if (devices) { 842 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 843 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 844 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 845 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 846 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 847 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 848 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 849 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 850 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 851 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 852 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 853 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 854 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 855 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 856 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 857 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 858 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 859 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 860 if (devices & ATOM_DEVICE_TV1_SUPPORT) 861 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 862 if (devices & ATOM_DEVICE_CV_SUPPORT) 863 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 864 } 865 } 866 i++; 867 } 868 } 869 870 static bool radeon_setup_enc_conn(struct drm_device *dev) 871 { 872 struct radeon_device *rdev = dev->dev_private; 873 bool ret = false; 874 875 if (rdev->bios) { 876 if (rdev->is_atom_bios) { 877 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 878 if (ret == false) 879 ret = radeon_get_atom_connector_info_from_object_table(dev); 880 } else { 881 ret = radeon_get_legacy_connector_info_from_bios(dev); 882 if (ret == false) 883 ret = radeon_get_legacy_connector_info_from_table(dev); 884 } 885 } else { 886 if (!ASIC_IS_AVIVO(rdev)) 887 ret = radeon_get_legacy_connector_info_from_table(dev); 888 } 889 if (ret) { 890 radeon_setup_encoder_clones(dev); 891 radeon_print_display_setup(dev); 892 } 893 894 return ret; 895 } 896 897 /* avivo */ 898 899 /** 900 * avivo_reduce_ratio - fractional number reduction 901 * 902 * @nom: nominator 903 * @den: denominator 904 * @nom_min: minimum value for nominator 905 * @den_min: minimum value for denominator 906 * 907 * Find the greatest common divisor and apply it on both nominator and 908 * denominator, but make nominator and denominator are at least as large 909 * as their minimum values. 910 */ 911 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 912 unsigned nom_min, unsigned den_min) 913 { 914 unsigned tmp; 915 916 /* reduce the numbers to a simpler ratio */ 917 tmp = gcd(*nom, *den); 918 *nom /= tmp; 919 *den /= tmp; 920 921 /* make sure nominator is large enough */ 922 if (*nom < nom_min) { 923 tmp = DIV_ROUND_UP(nom_min, *nom); 924 *nom *= tmp; 925 *den *= tmp; 926 } 927 928 /* make sure the denominator is large enough */ 929 if (*den < den_min) { 930 tmp = DIV_ROUND_UP(den_min, *den); 931 *nom *= tmp; 932 *den *= tmp; 933 } 934 } 935 936 /** 937 * avivo_get_fb_ref_div - feedback and ref divider calculation 938 * 939 * @nom: nominator 940 * @den: denominator 941 * @post_div: post divider 942 * @fb_div_max: feedback divider maximum 943 * @ref_div_max: reference divider maximum 944 * @fb_div: resulting feedback divider 945 * @ref_div: resulting reference divider 946 * 947 * Calculate feedback and reference divider for a given post divider. Makes 948 * sure we stay within the limits. 949 */ 950 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 951 unsigned fb_div_max, unsigned ref_div_max, 952 unsigned *fb_div, unsigned *ref_div) 953 { 954 /* limit reference * post divider to a maximum */ 955 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 956 957 /* get matching reference and feedback divider */ 958 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 959 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 960 961 /* limit fb divider to its maximum */ 962 if (*fb_div > fb_div_max) { 963 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 964 *fb_div = fb_div_max; 965 } 966 } 967 968 /** 969 * radeon_compute_pll_avivo - compute PLL paramaters 970 * 971 * @pll: information about the PLL 972 * @dot_clock_p: resulting pixel clock 973 * fb_div_p: resulting feedback divider 974 * frac_fb_div_p: fractional part of the feedback divider 975 * ref_div_p: resulting reference divider 976 * post_div_p: resulting reference divider 977 * 978 * Try to calculate the PLL parameters to generate the given frequency: 979 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 980 */ 981 void radeon_compute_pll_avivo(struct radeon_pll *pll, 982 u32 freq, 983 u32 *dot_clock_p, 984 u32 *fb_div_p, 985 u32 *frac_fb_div_p, 986 u32 *ref_div_p, 987 u32 *post_div_p) 988 { 989 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 990 freq : freq / 10; 991 992 unsigned fb_div_min, fb_div_max, fb_div; 993 unsigned post_div_min, post_div_max, post_div; 994 unsigned ref_div_min, ref_div_max, ref_div; 995 unsigned post_div_best, diff_best; 996 unsigned nom, den; 997 998 /* determine allowed feedback divider range */ 999 fb_div_min = pll->min_feedback_div; 1000 fb_div_max = pll->max_feedback_div; 1001 1002 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1003 fb_div_min *= 10; 1004 fb_div_max *= 10; 1005 } 1006 1007 /* determine allowed ref divider range */ 1008 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1009 ref_div_min = pll->reference_div; 1010 else 1011 ref_div_min = pll->min_ref_div; 1012 1013 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 1014 pll->flags & RADEON_PLL_USE_REF_DIV) 1015 ref_div_max = pll->reference_div; 1016 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1017 /* fix for problems on RS880 */ 1018 ref_div_max = min(pll->max_ref_div, 7u); 1019 else 1020 ref_div_max = pll->max_ref_div; 1021 1022 /* determine allowed post divider range */ 1023 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 1024 post_div_min = pll->post_div; 1025 post_div_max = pll->post_div; 1026 } else { 1027 unsigned vco_min, vco_max; 1028 1029 if (pll->flags & RADEON_PLL_IS_LCD) { 1030 vco_min = pll->lcd_pll_out_min; 1031 vco_max = pll->lcd_pll_out_max; 1032 } else { 1033 vco_min = pll->pll_out_min; 1034 vco_max = pll->pll_out_max; 1035 } 1036 1037 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1038 vco_min *= 10; 1039 vco_max *= 10; 1040 } 1041 1042 post_div_min = vco_min / target_clock; 1043 if ((target_clock * post_div_min) < vco_min) 1044 ++post_div_min; 1045 if (post_div_min < pll->min_post_div) 1046 post_div_min = pll->min_post_div; 1047 1048 post_div_max = vco_max / target_clock; 1049 if ((target_clock * post_div_max) > vco_max) 1050 --post_div_max; 1051 if (post_div_max > pll->max_post_div) 1052 post_div_max = pll->max_post_div; 1053 } 1054 1055 /* represent the searched ratio as fractional number */ 1056 nom = target_clock; 1057 den = pll->reference_freq; 1058 1059 /* reduce the numbers to a simpler ratio */ 1060 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1061 1062 /* now search for a post divider */ 1063 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1064 post_div_best = post_div_min; 1065 else 1066 post_div_best = post_div_max; 1067 diff_best = ~0; 1068 1069 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1070 unsigned diff; 1071 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1072 ref_div_max, &fb_div, &ref_div); 1073 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1074 (ref_div * post_div)); 1075 1076 if (diff < diff_best || (diff == diff_best && 1077 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1078 1079 post_div_best = post_div; 1080 diff_best = diff; 1081 } 1082 } 1083 post_div = post_div_best; 1084 1085 /* get the feedback and reference divider for the optimal value */ 1086 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1087 &fb_div, &ref_div); 1088 1089 /* reduce the numbers to a simpler ratio once more */ 1090 /* this also makes sure that the reference divider is large enough */ 1091 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1092 1093 /* avoid high jitter with small fractional dividers */ 1094 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1095 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1096 if (fb_div < fb_div_min) { 1097 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1098 fb_div *= tmp; 1099 ref_div *= tmp; 1100 } 1101 } 1102 1103 /* and finally save the result */ 1104 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1105 *fb_div_p = fb_div / 10; 1106 *frac_fb_div_p = fb_div % 10; 1107 } else { 1108 *fb_div_p = fb_div; 1109 *frac_fb_div_p = 0; 1110 } 1111 1112 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1113 (pll->reference_freq * *frac_fb_div_p)) / 1114 (ref_div * post_div * 10); 1115 *ref_div_p = ref_div; 1116 *post_div_p = post_div; 1117 1118 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1119 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1120 ref_div, post_div); 1121 } 1122 1123 /* pre-avivo */ 1124 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1125 { 1126 uint64_t mod; 1127 1128 n += d / 2; 1129 1130 mod = do_div(n, d); 1131 return n; 1132 } 1133 1134 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1135 uint64_t freq, 1136 uint32_t *dot_clock_p, 1137 uint32_t *fb_div_p, 1138 uint32_t *frac_fb_div_p, 1139 uint32_t *ref_div_p, 1140 uint32_t *post_div_p) 1141 { 1142 uint32_t min_ref_div = pll->min_ref_div; 1143 uint32_t max_ref_div = pll->max_ref_div; 1144 uint32_t min_post_div = pll->min_post_div; 1145 uint32_t max_post_div = pll->max_post_div; 1146 uint32_t min_fractional_feed_div = 0; 1147 uint32_t max_fractional_feed_div = 0; 1148 uint32_t best_vco = pll->best_vco; 1149 uint32_t best_post_div = 1; 1150 uint32_t best_ref_div = 1; 1151 uint32_t best_feedback_div = 1; 1152 uint32_t best_frac_feedback_div = 0; 1153 uint32_t best_freq = -1; 1154 uint32_t best_error = 0xffffffff; 1155 uint32_t best_vco_diff = 1; 1156 uint32_t post_div; 1157 u32 pll_out_min, pll_out_max; 1158 1159 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1160 freq = freq * 1000; 1161 1162 if (pll->flags & RADEON_PLL_IS_LCD) { 1163 pll_out_min = pll->lcd_pll_out_min; 1164 pll_out_max = pll->lcd_pll_out_max; 1165 } else { 1166 pll_out_min = pll->pll_out_min; 1167 pll_out_max = pll->pll_out_max; 1168 } 1169 1170 if (pll_out_min > 64800) 1171 pll_out_min = 64800; 1172 1173 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1174 min_ref_div = max_ref_div = pll->reference_div; 1175 else { 1176 while (min_ref_div < max_ref_div-1) { 1177 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1178 uint32_t pll_in = pll->reference_freq / mid; 1179 if (pll_in < pll->pll_in_min) 1180 max_ref_div = mid; 1181 else if (pll_in > pll->pll_in_max) 1182 min_ref_div = mid; 1183 else 1184 break; 1185 } 1186 } 1187 1188 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1189 min_post_div = max_post_div = pll->post_div; 1190 1191 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1192 min_fractional_feed_div = pll->min_frac_feedback_div; 1193 max_fractional_feed_div = pll->max_frac_feedback_div; 1194 } 1195 1196 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1197 uint32_t ref_div; 1198 1199 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1200 continue; 1201 1202 /* legacy radeons only have a few post_divs */ 1203 if (pll->flags & RADEON_PLL_LEGACY) { 1204 if ((post_div == 5) || 1205 (post_div == 7) || 1206 (post_div == 9) || 1207 (post_div == 10) || 1208 (post_div == 11) || 1209 (post_div == 13) || 1210 (post_div == 14) || 1211 (post_div == 15)) 1212 continue; 1213 } 1214 1215 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1216 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1217 uint32_t pll_in = pll->reference_freq / ref_div; 1218 uint32_t min_feed_div = pll->min_feedback_div; 1219 uint32_t max_feed_div = pll->max_feedback_div + 1; 1220 1221 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1222 continue; 1223 1224 while (min_feed_div < max_feed_div) { 1225 uint32_t vco; 1226 uint32_t min_frac_feed_div = min_fractional_feed_div; 1227 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1228 uint32_t frac_feedback_div; 1229 uint64_t tmp; 1230 1231 feedback_div = (min_feed_div + max_feed_div) / 2; 1232 1233 tmp = (uint64_t)pll->reference_freq * feedback_div; 1234 vco = radeon_div(tmp, ref_div); 1235 1236 if (vco < pll_out_min) { 1237 min_feed_div = feedback_div + 1; 1238 continue; 1239 } else if (vco > pll_out_max) { 1240 max_feed_div = feedback_div; 1241 continue; 1242 } 1243 1244 while (min_frac_feed_div < max_frac_feed_div) { 1245 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1246 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1247 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1248 current_freq = radeon_div(tmp, ref_div * post_div); 1249 1250 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1251 if (freq < current_freq) 1252 error = 0xffffffff; 1253 else 1254 error = freq - current_freq; 1255 } else 1256 error = abs(current_freq - freq); 1257 vco_diff = abs(vco - best_vco); 1258 1259 if ((best_vco == 0 && error < best_error) || 1260 (best_vco != 0 && 1261 ((best_error > 100 && error < best_error - 100) || 1262 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1263 best_post_div = post_div; 1264 best_ref_div = ref_div; 1265 best_feedback_div = feedback_div; 1266 best_frac_feedback_div = frac_feedback_div; 1267 best_freq = current_freq; 1268 best_error = error; 1269 best_vco_diff = vco_diff; 1270 } else if (current_freq == freq) { 1271 if (best_freq == -1) { 1272 best_post_div = post_div; 1273 best_ref_div = ref_div; 1274 best_feedback_div = feedback_div; 1275 best_frac_feedback_div = frac_feedback_div; 1276 best_freq = current_freq; 1277 best_error = error; 1278 best_vco_diff = vco_diff; 1279 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1280 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1281 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1282 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1283 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1284 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1285 best_post_div = post_div; 1286 best_ref_div = ref_div; 1287 best_feedback_div = feedback_div; 1288 best_frac_feedback_div = frac_feedback_div; 1289 best_freq = current_freq; 1290 best_error = error; 1291 best_vco_diff = vco_diff; 1292 } 1293 } 1294 if (current_freq < freq) 1295 min_frac_feed_div = frac_feedback_div + 1; 1296 else 1297 max_frac_feed_div = frac_feedback_div; 1298 } 1299 if (current_freq < freq) 1300 min_feed_div = feedback_div + 1; 1301 else 1302 max_feed_div = feedback_div; 1303 } 1304 } 1305 } 1306 1307 *dot_clock_p = best_freq / 10000; 1308 *fb_div_p = best_feedback_div; 1309 *frac_fb_div_p = best_frac_feedback_div; 1310 *ref_div_p = best_ref_div; 1311 *post_div_p = best_post_div; 1312 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1313 (long long)freq, 1314 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1315 best_ref_div, best_post_div); 1316 1317 } 1318 1319 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) 1320 { 1321 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1322 1323 if (radeon_fb->obj) { 1324 drm_gem_object_unreference_unlocked(radeon_fb->obj); 1325 } 1326 drm_framebuffer_cleanup(fb); 1327 kfree(radeon_fb); 1328 } 1329 1330 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, 1331 struct drm_file *file_priv, 1332 unsigned int *handle) 1333 { 1334 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); 1335 1336 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); 1337 } 1338 1339 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1340 .destroy = radeon_user_framebuffer_destroy, 1341 .create_handle = radeon_user_framebuffer_create_handle, 1342 }; 1343 1344 int 1345 radeon_framebuffer_init(struct drm_device *dev, 1346 struct radeon_framebuffer *rfb, 1347 const struct drm_mode_fb_cmd2 *mode_cmd, 1348 struct drm_gem_object *obj) 1349 { 1350 int ret; 1351 rfb->obj = obj; 1352 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 1353 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); 1354 if (ret) { 1355 rfb->obj = NULL; 1356 return ret; 1357 } 1358 return 0; 1359 } 1360 1361 static struct drm_framebuffer * 1362 radeon_user_framebuffer_create(struct drm_device *dev, 1363 struct drm_file *file_priv, 1364 const struct drm_mode_fb_cmd2 *mode_cmd) 1365 { 1366 struct drm_gem_object *obj; 1367 struct radeon_framebuffer *radeon_fb; 1368 int ret; 1369 1370 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 1371 if (obj == NULL) { 1372 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1373 "can't create framebuffer\n", mode_cmd->handles[0]); 1374 return ERR_PTR(-ENOENT); 1375 } 1376 1377 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 1378 if (radeon_fb == NULL) { 1379 drm_gem_object_unreference_unlocked(obj); 1380 return ERR_PTR(-ENOMEM); 1381 } 1382 1383 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 1384 if (ret) { 1385 kfree(radeon_fb); 1386 drm_gem_object_unreference_unlocked(obj); 1387 return ERR_PTR(ret); 1388 } 1389 1390 return &radeon_fb->base; 1391 } 1392 1393 static void radeon_output_poll_changed(struct drm_device *dev) 1394 { 1395 struct radeon_device *rdev = dev->dev_private; 1396 radeon_fb_output_poll_changed(rdev); 1397 } 1398 1399 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1400 .fb_create = radeon_user_framebuffer_create, 1401 .output_poll_changed = radeon_output_poll_changed 1402 }; 1403 1404 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1405 { { 0, "driver" }, 1406 { 1, "bios" }, 1407 }; 1408 1409 static struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1410 { { TV_STD_NTSC, "ntsc" }, 1411 { TV_STD_PAL, "pal" }, 1412 { TV_STD_PAL_M, "pal-m" }, 1413 { TV_STD_PAL_60, "pal-60" }, 1414 { TV_STD_NTSC_J, "ntsc-j" }, 1415 { TV_STD_SCART_PAL, "scart-pal" }, 1416 { TV_STD_PAL_CN, "pal-cn" }, 1417 { TV_STD_SECAM, "secam" }, 1418 }; 1419 1420 static struct drm_prop_enum_list radeon_underscan_enum_list[] = 1421 { { UNDERSCAN_OFF, "off" }, 1422 { UNDERSCAN_ON, "on" }, 1423 { UNDERSCAN_AUTO, "auto" }, 1424 }; 1425 1426 static struct drm_prop_enum_list radeon_audio_enum_list[] = 1427 { { RADEON_AUDIO_DISABLE, "off" }, 1428 { RADEON_AUDIO_ENABLE, "on" }, 1429 { RADEON_AUDIO_AUTO, "auto" }, 1430 }; 1431 1432 /* XXX support different dither options? spatial, temporal, both, etc. */ 1433 static struct drm_prop_enum_list radeon_dither_enum_list[] = 1434 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1435 { RADEON_FMT_DITHER_ENABLE, "on" }, 1436 }; 1437 1438 static struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1439 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1440 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1441 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1442 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1443 }; 1444 1445 static int radeon_modeset_create_props(struct radeon_device *rdev) 1446 { 1447 int sz; 1448 1449 if (rdev->is_atom_bios) { 1450 rdev->mode_info.coherent_mode_property = 1451 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1452 if (!rdev->mode_info.coherent_mode_property) 1453 return -ENOMEM; 1454 } 1455 1456 if (!ASIC_IS_AVIVO(rdev)) { 1457 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1458 rdev->mode_info.tmds_pll_property = 1459 drm_property_create_enum(rdev->ddev, 0, 1460 "tmds_pll", 1461 radeon_tmds_pll_enum_list, sz); 1462 } 1463 1464 rdev->mode_info.load_detect_property = 1465 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1466 if (!rdev->mode_info.load_detect_property) 1467 return -ENOMEM; 1468 1469 drm_mode_create_scaling_mode_property(rdev->ddev); 1470 1471 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1472 rdev->mode_info.tv_std_property = 1473 drm_property_create_enum(rdev->ddev, 0, 1474 "tv standard", 1475 radeon_tv_std_enum_list, sz); 1476 1477 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1478 rdev->mode_info.underscan_property = 1479 drm_property_create_enum(rdev->ddev, 0, 1480 "underscan", 1481 radeon_underscan_enum_list, sz); 1482 1483 rdev->mode_info.underscan_hborder_property = 1484 drm_property_create_range(rdev->ddev, 0, 1485 "underscan hborder", 0, 128); 1486 if (!rdev->mode_info.underscan_hborder_property) 1487 return -ENOMEM; 1488 1489 rdev->mode_info.underscan_vborder_property = 1490 drm_property_create_range(rdev->ddev, 0, 1491 "underscan vborder", 0, 128); 1492 if (!rdev->mode_info.underscan_vborder_property) 1493 return -ENOMEM; 1494 1495 sz = ARRAY_SIZE(radeon_audio_enum_list); 1496 rdev->mode_info.audio_property = 1497 drm_property_create_enum(rdev->ddev, 0, 1498 "audio", 1499 radeon_audio_enum_list, sz); 1500 1501 sz = ARRAY_SIZE(radeon_dither_enum_list); 1502 rdev->mode_info.dither_property = 1503 drm_property_create_enum(rdev->ddev, 0, 1504 "dither", 1505 radeon_dither_enum_list, sz); 1506 1507 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1508 rdev->mode_info.output_csc_property = 1509 drm_property_create_enum(rdev->ddev, 0, 1510 "output_csc", 1511 radeon_output_csc_enum_list, sz); 1512 1513 return 0; 1514 } 1515 1516 void radeon_update_display_priority(struct radeon_device *rdev) 1517 { 1518 /* adjustment options for the display watermarks */ 1519 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1520 /* set display priority to high for r3xx, rv515 chips 1521 * this avoids flickering due to underflow to the 1522 * display controllers during heavy acceleration. 1523 * Don't force high on rs4xx igp chips as it seems to 1524 * affect the sound card. See kernel bug 15982. 1525 */ 1526 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1527 !(rdev->flags & RADEON_IS_IGP)) 1528 rdev->disp_priority = 2; 1529 else 1530 rdev->disp_priority = 0; 1531 } else 1532 rdev->disp_priority = radeon_disp_priority; 1533 1534 } 1535 1536 /* 1537 * Allocate hdmi structs and determine register offsets 1538 */ 1539 static void radeon_afmt_init(struct radeon_device *rdev) 1540 { 1541 int i; 1542 1543 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1544 rdev->mode_info.afmt[i] = NULL; 1545 1546 if (ASIC_IS_NODCE(rdev)) { 1547 /* nothing to do */ 1548 } else if (ASIC_IS_DCE4(rdev)) { 1549 static uint32_t eg_offsets[] = { 1550 EVERGREEN_CRTC0_REGISTER_OFFSET, 1551 EVERGREEN_CRTC1_REGISTER_OFFSET, 1552 EVERGREEN_CRTC2_REGISTER_OFFSET, 1553 EVERGREEN_CRTC3_REGISTER_OFFSET, 1554 EVERGREEN_CRTC4_REGISTER_OFFSET, 1555 EVERGREEN_CRTC5_REGISTER_OFFSET, 1556 0x13830 - 0x7030, 1557 }; 1558 int num_afmt; 1559 1560 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1561 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1562 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1563 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1564 if (ASIC_IS_DCE8(rdev)) 1565 num_afmt = 7; 1566 else if (ASIC_IS_DCE6(rdev)) 1567 num_afmt = 6; 1568 else if (ASIC_IS_DCE5(rdev)) 1569 num_afmt = 6; 1570 else if (ASIC_IS_DCE41(rdev)) 1571 num_afmt = 2; 1572 else /* DCE4 */ 1573 num_afmt = 6; 1574 1575 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1576 for (i = 0; i < num_afmt; i++) { 1577 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1578 if (rdev->mode_info.afmt[i]) { 1579 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1580 rdev->mode_info.afmt[i]->id = i; 1581 } 1582 } 1583 } else if (ASIC_IS_DCE3(rdev)) { 1584 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1585 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1586 if (rdev->mode_info.afmt[0]) { 1587 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1588 rdev->mode_info.afmt[0]->id = 0; 1589 } 1590 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1591 if (rdev->mode_info.afmt[1]) { 1592 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1593 rdev->mode_info.afmt[1]->id = 1; 1594 } 1595 } else if (ASIC_IS_DCE2(rdev)) { 1596 /* DCE2 has at least 1 routable audio block */ 1597 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1598 if (rdev->mode_info.afmt[0]) { 1599 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1600 rdev->mode_info.afmt[0]->id = 0; 1601 } 1602 /* r6xx has 2 routable audio blocks */ 1603 if (rdev->family >= CHIP_R600) { 1604 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1605 if (rdev->mode_info.afmt[1]) { 1606 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1607 rdev->mode_info.afmt[1]->id = 1; 1608 } 1609 } 1610 } 1611 } 1612 1613 static void radeon_afmt_fini(struct radeon_device *rdev) 1614 { 1615 int i; 1616 1617 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1618 kfree(rdev->mode_info.afmt[i]); 1619 rdev->mode_info.afmt[i] = NULL; 1620 } 1621 } 1622 1623 int radeon_modeset_init(struct radeon_device *rdev) 1624 { 1625 int i; 1626 int ret; 1627 1628 drm_mode_config_init(rdev->ddev); 1629 rdev->mode_info.mode_config_initialized = true; 1630 1631 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1632 1633 if (ASIC_IS_DCE5(rdev)) { 1634 rdev->ddev->mode_config.max_width = 16384; 1635 rdev->ddev->mode_config.max_height = 16384; 1636 } else if (ASIC_IS_AVIVO(rdev)) { 1637 rdev->ddev->mode_config.max_width = 8192; 1638 rdev->ddev->mode_config.max_height = 8192; 1639 } else { 1640 rdev->ddev->mode_config.max_width = 4096; 1641 rdev->ddev->mode_config.max_height = 4096; 1642 } 1643 1644 rdev->ddev->mode_config.preferred_depth = 24; 1645 rdev->ddev->mode_config.prefer_shadow = 1; 1646 1647 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1648 1649 ret = radeon_modeset_create_props(rdev); 1650 if (ret) { 1651 return ret; 1652 } 1653 1654 /* init i2c buses */ 1655 radeon_i2c_init(rdev); 1656 1657 /* check combios for a valid hardcoded EDID - Sun servers */ 1658 if (!rdev->is_atom_bios) { 1659 /* check for hardcoded EDID in BIOS */ 1660 radeon_combios_check_hardcoded_edid(rdev); 1661 } 1662 1663 /* allocate crtcs */ 1664 for (i = 0; i < rdev->num_crtc; i++) { 1665 radeon_crtc_init(rdev->ddev, i); 1666 } 1667 1668 /* okay we should have all the bios connectors */ 1669 ret = radeon_setup_enc_conn(rdev->ddev); 1670 if (!ret) { 1671 return ret; 1672 } 1673 1674 /* init dig PHYs, disp eng pll */ 1675 if (rdev->is_atom_bios) { 1676 radeon_atom_encoder_init(rdev); 1677 radeon_atom_disp_eng_pll_init(rdev); 1678 } 1679 1680 /* initialize hpd */ 1681 radeon_hpd_init(rdev); 1682 1683 /* setup afmt */ 1684 radeon_afmt_init(rdev); 1685 1686 radeon_fbdev_init(rdev); 1687 drm_kms_helper_poll_init(rdev->ddev); 1688 1689 /* do pm late init */ 1690 ret = radeon_pm_late_init(rdev); 1691 1692 return 0; 1693 } 1694 1695 void radeon_modeset_fini(struct radeon_device *rdev) 1696 { 1697 radeon_fbdev_fini(rdev); 1698 kfree(rdev->mode_info.bios_hardcoded_edid); 1699 1700 /* free i2c buses */ 1701 radeon_i2c_fini(rdev); 1702 1703 if (rdev->mode_info.mode_config_initialized) { 1704 radeon_afmt_fini(rdev); 1705 drm_kms_helper_poll_fini(rdev->ddev); 1706 radeon_hpd_fini(rdev); 1707 drm_mode_config_cleanup(rdev->ddev); 1708 rdev->mode_info.mode_config_initialized = false; 1709 } 1710 } 1711 1712 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1713 { 1714 /* try and guess if this is a tv or a monitor */ 1715 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1716 (mode->vdisplay == 576) || /* 576p */ 1717 (mode->vdisplay == 720) || /* 720p */ 1718 (mode->vdisplay == 1080)) /* 1080p */ 1719 return true; 1720 else 1721 return false; 1722 } 1723 1724 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1725 const struct drm_display_mode *mode, 1726 struct drm_display_mode *adjusted_mode) 1727 { 1728 struct drm_device *dev = crtc->dev; 1729 struct radeon_device *rdev = dev->dev_private; 1730 struct drm_encoder *encoder; 1731 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1732 struct radeon_encoder *radeon_encoder; 1733 struct drm_connector *connector; 1734 struct radeon_connector *radeon_connector; 1735 bool first = true; 1736 u32 src_v = 1, dst_v = 1; 1737 u32 src_h = 1, dst_h = 1; 1738 1739 radeon_crtc->h_border = 0; 1740 radeon_crtc->v_border = 0; 1741 1742 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1743 if (encoder->crtc != crtc) 1744 continue; 1745 radeon_encoder = to_radeon_encoder(encoder); 1746 connector = radeon_get_connector_for_encoder(encoder); 1747 radeon_connector = to_radeon_connector(connector); 1748 1749 if (first) { 1750 /* set scaling */ 1751 if (radeon_encoder->rmx_type == RMX_OFF) 1752 radeon_crtc->rmx_type = RMX_OFF; 1753 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1754 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1755 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1756 else 1757 radeon_crtc->rmx_type = RMX_OFF; 1758 /* copy native mode */ 1759 memcpy(&radeon_crtc->native_mode, 1760 &radeon_encoder->native_mode, 1761 sizeof(struct drm_display_mode)); 1762 src_v = crtc->mode.vdisplay; 1763 dst_v = radeon_crtc->native_mode.vdisplay; 1764 src_h = crtc->mode.hdisplay; 1765 dst_h = radeon_crtc->native_mode.hdisplay; 1766 1767 /* fix up for overscan on hdmi */ 1768 if (ASIC_IS_AVIVO(rdev) && 1769 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1770 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1771 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1772 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1773 is_hdtv_mode(mode)))) { 1774 if (radeon_encoder->underscan_hborder != 0) 1775 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1776 else 1777 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1778 if (radeon_encoder->underscan_vborder != 0) 1779 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1780 else 1781 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1782 radeon_crtc->rmx_type = RMX_FULL; 1783 src_v = crtc->mode.vdisplay; 1784 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1785 src_h = crtc->mode.hdisplay; 1786 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1787 } 1788 first = false; 1789 } else { 1790 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1791 /* WARNING: Right now this can't happen but 1792 * in the future we need to check that scaling 1793 * are consistent across different encoder 1794 * (ie all encoder can work with the same 1795 * scaling). 1796 */ 1797 DRM_ERROR("Scaling not consistent across encoder.\n"); 1798 return false; 1799 } 1800 } 1801 } 1802 if (radeon_crtc->rmx_type != RMX_OFF) { 1803 fixed20_12 a, b; 1804 a.full = dfixed_const(src_v); 1805 b.full = dfixed_const(dst_v); 1806 radeon_crtc->vsc.full = dfixed_div(a, b); 1807 a.full = dfixed_const(src_h); 1808 b.full = dfixed_const(dst_h); 1809 radeon_crtc->hsc.full = dfixed_div(a, b); 1810 } else { 1811 radeon_crtc->vsc.full = dfixed_const(1); 1812 radeon_crtc->hsc.full = dfixed_const(1); 1813 } 1814 return true; 1815 } 1816 1817 /* 1818 * Retrieve current video scanout position of crtc on a given gpu, and 1819 * an optional accurate timestamp of when query happened. 1820 * 1821 * \param dev Device to query. 1822 * \param crtc Crtc to query. 1823 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1824 * For driver internal use only also supports these flags: 1825 * 1826 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1827 * of a fudged earlier start of vblank. 1828 * 1829 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1830 * fudged earlier start of vblank in *vpos and the distance 1831 * to true start of vblank in *hpos. 1832 * 1833 * \param *vpos Location where vertical scanout position should be stored. 1834 * \param *hpos Location where horizontal scanout position should go. 1835 * \param *stime Target location for timestamp taken immediately before 1836 * scanout position query. Can be NULL to skip timestamp. 1837 * \param *etime Target location for timestamp taken immediately after 1838 * scanout position query. Can be NULL to skip timestamp. 1839 * 1840 * Returns vpos as a positive number while in active scanout area. 1841 * Returns vpos as a negative number inside vblank, counting the number 1842 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1843 * until start of active scanout / end of vblank." 1844 * 1845 * \return Flags, or'ed together as follows: 1846 * 1847 * DRM_SCANOUTPOS_VALID = Query successful. 1848 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1849 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1850 * this flag means that returned position may be offset by a constant but 1851 * unknown small number of scanlines wrt. real scanout position. 1852 * 1853 */ 1854 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1855 unsigned int flags, int *vpos, int *hpos, 1856 ktime_t *stime, ktime_t *etime, 1857 const struct drm_display_mode *mode) 1858 { 1859 u32 stat_crtc = 0, vbl = 0, position = 0; 1860 int vbl_start, vbl_end, vtotal, ret = 0; 1861 bool in_vbl = true; 1862 1863 struct radeon_device *rdev = dev->dev_private; 1864 1865 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1866 1867 /* Get optional system timestamp before query. */ 1868 if (stime) 1869 *stime = ktime_get(); 1870 1871 if (ASIC_IS_DCE4(rdev)) { 1872 if (pipe == 0) { 1873 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1874 EVERGREEN_CRTC0_REGISTER_OFFSET); 1875 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1876 EVERGREEN_CRTC0_REGISTER_OFFSET); 1877 ret |= DRM_SCANOUTPOS_VALID; 1878 } 1879 if (pipe == 1) { 1880 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1881 EVERGREEN_CRTC1_REGISTER_OFFSET); 1882 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1883 EVERGREEN_CRTC1_REGISTER_OFFSET); 1884 ret |= DRM_SCANOUTPOS_VALID; 1885 } 1886 if (pipe == 2) { 1887 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1888 EVERGREEN_CRTC2_REGISTER_OFFSET); 1889 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1890 EVERGREEN_CRTC2_REGISTER_OFFSET); 1891 ret |= DRM_SCANOUTPOS_VALID; 1892 } 1893 if (pipe == 3) { 1894 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1895 EVERGREEN_CRTC3_REGISTER_OFFSET); 1896 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1897 EVERGREEN_CRTC3_REGISTER_OFFSET); 1898 ret |= DRM_SCANOUTPOS_VALID; 1899 } 1900 if (pipe == 4) { 1901 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1902 EVERGREEN_CRTC4_REGISTER_OFFSET); 1903 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1904 EVERGREEN_CRTC4_REGISTER_OFFSET); 1905 ret |= DRM_SCANOUTPOS_VALID; 1906 } 1907 if (pipe == 5) { 1908 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1909 EVERGREEN_CRTC5_REGISTER_OFFSET); 1910 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1911 EVERGREEN_CRTC5_REGISTER_OFFSET); 1912 ret |= DRM_SCANOUTPOS_VALID; 1913 } 1914 } else if (ASIC_IS_AVIVO(rdev)) { 1915 if (pipe == 0) { 1916 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1917 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1918 ret |= DRM_SCANOUTPOS_VALID; 1919 } 1920 if (pipe == 1) { 1921 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1922 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1923 ret |= DRM_SCANOUTPOS_VALID; 1924 } 1925 } else { 1926 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1927 if (pipe == 0) { 1928 /* Assume vbl_end == 0, get vbl_start from 1929 * upper 16 bits. 1930 */ 1931 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1932 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1933 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1934 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1935 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1936 if (!(stat_crtc & 1)) 1937 in_vbl = false; 1938 1939 ret |= DRM_SCANOUTPOS_VALID; 1940 } 1941 if (pipe == 1) { 1942 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1943 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1944 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1945 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1946 if (!(stat_crtc & 1)) 1947 in_vbl = false; 1948 1949 ret |= DRM_SCANOUTPOS_VALID; 1950 } 1951 } 1952 1953 /* Get optional system timestamp after query. */ 1954 if (etime) 1955 *etime = ktime_get(); 1956 1957 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1958 1959 /* Decode into vertical and horizontal scanout position. */ 1960 *vpos = position & 0x1fff; 1961 *hpos = (position >> 16) & 0x1fff; 1962 1963 /* Valid vblank area boundaries from gpu retrieved? */ 1964 if (vbl > 0) { 1965 /* Yes: Decode. */ 1966 ret |= DRM_SCANOUTPOS_ACCURATE; 1967 vbl_start = vbl & 0x1fff; 1968 vbl_end = (vbl >> 16) & 0x1fff; 1969 } 1970 else { 1971 /* No: Fake something reasonable which gives at least ok results. */ 1972 vbl_start = mode->crtc_vdisplay; 1973 vbl_end = 0; 1974 } 1975 1976 /* Called from driver internal vblank counter query code? */ 1977 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1978 /* Caller wants distance from real vbl_start in *hpos */ 1979 *hpos = *vpos - vbl_start; 1980 } 1981 1982 /* Fudge vblank to start a few scanlines earlier to handle the 1983 * problem that vblank irqs fire a few scanlines before start 1984 * of vblank. Some driver internal callers need the true vblank 1985 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1986 * 1987 * The cause of the "early" vblank irq is that the irq is triggered 1988 * by the line buffer logic when the line buffer read position enters 1989 * the vblank, whereas our crtc scanout position naturally lags the 1990 * line buffer read position. 1991 */ 1992 if (!(flags & USE_REAL_VBLANKSTART)) 1993 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1994 1995 /* Test scanout position against vblank region. */ 1996 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1997 in_vbl = false; 1998 1999 /* In vblank? */ 2000 if (in_vbl) 2001 ret |= DRM_SCANOUTPOS_IN_VBLANK; 2002 2003 /* Called from driver internal vblank counter query code? */ 2004 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 2005 /* Caller wants distance from fudged earlier vbl_start */ 2006 *vpos -= vbl_start; 2007 return ret; 2008 } 2009 2010 /* Check if inside vblank area and apply corrective offsets: 2011 * vpos will then be >=0 in video scanout area, but negative 2012 * within vblank area, counting down the number of lines until 2013 * start of scanout. 2014 */ 2015 2016 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 2017 if (in_vbl && (*vpos >= vbl_start)) { 2018 vtotal = mode->crtc_vtotal; 2019 *vpos = *vpos - vtotal; 2020 } 2021 2022 /* Correct for shifted end of vbl at vbl_end. */ 2023 *vpos = *vpos - vbl_end; 2024 2025 return ret; 2026 } 2027