1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 
27 #include <linux/pci.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/gcd.h>
30 
31 #include <asm/div64.h>
32 
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_device.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_fourcc.h>
39 #include <drm/drm_framebuffer.h>
40 #include <drm/drm_gem_framebuffer_helper.h>
41 #include <drm/drm_plane_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_vblank.h>
44 #include <drm/radeon_drm.h>
45 
46 #include "atom.h"
47 #include "radeon.h"
48 #include "radeon_kms.h"
49 
50 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
51 {
52 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
53 	struct drm_device *dev = crtc->dev;
54 	struct radeon_device *rdev = dev->dev_private;
55 	u16 *r, *g, *b;
56 	int i;
57 
58 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
59 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
60 
61 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
62 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
63 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
64 
65 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
66 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
67 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
68 
69 	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
70 	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
71 	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
72 
73 	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
74 	r = crtc->gamma_store;
75 	g = r + crtc->gamma_size;
76 	b = g + crtc->gamma_size;
77 	for (i = 0; i < 256; i++) {
78 		WREG32(AVIVO_DC_LUT_30_COLOR,
79 		       ((*r++ & 0xffc0) << 14) |
80 		       ((*g++ & 0xffc0) << 4) |
81 		       (*b++ >> 6));
82 	}
83 
84 	/* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
85 	WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
86 }
87 
88 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
89 {
90 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
91 	struct drm_device *dev = crtc->dev;
92 	struct radeon_device *rdev = dev->dev_private;
93 	u16 *r, *g, *b;
94 	int i;
95 
96 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
97 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
98 
99 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
100 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
101 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
102 
103 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
104 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
105 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
106 
107 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
108 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
109 
110 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
111 	r = crtc->gamma_store;
112 	g = r + crtc->gamma_size;
113 	b = g + crtc->gamma_size;
114 	for (i = 0; i < 256; i++) {
115 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
116 		       ((*r++ & 0xffc0) << 14) |
117 		       ((*g++ & 0xffc0) << 4) |
118 		       (*b++ >> 6));
119 	}
120 }
121 
122 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
123 {
124 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125 	struct drm_device *dev = crtc->dev;
126 	struct radeon_device *rdev = dev->dev_private;
127 	u16 *r, *g, *b;
128 	int i;
129 
130 	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
131 
132 	msleep(10);
133 
134 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
135 	       (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
136 		NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
137 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
138 	       NI_GRPH_PRESCALE_BYPASS);
139 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
140 	       NI_OVL_PRESCALE_BYPASS);
141 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
142 	       (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
143 		NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
144 
145 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
146 
147 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
148 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
149 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
150 
151 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
152 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
153 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
154 
155 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
156 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
157 
158 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
159 	r = crtc->gamma_store;
160 	g = r + crtc->gamma_size;
161 	b = g + crtc->gamma_size;
162 	for (i = 0; i < 256; i++) {
163 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
164 		       ((*r++ & 0xffc0) << 14) |
165 		       ((*g++ & 0xffc0) << 4) |
166 		       (*b++ >> 6));
167 	}
168 
169 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
170 	       (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
171 		NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
172 		NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
173 		NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
174 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
175 	       (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
176 		NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
177 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
178 	       (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
179 		NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
180 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
181 	       (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
182 		NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
183 	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
184 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
185 	if (ASIC_IS_DCE8(rdev)) {
186 		/* XXX this only needs to be programmed once per crtc at startup,
187 		 * not sure where the best place for it is
188 		 */
189 		WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
190 		       CIK_CURSOR_ALPHA_BLND_ENA);
191 	}
192 }
193 
194 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
195 {
196 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
197 	struct drm_device *dev = crtc->dev;
198 	struct radeon_device *rdev = dev->dev_private;
199 	u16 *r, *g, *b;
200 	int i;
201 	uint32_t dac2_cntl;
202 
203 	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
204 	if (radeon_crtc->crtc_id == 0)
205 		dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
206 	else
207 		dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
208 	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
209 
210 	WREG8(RADEON_PALETTE_INDEX, 0);
211 	r = crtc->gamma_store;
212 	g = r + crtc->gamma_size;
213 	b = g + crtc->gamma_size;
214 	for (i = 0; i < 256; i++) {
215 		WREG32(RADEON_PALETTE_30_DATA,
216 		       ((*r++ & 0xffc0) << 14) |
217 		       ((*g++ & 0xffc0) << 4) |
218 		       (*b++ >> 6));
219 	}
220 }
221 
222 void radeon_crtc_load_lut(struct drm_crtc *crtc)
223 {
224 	struct drm_device *dev = crtc->dev;
225 	struct radeon_device *rdev = dev->dev_private;
226 
227 	if (!crtc->enabled)
228 		return;
229 
230 	if (ASIC_IS_DCE5(rdev))
231 		dce5_crtc_load_lut(crtc);
232 	else if (ASIC_IS_DCE4(rdev))
233 		dce4_crtc_load_lut(crtc);
234 	else if (ASIC_IS_AVIVO(rdev))
235 		avivo_crtc_load_lut(crtc);
236 	else
237 		legacy_crtc_load_lut(crtc);
238 }
239 
240 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
241 				 u16 *blue, uint32_t size,
242 				 struct drm_modeset_acquire_ctx *ctx)
243 {
244 	radeon_crtc_load_lut(crtc);
245 
246 	return 0;
247 }
248 
249 static void radeon_crtc_destroy(struct drm_crtc *crtc)
250 {
251 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 
253 	drm_crtc_cleanup(crtc);
254 	destroy_workqueue(radeon_crtc->flip_queue);
255 	kfree(radeon_crtc);
256 }
257 
258 /**
259  * radeon_unpin_work_func - unpin old buffer object
260  *
261  * @__work: kernel work item
262  *
263  * Unpin the old frame buffer object outside of the interrupt handler
264  */
265 static void radeon_unpin_work_func(struct work_struct *__work)
266 {
267 	struct radeon_flip_work *work =
268 		container_of(__work, struct radeon_flip_work, unpin_work);
269 	int r;
270 
271 	/* unpin of the old buffer */
272 	r = radeon_bo_reserve(work->old_rbo, false);
273 	if (likely(r == 0)) {
274 		radeon_bo_unpin(work->old_rbo);
275 		radeon_bo_unreserve(work->old_rbo);
276 	} else
277 		DRM_ERROR("failed to reserve buffer after flip\n");
278 
279 	drm_gem_object_put(&work->old_rbo->tbo.base);
280 	kfree(work);
281 }
282 
283 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
284 {
285 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
286 	unsigned long flags;
287 	u32 update_pending;
288 	int vpos, hpos;
289 
290 	/* can happen during initialization */
291 	if (radeon_crtc == NULL)
292 		return;
293 
294 	/* Skip the pageflip completion check below (based on polling) on
295 	 * asics which reliably support hw pageflip completion irqs. pflip
296 	 * irqs are a reliable and race-free method of handling pageflip
297 	 * completion detection. A use_pflipirq module parameter < 2 allows
298 	 * to override this in case of asics with faulty pflip irqs.
299 	 * A module parameter of 0 would only use this polling based path,
300 	 * a parameter of 1 would use pflip irq only as a backup to this
301 	 * path, as in Linux 3.16.
302 	 */
303 	if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
304 		return;
305 
306 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
307 	if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
308 		DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
309 				 "RADEON_FLIP_SUBMITTED(%d)\n",
310 				 radeon_crtc->flip_status,
311 				 RADEON_FLIP_SUBMITTED);
312 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
313 		return;
314 	}
315 
316 	update_pending = radeon_page_flip_pending(rdev, crtc_id);
317 
318 	/* Has the pageflip already completed in crtc, or is it certain
319 	 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
320 	 * distance to start of "fudged earlier" vblank in vpos, distance to
321 	 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
322 	 * the last few scanlines before start of real vblank, where the vblank
323 	 * irq can fire, so we have sampled update_pending a bit too early and
324 	 * know the flip will complete at leading edge of the upcoming real
325 	 * vblank. On pre-AVIVO hardware, flips also complete inside the real
326 	 * vblank, not only at leading edge, so if update_pending for hpos >= 0
327 	 *  == inside real vblank, the flip will complete almost immediately.
328 	 * Note that this method of completion handling is still not 100% race
329 	 * free, as we could execute before the radeon_flip_work_func managed
330 	 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
331 	 * but the flip still gets programmed into hw and completed during
332 	 * vblank, leading to a delayed emission of the flip completion event.
333 	 * This applies at least to pre-AVIVO hardware, where flips are always
334 	 * completing inside vblank, not only at leading edge of vblank.
335 	 */
336 	if (update_pending &&
337 	    (DRM_SCANOUTPOS_VALID &
338 	     radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
339 					GET_DISTANCE_TO_VBLANKSTART,
340 					&vpos, &hpos, NULL, NULL,
341 					&rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
342 	    ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
343 		/* crtc didn't flip in this target vblank interval,
344 		 * but flip is pending in crtc. Based on the current
345 		 * scanout position we know that the current frame is
346 		 * (nearly) complete and the flip will (likely)
347 		 * complete before the start of the next frame.
348 		 */
349 		update_pending = 0;
350 	}
351 	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
352 	if (!update_pending)
353 		radeon_crtc_handle_flip(rdev, crtc_id);
354 }
355 
356 /**
357  * radeon_crtc_handle_flip - page flip completed
358  *
359  * @rdev: radeon device pointer
360  * @crtc_id: crtc number this event is for
361  *
362  * Called when we are sure that a page flip for this crtc is completed.
363  */
364 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
365 {
366 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
367 	struct radeon_flip_work *work;
368 	unsigned long flags;
369 
370 	/* this can happen at init */
371 	if (radeon_crtc == NULL)
372 		return;
373 
374 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
375 	work = radeon_crtc->flip_work;
376 	if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
377 		DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
378 				 "RADEON_FLIP_SUBMITTED(%d)\n",
379 				 radeon_crtc->flip_status,
380 				 RADEON_FLIP_SUBMITTED);
381 		spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
382 		return;
383 	}
384 
385 	/* Pageflip completed. Clean up. */
386 	radeon_crtc->flip_status = RADEON_FLIP_NONE;
387 	radeon_crtc->flip_work = NULL;
388 
389 	/* wakeup userspace */
390 	if (work->event)
391 		drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
392 
393 	spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
394 
395 	drm_crtc_vblank_put(&radeon_crtc->base);
396 	radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
397 	queue_work(radeon_crtc->flip_queue, &work->unpin_work);
398 }
399 
400 /**
401  * radeon_flip_work_func - page flip framebuffer
402  *
403  * @__work: kernel work item
404  *
405  * Wait for the buffer object to become idle and do the actual page flip
406  */
407 static void radeon_flip_work_func(struct work_struct *__work)
408 {
409 	struct radeon_flip_work *work =
410 		container_of(__work, struct radeon_flip_work, flip_work);
411 	struct radeon_device *rdev = work->rdev;
412 	struct drm_device *dev = rdev->ddev;
413 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
414 
415 	struct drm_crtc *crtc = &radeon_crtc->base;
416 	unsigned long flags;
417 	int r;
418 	int vpos, hpos;
419 
420 	down_read(&rdev->exclusive_lock);
421 	if (work->fence) {
422 		struct radeon_fence *fence;
423 
424 		fence = to_radeon_fence(work->fence);
425 		if (fence && fence->rdev == rdev) {
426 			r = radeon_fence_wait(fence, false);
427 			if (r == -EDEADLK) {
428 				up_read(&rdev->exclusive_lock);
429 				do {
430 					r = radeon_gpu_reset(rdev);
431 				} while (r == -EAGAIN);
432 				down_read(&rdev->exclusive_lock);
433 			}
434 		} else
435 			r = dma_fence_wait(work->fence, false);
436 
437 		if (r)
438 			DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
439 
440 		/* We continue with the page flip even if we failed to wait on
441 		 * the fence, otherwise the DRM core and userspace will be
442 		 * confused about which BO the CRTC is scanning out
443 		 */
444 
445 		dma_fence_put(work->fence);
446 		work->fence = NULL;
447 	}
448 
449 	/* Wait until we're out of the vertical blank period before the one
450 	 * targeted by the flip. Always wait on pre DCE4 to avoid races with
451 	 * flip completion handling from vblank irq, as these old asics don't
452 	 * have reliable pageflip completion interrupts.
453 	 */
454 	while (radeon_crtc->enabled &&
455 		(radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
456 					    &vpos, &hpos, NULL, NULL,
457 					    &crtc->hwmode)
458 		& (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
459 		(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
460 		(!ASIC_IS_AVIVO(rdev) ||
461 		((int) (work->target_vblank -
462 		crtc->funcs->get_vblank_counter(crtc)) > 0)))
463 		usleep_range(1000, 2000);
464 
465 	/* We borrow the event spin lock for protecting flip_status */
466 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
467 
468 	/* set the proper interrupt */
469 	radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
470 
471 	/* do the flip (mmio) */
472 	radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
473 
474 	radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
475 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
476 	up_read(&rdev->exclusive_lock);
477 }
478 
479 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
480 					struct drm_framebuffer *fb,
481 					struct drm_pending_vblank_event *event,
482 					uint32_t page_flip_flags,
483 					uint32_t target,
484 					struct drm_modeset_acquire_ctx *ctx)
485 {
486 	struct drm_device *dev = crtc->dev;
487 	struct radeon_device *rdev = dev->dev_private;
488 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
489 	struct drm_gem_object *obj;
490 	struct radeon_flip_work *work;
491 	struct radeon_bo *new_rbo;
492 	uint32_t tiling_flags, pitch_pixels;
493 	uint64_t base;
494 	unsigned long flags;
495 	int r;
496 
497 	work = kzalloc(sizeof *work, GFP_KERNEL);
498 	if (work == NULL)
499 		return -ENOMEM;
500 
501 	INIT_WORK(&work->flip_work, radeon_flip_work_func);
502 	INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
503 
504 	work->rdev = rdev;
505 	work->crtc_id = radeon_crtc->crtc_id;
506 	work->event = event;
507 	work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
508 
509 	/* schedule unpin of the old buffer */
510 	obj = crtc->primary->fb->obj[0];
511 
512 	/* take a reference to the old object */
513 	drm_gem_object_get(obj);
514 	work->old_rbo = gem_to_radeon_bo(obj);
515 
516 	obj = fb->obj[0];
517 	new_rbo = gem_to_radeon_bo(obj);
518 
519 	/* pin the new buffer */
520 	DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
521 			 work->old_rbo, new_rbo);
522 
523 	r = radeon_bo_reserve(new_rbo, false);
524 	if (unlikely(r != 0)) {
525 		DRM_ERROR("failed to reserve new rbo buffer before flip\n");
526 		goto cleanup;
527 	}
528 	/* Only 27 bit offset for legacy CRTC */
529 	r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
530 				     ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
531 	if (unlikely(r != 0)) {
532 		radeon_bo_unreserve(new_rbo);
533 		r = -EINVAL;
534 		DRM_ERROR("failed to pin new rbo buffer before flip\n");
535 		goto cleanup;
536 	}
537 	r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
538 				   &work->fence);
539 	if (r) {
540 		radeon_bo_unreserve(new_rbo);
541 		DRM_ERROR("failed to get new rbo buffer fences\n");
542 		goto cleanup;
543 	}
544 	radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
545 	radeon_bo_unreserve(new_rbo);
546 
547 	if (!ASIC_IS_AVIVO(rdev)) {
548 		/* crtc offset is from display base addr not FB location */
549 		base -= radeon_crtc->legacy_display_base_addr;
550 		pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
551 
552 		if (tiling_flags & RADEON_TILING_MACRO) {
553 			if (ASIC_IS_R300(rdev)) {
554 				base &= ~0x7ff;
555 			} else {
556 				int byteshift = fb->format->cpp[0] * 8 >> 4;
557 				int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
558 				base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
559 			}
560 		} else {
561 			int offset = crtc->y * pitch_pixels + crtc->x;
562 			switch (fb->format->cpp[0] * 8) {
563 			case 8:
564 			default:
565 				offset *= 1;
566 				break;
567 			case 15:
568 			case 16:
569 				offset *= 2;
570 				break;
571 			case 24:
572 				offset *= 3;
573 				break;
574 			case 32:
575 				offset *= 4;
576 				break;
577 			}
578 			base += offset;
579 		}
580 		base &= ~7;
581 	}
582 	work->base = base;
583 	work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
584 		crtc->funcs->get_vblank_counter(crtc);
585 
586 	/* We borrow the event spin lock for protecting flip_work */
587 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
588 
589 	if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
590 		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
591 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
592 		r = -EBUSY;
593 		goto pflip_cleanup;
594 	}
595 	radeon_crtc->flip_status = RADEON_FLIP_PENDING;
596 	radeon_crtc->flip_work = work;
597 
598 	/* update crtc fb */
599 	crtc->primary->fb = fb;
600 
601 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
602 
603 	queue_work(radeon_crtc->flip_queue, &work->flip_work);
604 	return 0;
605 
606 pflip_cleanup:
607 	if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
608 		DRM_ERROR("failed to reserve new rbo in error path\n");
609 		goto cleanup;
610 	}
611 	radeon_bo_unpin(new_rbo);
612 	radeon_bo_unreserve(new_rbo);
613 
614 cleanup:
615 	drm_gem_object_put(&work->old_rbo->tbo.base);
616 	dma_fence_put(work->fence);
617 	kfree(work);
618 	return r;
619 }
620 
621 static int
622 radeon_crtc_set_config(struct drm_mode_set *set,
623 		       struct drm_modeset_acquire_ctx *ctx)
624 {
625 	struct drm_device *dev;
626 	struct radeon_device *rdev;
627 	struct drm_crtc *crtc;
628 	bool active = false;
629 	int ret;
630 
631 	if (!set || !set->crtc)
632 		return -EINVAL;
633 
634 	dev = set->crtc->dev;
635 
636 	ret = pm_runtime_get_sync(dev->dev);
637 	if (ret < 0) {
638 		pm_runtime_put_autosuspend(dev->dev);
639 		return ret;
640 	}
641 
642 	ret = drm_crtc_helper_set_config(set, ctx);
643 
644 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
645 		if (crtc->enabled)
646 			active = true;
647 
648 	pm_runtime_mark_last_busy(dev->dev);
649 
650 	rdev = dev->dev_private;
651 	/* if we have active crtcs and we don't have a power ref,
652 	   take the current one */
653 	if (active && !rdev->have_disp_power_ref) {
654 		rdev->have_disp_power_ref = true;
655 		return ret;
656 	}
657 	/* if we have no active crtcs, then drop the power ref
658 	   we got before */
659 	if (!active && rdev->have_disp_power_ref) {
660 		pm_runtime_put_autosuspend(dev->dev);
661 		rdev->have_disp_power_ref = false;
662 	}
663 
664 	/* drop the power reference we got coming in here */
665 	pm_runtime_put_autosuspend(dev->dev);
666 	return ret;
667 }
668 
669 static const struct drm_crtc_funcs radeon_crtc_funcs = {
670 	.cursor_set2 = radeon_crtc_cursor_set2,
671 	.cursor_move = radeon_crtc_cursor_move,
672 	.gamma_set = radeon_crtc_gamma_set,
673 	.set_config = radeon_crtc_set_config,
674 	.destroy = radeon_crtc_destroy,
675 	.page_flip_target = radeon_crtc_page_flip_target,
676 	.get_vblank_counter = radeon_get_vblank_counter_kms,
677 	.enable_vblank = radeon_enable_vblank_kms,
678 	.disable_vblank = radeon_disable_vblank_kms,
679 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
680 };
681 
682 static void radeon_crtc_init(struct drm_device *dev, int index)
683 {
684 	struct radeon_device *rdev = dev->dev_private;
685 	struct radeon_crtc *radeon_crtc;
686 
687 	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
688 	if (radeon_crtc == NULL)
689 		return;
690 
691 	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
692 
693 	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
694 	radeon_crtc->crtc_id = index;
695 	radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
696 	rdev->mode_info.crtcs[index] = radeon_crtc;
697 
698 	if (rdev->family >= CHIP_BONAIRE) {
699 		radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
700 		radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
701 	} else {
702 		radeon_crtc->max_cursor_width = CURSOR_WIDTH;
703 		radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
704 	}
705 	dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
706 	dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
707 
708 #if 0
709 	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
710 	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
711 	radeon_crtc->mode_set.num_connectors = 0;
712 #endif
713 
714 	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
715 		radeon_atombios_init_crtc(dev, radeon_crtc);
716 	else
717 		radeon_legacy_init_crtc(dev, radeon_crtc);
718 }
719 
720 static const char *encoder_names[38] = {
721 	"NONE",
722 	"INTERNAL_LVDS",
723 	"INTERNAL_TMDS1",
724 	"INTERNAL_TMDS2",
725 	"INTERNAL_DAC1",
726 	"INTERNAL_DAC2",
727 	"INTERNAL_SDVOA",
728 	"INTERNAL_SDVOB",
729 	"SI170B",
730 	"CH7303",
731 	"CH7301",
732 	"INTERNAL_DVO1",
733 	"EXTERNAL_SDVOA",
734 	"EXTERNAL_SDVOB",
735 	"TITFP513",
736 	"INTERNAL_LVTM1",
737 	"VT1623",
738 	"HDMI_SI1930",
739 	"HDMI_INTERNAL",
740 	"INTERNAL_KLDSCP_TMDS1",
741 	"INTERNAL_KLDSCP_DVO1",
742 	"INTERNAL_KLDSCP_DAC1",
743 	"INTERNAL_KLDSCP_DAC2",
744 	"SI178",
745 	"MVPU_FPGA",
746 	"INTERNAL_DDI",
747 	"VT1625",
748 	"HDMI_SI1932",
749 	"DP_AN9801",
750 	"DP_DP501",
751 	"INTERNAL_UNIPHY",
752 	"INTERNAL_KLDSCP_LVTMA",
753 	"INTERNAL_UNIPHY1",
754 	"INTERNAL_UNIPHY2",
755 	"NUTMEG",
756 	"TRAVIS",
757 	"INTERNAL_VCE",
758 	"INTERNAL_UNIPHY3",
759 };
760 
761 static const char *hpd_names[6] = {
762 	"HPD1",
763 	"HPD2",
764 	"HPD3",
765 	"HPD4",
766 	"HPD5",
767 	"HPD6",
768 };
769 
770 static void radeon_print_display_setup(struct drm_device *dev)
771 {
772 	struct drm_connector *connector;
773 	struct radeon_connector *radeon_connector;
774 	struct drm_encoder *encoder;
775 	struct radeon_encoder *radeon_encoder;
776 	uint32_t devices;
777 	int i = 0;
778 
779 	DRM_INFO("Radeon Display Connectors\n");
780 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 		radeon_connector = to_radeon_connector(connector);
782 		DRM_INFO("Connector %d:\n", i);
783 		DRM_INFO("  %s\n", connector->name);
784 		if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
785 			DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
786 		if (radeon_connector->ddc_bus) {
787 			DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
788 				 radeon_connector->ddc_bus->rec.mask_clk_reg,
789 				 radeon_connector->ddc_bus->rec.mask_data_reg,
790 				 radeon_connector->ddc_bus->rec.a_clk_reg,
791 				 radeon_connector->ddc_bus->rec.a_data_reg,
792 				 radeon_connector->ddc_bus->rec.en_clk_reg,
793 				 radeon_connector->ddc_bus->rec.en_data_reg,
794 				 radeon_connector->ddc_bus->rec.y_clk_reg,
795 				 radeon_connector->ddc_bus->rec.y_data_reg);
796 			if (radeon_connector->router.ddc_valid)
797 				DRM_INFO("  DDC Router 0x%x/0x%x\n",
798 					 radeon_connector->router.ddc_mux_control_pin,
799 					 radeon_connector->router.ddc_mux_state);
800 			if (radeon_connector->router.cd_valid)
801 				DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
802 					 radeon_connector->router.cd_mux_control_pin,
803 					 radeon_connector->router.cd_mux_state);
804 		} else {
805 			if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
806 			    connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
807 			    connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
808 			    connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
809 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
810 			    connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
811 				DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
812 		}
813 		DRM_INFO("  Encoders:\n");
814 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
815 			radeon_encoder = to_radeon_encoder(encoder);
816 			devices = radeon_encoder->devices & radeon_connector->devices;
817 			if (devices) {
818 				if (devices & ATOM_DEVICE_CRT1_SUPPORT)
819 					DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
820 				if (devices & ATOM_DEVICE_CRT2_SUPPORT)
821 					DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
822 				if (devices & ATOM_DEVICE_LCD1_SUPPORT)
823 					DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
824 				if (devices & ATOM_DEVICE_DFP1_SUPPORT)
825 					DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
826 				if (devices & ATOM_DEVICE_DFP2_SUPPORT)
827 					DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
828 				if (devices & ATOM_DEVICE_DFP3_SUPPORT)
829 					DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
830 				if (devices & ATOM_DEVICE_DFP4_SUPPORT)
831 					DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
832 				if (devices & ATOM_DEVICE_DFP5_SUPPORT)
833 					DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
834 				if (devices & ATOM_DEVICE_DFP6_SUPPORT)
835 					DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
836 				if (devices & ATOM_DEVICE_TV1_SUPPORT)
837 					DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
838 				if (devices & ATOM_DEVICE_CV_SUPPORT)
839 					DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
840 			}
841 		}
842 		i++;
843 	}
844 }
845 
846 static bool radeon_setup_enc_conn(struct drm_device *dev)
847 {
848 	struct radeon_device *rdev = dev->dev_private;
849 	bool ret = false;
850 
851 	if (rdev->bios) {
852 		if (rdev->is_atom_bios) {
853 			ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
854 			if (!ret)
855 				ret = radeon_get_atom_connector_info_from_object_table(dev);
856 		} else {
857 			ret = radeon_get_legacy_connector_info_from_bios(dev);
858 			if (!ret)
859 				ret = radeon_get_legacy_connector_info_from_table(dev);
860 		}
861 	} else {
862 		if (!ASIC_IS_AVIVO(rdev))
863 			ret = radeon_get_legacy_connector_info_from_table(dev);
864 	}
865 	if (ret) {
866 		radeon_setup_encoder_clones(dev);
867 		radeon_print_display_setup(dev);
868 	}
869 
870 	return ret;
871 }
872 
873 /* avivo */
874 
875 /**
876  * avivo_reduce_ratio - fractional number reduction
877  *
878  * @nom: nominator
879  * @den: denominator
880  * @nom_min: minimum value for nominator
881  * @den_min: minimum value for denominator
882  *
883  * Find the greatest common divisor and apply it on both nominator and
884  * denominator, but make nominator and denominator are at least as large
885  * as their minimum values.
886  */
887 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
888 			       unsigned nom_min, unsigned den_min)
889 {
890 	unsigned tmp;
891 
892 	/* reduce the numbers to a simpler ratio */
893 	tmp = gcd(*nom, *den);
894 	*nom /= tmp;
895 	*den /= tmp;
896 
897 	/* make sure nominator is large enough */
898 	if (*nom < nom_min) {
899 		tmp = DIV_ROUND_UP(nom_min, *nom);
900 		*nom *= tmp;
901 		*den *= tmp;
902 	}
903 
904 	/* make sure the denominator is large enough */
905 	if (*den < den_min) {
906 		tmp = DIV_ROUND_UP(den_min, *den);
907 		*nom *= tmp;
908 		*den *= tmp;
909 	}
910 }
911 
912 /**
913  * avivo_get_fb_ref_div - feedback and ref divider calculation
914  *
915  * @nom: nominator
916  * @den: denominator
917  * @post_div: post divider
918  * @fb_div_max: feedback divider maximum
919  * @ref_div_max: reference divider maximum
920  * @fb_div: resulting feedback divider
921  * @ref_div: resulting reference divider
922  *
923  * Calculate feedback and reference divider for a given post divider. Makes
924  * sure we stay within the limits.
925  */
926 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
927 				 unsigned fb_div_max, unsigned ref_div_max,
928 				 unsigned *fb_div, unsigned *ref_div)
929 {
930 	/* limit reference * post divider to a maximum */
931 	ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
932 
933 	/* get matching reference and feedback divider */
934 	*ref_div = min(max(den/post_div, 1u), ref_div_max);
935 	*fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
936 
937 	/* limit fb divider to its maximum */
938 	if (*fb_div > fb_div_max) {
939 		*ref_div = (*ref_div * fb_div_max)/(*fb_div);
940 		*fb_div = fb_div_max;
941 	}
942 }
943 
944 /**
945  * radeon_compute_pll_avivo - compute PLL paramaters
946  *
947  * @pll: information about the PLL
948  * @freq: target frequency
949  * @dot_clock_p: resulting pixel clock
950  * @fb_div_p: resulting feedback divider
951  * @frac_fb_div_p: fractional part of the feedback divider
952  * @ref_div_p: resulting reference divider
953  * @post_div_p: resulting reference divider
954  *
955  * Try to calculate the PLL parameters to generate the given frequency:
956  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
957  */
958 void radeon_compute_pll_avivo(struct radeon_pll *pll,
959 			      u32 freq,
960 			      u32 *dot_clock_p,
961 			      u32 *fb_div_p,
962 			      u32 *frac_fb_div_p,
963 			      u32 *ref_div_p,
964 			      u32 *post_div_p)
965 {
966 	unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
967 		freq : freq / 10;
968 
969 	unsigned fb_div_min, fb_div_max, fb_div;
970 	unsigned post_div_min, post_div_max, post_div;
971 	unsigned ref_div_min, ref_div_max, ref_div;
972 	unsigned post_div_best, diff_best;
973 	unsigned nom, den;
974 
975 	/* determine allowed feedback divider range */
976 	fb_div_min = pll->min_feedback_div;
977 	fb_div_max = pll->max_feedback_div;
978 
979 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
980 		fb_div_min *= 10;
981 		fb_div_max *= 10;
982 	}
983 
984 	/* determine allowed ref divider range */
985 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
986 		ref_div_min = pll->reference_div;
987 	else
988 		ref_div_min = pll->min_ref_div;
989 
990 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
991 	    pll->flags & RADEON_PLL_USE_REF_DIV)
992 		ref_div_max = pll->reference_div;
993 	else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
994 		/* fix for problems on RS880 */
995 		ref_div_max = min(pll->max_ref_div, 7u);
996 	else
997 		ref_div_max = pll->max_ref_div;
998 
999 	/* determine allowed post divider range */
1000 	if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1001 		post_div_min = pll->post_div;
1002 		post_div_max = pll->post_div;
1003 	} else {
1004 		unsigned vco_min, vco_max;
1005 
1006 		if (pll->flags & RADEON_PLL_IS_LCD) {
1007 			vco_min = pll->lcd_pll_out_min;
1008 			vco_max = pll->lcd_pll_out_max;
1009 		} else {
1010 			vco_min = pll->pll_out_min;
1011 			vco_max = pll->pll_out_max;
1012 		}
1013 
1014 		if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1015 			vco_min *= 10;
1016 			vco_max *= 10;
1017 		}
1018 
1019 		post_div_min = vco_min / target_clock;
1020 		if ((target_clock * post_div_min) < vco_min)
1021 			++post_div_min;
1022 		if (post_div_min < pll->min_post_div)
1023 			post_div_min = pll->min_post_div;
1024 
1025 		post_div_max = vco_max / target_clock;
1026 		if ((target_clock * post_div_max) > vco_max)
1027 			--post_div_max;
1028 		if (post_div_max > pll->max_post_div)
1029 			post_div_max = pll->max_post_div;
1030 	}
1031 
1032 	/* represent the searched ratio as fractional number */
1033 	nom = target_clock;
1034 	den = pll->reference_freq;
1035 
1036 	/* reduce the numbers to a simpler ratio */
1037 	avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1038 
1039 	/* now search for a post divider */
1040 	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1041 		post_div_best = post_div_min;
1042 	else
1043 		post_div_best = post_div_max;
1044 	diff_best = ~0;
1045 
1046 	for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1047 		unsigned diff;
1048 		avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1049 				     ref_div_max, &fb_div, &ref_div);
1050 		diff = abs(target_clock - (pll->reference_freq * fb_div) /
1051 			(ref_div * post_div));
1052 
1053 		if (diff < diff_best || (diff == diff_best &&
1054 		    !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1055 
1056 			post_div_best = post_div;
1057 			diff_best = diff;
1058 		}
1059 	}
1060 	post_div = post_div_best;
1061 
1062 	/* get the feedback and reference divider for the optimal value */
1063 	avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1064 			     &fb_div, &ref_div);
1065 
1066 	/* reduce the numbers to a simpler ratio once more */
1067 	/* this also makes sure that the reference divider is large enough */
1068 	avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1069 
1070 	/* avoid high jitter with small fractional dividers */
1071 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1072 		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1073 		if (fb_div < fb_div_min) {
1074 			unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1075 			fb_div *= tmp;
1076 			ref_div *= tmp;
1077 		}
1078 	}
1079 
1080 	/* and finally save the result */
1081 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1082 		*fb_div_p = fb_div / 10;
1083 		*frac_fb_div_p = fb_div % 10;
1084 	} else {
1085 		*fb_div_p = fb_div;
1086 		*frac_fb_div_p = 0;
1087 	}
1088 
1089 	*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1090 			(pll->reference_freq * *frac_fb_div_p)) /
1091 		       (ref_div * post_div * 10);
1092 	*ref_div_p = ref_div;
1093 	*post_div_p = post_div;
1094 
1095 	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1096 		      freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1097 		      ref_div, post_div);
1098 }
1099 
1100 /* pre-avivo */
1101 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1102 {
1103 	n += d / 2;
1104 
1105 	do_div(n, d);
1106 	return n;
1107 }
1108 
1109 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1110 			       uint64_t freq,
1111 			       uint32_t *dot_clock_p,
1112 			       uint32_t *fb_div_p,
1113 			       uint32_t *frac_fb_div_p,
1114 			       uint32_t *ref_div_p,
1115 			       uint32_t *post_div_p)
1116 {
1117 	uint32_t min_ref_div = pll->min_ref_div;
1118 	uint32_t max_ref_div = pll->max_ref_div;
1119 	uint32_t min_post_div = pll->min_post_div;
1120 	uint32_t max_post_div = pll->max_post_div;
1121 	uint32_t min_fractional_feed_div = 0;
1122 	uint32_t max_fractional_feed_div = 0;
1123 	uint32_t best_vco = pll->best_vco;
1124 	uint32_t best_post_div = 1;
1125 	uint32_t best_ref_div = 1;
1126 	uint32_t best_feedback_div = 1;
1127 	uint32_t best_frac_feedback_div = 0;
1128 	uint32_t best_freq = -1;
1129 	uint32_t best_error = 0xffffffff;
1130 	uint32_t best_vco_diff = 1;
1131 	uint32_t post_div;
1132 	u32 pll_out_min, pll_out_max;
1133 
1134 	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1135 	freq = freq * 1000;
1136 
1137 	if (pll->flags & RADEON_PLL_IS_LCD) {
1138 		pll_out_min = pll->lcd_pll_out_min;
1139 		pll_out_max = pll->lcd_pll_out_max;
1140 	} else {
1141 		pll_out_min = pll->pll_out_min;
1142 		pll_out_max = pll->pll_out_max;
1143 	}
1144 
1145 	if (pll_out_min > 64800)
1146 		pll_out_min = 64800;
1147 
1148 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
1149 		min_ref_div = max_ref_div = pll->reference_div;
1150 	else {
1151 		while (min_ref_div < max_ref_div-1) {
1152 			uint32_t mid = (min_ref_div + max_ref_div) / 2;
1153 			uint32_t pll_in = pll->reference_freq / mid;
1154 			if (pll_in < pll->pll_in_min)
1155 				max_ref_div = mid;
1156 			else if (pll_in > pll->pll_in_max)
1157 				min_ref_div = mid;
1158 			else
1159 				break;
1160 		}
1161 	}
1162 
1163 	if (pll->flags & RADEON_PLL_USE_POST_DIV)
1164 		min_post_div = max_post_div = pll->post_div;
1165 
1166 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1167 		min_fractional_feed_div = pll->min_frac_feedback_div;
1168 		max_fractional_feed_div = pll->max_frac_feedback_div;
1169 	}
1170 
1171 	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1172 		uint32_t ref_div;
1173 
1174 		if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1175 			continue;
1176 
1177 		/* legacy radeons only have a few post_divs */
1178 		if (pll->flags & RADEON_PLL_LEGACY) {
1179 			if ((post_div == 5) ||
1180 			    (post_div == 7) ||
1181 			    (post_div == 9) ||
1182 			    (post_div == 10) ||
1183 			    (post_div == 11) ||
1184 			    (post_div == 13) ||
1185 			    (post_div == 14) ||
1186 			    (post_div == 15))
1187 				continue;
1188 		}
1189 
1190 		for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1191 			uint32_t feedback_div, current_freq = 0, error, vco_diff;
1192 			uint32_t pll_in = pll->reference_freq / ref_div;
1193 			uint32_t min_feed_div = pll->min_feedback_div;
1194 			uint32_t max_feed_div = pll->max_feedback_div + 1;
1195 
1196 			if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1197 				continue;
1198 
1199 			while (min_feed_div < max_feed_div) {
1200 				uint32_t vco;
1201 				uint32_t min_frac_feed_div = min_fractional_feed_div;
1202 				uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1203 				uint32_t frac_feedback_div;
1204 				uint64_t tmp;
1205 
1206 				feedback_div = (min_feed_div + max_feed_div) / 2;
1207 
1208 				tmp = (uint64_t)pll->reference_freq * feedback_div;
1209 				vco = radeon_div(tmp, ref_div);
1210 
1211 				if (vco < pll_out_min) {
1212 					min_feed_div = feedback_div + 1;
1213 					continue;
1214 				} else if (vco > pll_out_max) {
1215 					max_feed_div = feedback_div;
1216 					continue;
1217 				}
1218 
1219 				while (min_frac_feed_div < max_frac_feed_div) {
1220 					frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1221 					tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1222 					tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1223 					current_freq = radeon_div(tmp, ref_div * post_div);
1224 
1225 					if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1226 						if (freq < current_freq)
1227 							error = 0xffffffff;
1228 						else
1229 							error = freq - current_freq;
1230 					} else
1231 						error = abs(current_freq - freq);
1232 					vco_diff = abs(vco - best_vco);
1233 
1234 					if ((best_vco == 0 && error < best_error) ||
1235 					    (best_vco != 0 &&
1236 					     ((best_error > 100 && error < best_error - 100) ||
1237 					      (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1238 						best_post_div = post_div;
1239 						best_ref_div = ref_div;
1240 						best_feedback_div = feedback_div;
1241 						best_frac_feedback_div = frac_feedback_div;
1242 						best_freq = current_freq;
1243 						best_error = error;
1244 						best_vco_diff = vco_diff;
1245 					} else if (current_freq == freq) {
1246 						if (best_freq == -1) {
1247 							best_post_div = post_div;
1248 							best_ref_div = ref_div;
1249 							best_feedback_div = feedback_div;
1250 							best_frac_feedback_div = frac_feedback_div;
1251 							best_freq = current_freq;
1252 							best_error = error;
1253 							best_vco_diff = vco_diff;
1254 						} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1255 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1256 							   ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1257 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1258 							   ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1259 							   ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1260 							best_post_div = post_div;
1261 							best_ref_div = ref_div;
1262 							best_feedback_div = feedback_div;
1263 							best_frac_feedback_div = frac_feedback_div;
1264 							best_freq = current_freq;
1265 							best_error = error;
1266 							best_vco_diff = vco_diff;
1267 						}
1268 					}
1269 					if (current_freq < freq)
1270 						min_frac_feed_div = frac_feedback_div + 1;
1271 					else
1272 						max_frac_feed_div = frac_feedback_div;
1273 				}
1274 				if (current_freq < freq)
1275 					min_feed_div = feedback_div + 1;
1276 				else
1277 					max_feed_div = feedback_div;
1278 			}
1279 		}
1280 	}
1281 
1282 	*dot_clock_p = best_freq / 10000;
1283 	*fb_div_p = best_feedback_div;
1284 	*frac_fb_div_p = best_frac_feedback_div;
1285 	*ref_div_p = best_ref_div;
1286 	*post_div_p = best_post_div;
1287 	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1288 		      (long long)freq,
1289 		      best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1290 		      best_ref_div, best_post_div);
1291 
1292 }
1293 
1294 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1295 	.destroy = drm_gem_fb_destroy,
1296 	.create_handle = drm_gem_fb_create_handle,
1297 };
1298 
1299 int
1300 radeon_framebuffer_init(struct drm_device *dev,
1301 			struct drm_framebuffer *fb,
1302 			const struct drm_mode_fb_cmd2 *mode_cmd,
1303 			struct drm_gem_object *obj)
1304 {
1305 	int ret;
1306 	fb->obj[0] = obj;
1307 	drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1308 	ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1309 	if (ret) {
1310 		fb->obj[0] = NULL;
1311 		return ret;
1312 	}
1313 	return 0;
1314 }
1315 
1316 static struct drm_framebuffer *
1317 radeon_user_framebuffer_create(struct drm_device *dev,
1318 			       struct drm_file *file_priv,
1319 			       const struct drm_mode_fb_cmd2 *mode_cmd)
1320 {
1321 	struct drm_gem_object *obj;
1322 	struct drm_framebuffer *fb;
1323 	int ret;
1324 
1325 	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1326 	if (obj ==  NULL) {
1327 		dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1328 			"can't create framebuffer\n", mode_cmd->handles[0]);
1329 		return ERR_PTR(-ENOENT);
1330 	}
1331 
1332 	/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1333 	if (obj->import_attach) {
1334 		DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1335 		drm_gem_object_put(obj);
1336 		return ERR_PTR(-EINVAL);
1337 	}
1338 
1339 	fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1340 	if (fb == NULL) {
1341 		drm_gem_object_put(obj);
1342 		return ERR_PTR(-ENOMEM);
1343 	}
1344 
1345 	ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1346 	if (ret) {
1347 		kfree(fb);
1348 		drm_gem_object_put(obj);
1349 		return ERR_PTR(ret);
1350 	}
1351 
1352 	return fb;
1353 }
1354 
1355 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1356 	.fb_create = radeon_user_framebuffer_create,
1357 	.output_poll_changed = drm_fb_helper_output_poll_changed,
1358 };
1359 
1360 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1361 {	{ 0, "driver" },
1362 	{ 1, "bios" },
1363 };
1364 
1365 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1366 {	{ TV_STD_NTSC, "ntsc" },
1367 	{ TV_STD_PAL, "pal" },
1368 	{ TV_STD_PAL_M, "pal-m" },
1369 	{ TV_STD_PAL_60, "pal-60" },
1370 	{ TV_STD_NTSC_J, "ntsc-j" },
1371 	{ TV_STD_SCART_PAL, "scart-pal" },
1372 	{ TV_STD_PAL_CN, "pal-cn" },
1373 	{ TV_STD_SECAM, "secam" },
1374 };
1375 
1376 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1377 {	{ UNDERSCAN_OFF, "off" },
1378 	{ UNDERSCAN_ON, "on" },
1379 	{ UNDERSCAN_AUTO, "auto" },
1380 };
1381 
1382 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1383 {	{ RADEON_AUDIO_DISABLE, "off" },
1384 	{ RADEON_AUDIO_ENABLE, "on" },
1385 	{ RADEON_AUDIO_AUTO, "auto" },
1386 };
1387 
1388 /* XXX support different dither options? spatial, temporal, both, etc. */
1389 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1390 {	{ RADEON_FMT_DITHER_DISABLE, "off" },
1391 	{ RADEON_FMT_DITHER_ENABLE, "on" },
1392 };
1393 
1394 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1395 {	{ RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1396 	{ RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1397 	{ RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1398 	{ RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1399 };
1400 
1401 static int radeon_modeset_create_props(struct radeon_device *rdev)
1402 {
1403 	int sz;
1404 
1405 	if (rdev->is_atom_bios) {
1406 		rdev->mode_info.coherent_mode_property =
1407 			drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1408 		if (!rdev->mode_info.coherent_mode_property)
1409 			return -ENOMEM;
1410 	}
1411 
1412 	if (!ASIC_IS_AVIVO(rdev)) {
1413 		sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1414 		rdev->mode_info.tmds_pll_property =
1415 			drm_property_create_enum(rdev->ddev, 0,
1416 					    "tmds_pll",
1417 					    radeon_tmds_pll_enum_list, sz);
1418 	}
1419 
1420 	rdev->mode_info.load_detect_property =
1421 		drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1422 	if (!rdev->mode_info.load_detect_property)
1423 		return -ENOMEM;
1424 
1425 	drm_mode_create_scaling_mode_property(rdev->ddev);
1426 
1427 	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1428 	rdev->mode_info.tv_std_property =
1429 		drm_property_create_enum(rdev->ddev, 0,
1430 				    "tv standard",
1431 				    radeon_tv_std_enum_list, sz);
1432 
1433 	sz = ARRAY_SIZE(radeon_underscan_enum_list);
1434 	rdev->mode_info.underscan_property =
1435 		drm_property_create_enum(rdev->ddev, 0,
1436 				    "underscan",
1437 				    radeon_underscan_enum_list, sz);
1438 
1439 	rdev->mode_info.underscan_hborder_property =
1440 		drm_property_create_range(rdev->ddev, 0,
1441 					"underscan hborder", 0, 128);
1442 	if (!rdev->mode_info.underscan_hborder_property)
1443 		return -ENOMEM;
1444 
1445 	rdev->mode_info.underscan_vborder_property =
1446 		drm_property_create_range(rdev->ddev, 0,
1447 					"underscan vborder", 0, 128);
1448 	if (!rdev->mode_info.underscan_vborder_property)
1449 		return -ENOMEM;
1450 
1451 	sz = ARRAY_SIZE(radeon_audio_enum_list);
1452 	rdev->mode_info.audio_property =
1453 		drm_property_create_enum(rdev->ddev, 0,
1454 					 "audio",
1455 					 radeon_audio_enum_list, sz);
1456 
1457 	sz = ARRAY_SIZE(radeon_dither_enum_list);
1458 	rdev->mode_info.dither_property =
1459 		drm_property_create_enum(rdev->ddev, 0,
1460 					 "dither",
1461 					 radeon_dither_enum_list, sz);
1462 
1463 	sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1464 	rdev->mode_info.output_csc_property =
1465 		drm_property_create_enum(rdev->ddev, 0,
1466 					 "output_csc",
1467 					 radeon_output_csc_enum_list, sz);
1468 
1469 	return 0;
1470 }
1471 
1472 void radeon_update_display_priority(struct radeon_device *rdev)
1473 {
1474 	/* adjustment options for the display watermarks */
1475 	if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1476 		/* set display priority to high for r3xx, rv515 chips
1477 		 * this avoids flickering due to underflow to the
1478 		 * display controllers during heavy acceleration.
1479 		 * Don't force high on rs4xx igp chips as it seems to
1480 		 * affect the sound card.  See kernel bug 15982.
1481 		 */
1482 		if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1483 		    !(rdev->flags & RADEON_IS_IGP))
1484 			rdev->disp_priority = 2;
1485 		else
1486 			rdev->disp_priority = 0;
1487 	} else
1488 		rdev->disp_priority = radeon_disp_priority;
1489 
1490 }
1491 
1492 /*
1493  * Allocate hdmi structs and determine register offsets
1494  */
1495 static void radeon_afmt_init(struct radeon_device *rdev)
1496 {
1497 	int i;
1498 
1499 	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1500 		rdev->mode_info.afmt[i] = NULL;
1501 
1502 	if (ASIC_IS_NODCE(rdev)) {
1503 		/* nothing to do */
1504 	} else if (ASIC_IS_DCE4(rdev)) {
1505 		static uint32_t eg_offsets[] = {
1506 			EVERGREEN_CRTC0_REGISTER_OFFSET,
1507 			EVERGREEN_CRTC1_REGISTER_OFFSET,
1508 			EVERGREEN_CRTC2_REGISTER_OFFSET,
1509 			EVERGREEN_CRTC3_REGISTER_OFFSET,
1510 			EVERGREEN_CRTC4_REGISTER_OFFSET,
1511 			EVERGREEN_CRTC5_REGISTER_OFFSET,
1512 			0x13830 - 0x7030,
1513 		};
1514 		int num_afmt;
1515 
1516 		/* DCE8 has 7 audio blocks tied to DIG encoders */
1517 		/* DCE6 has 6 audio blocks tied to DIG encoders */
1518 		/* DCE4/5 has 6 audio blocks tied to DIG encoders */
1519 		/* DCE4.1 has 2 audio blocks tied to DIG encoders */
1520 		if (ASIC_IS_DCE8(rdev))
1521 			num_afmt = 7;
1522 		else if (ASIC_IS_DCE6(rdev))
1523 			num_afmt = 6;
1524 		else if (ASIC_IS_DCE5(rdev))
1525 			num_afmt = 6;
1526 		else if (ASIC_IS_DCE41(rdev))
1527 			num_afmt = 2;
1528 		else /* DCE4 */
1529 			num_afmt = 6;
1530 
1531 		BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1532 		for (i = 0; i < num_afmt; i++) {
1533 			rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1534 			if (rdev->mode_info.afmt[i]) {
1535 				rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1536 				rdev->mode_info.afmt[i]->id = i;
1537 			}
1538 		}
1539 	} else if (ASIC_IS_DCE3(rdev)) {
1540 		/* DCE3.x has 2 audio blocks tied to DIG encoders */
1541 		rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1542 		if (rdev->mode_info.afmt[0]) {
1543 			rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1544 			rdev->mode_info.afmt[0]->id = 0;
1545 		}
1546 		rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1547 		if (rdev->mode_info.afmt[1]) {
1548 			rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1549 			rdev->mode_info.afmt[1]->id = 1;
1550 		}
1551 	} else if (ASIC_IS_DCE2(rdev)) {
1552 		/* DCE2 has at least 1 routable audio block */
1553 		rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1554 		if (rdev->mode_info.afmt[0]) {
1555 			rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1556 			rdev->mode_info.afmt[0]->id = 0;
1557 		}
1558 		/* r6xx has 2 routable audio blocks */
1559 		if (rdev->family >= CHIP_R600) {
1560 			rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1561 			if (rdev->mode_info.afmt[1]) {
1562 				rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1563 				rdev->mode_info.afmt[1]->id = 1;
1564 			}
1565 		}
1566 	}
1567 }
1568 
1569 static void radeon_afmt_fini(struct radeon_device *rdev)
1570 {
1571 	int i;
1572 
1573 	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1574 		kfree(rdev->mode_info.afmt[i]);
1575 		rdev->mode_info.afmt[i] = NULL;
1576 	}
1577 }
1578 
1579 int radeon_modeset_init(struct radeon_device *rdev)
1580 {
1581 	int i;
1582 	int ret;
1583 
1584 	drm_mode_config_init(rdev->ddev);
1585 	rdev->mode_info.mode_config_initialized = true;
1586 
1587 	rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1588 
1589 	if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1590 		rdev->ddev->mode_config.async_page_flip = true;
1591 
1592 	if (ASIC_IS_DCE5(rdev)) {
1593 		rdev->ddev->mode_config.max_width = 16384;
1594 		rdev->ddev->mode_config.max_height = 16384;
1595 	} else if (ASIC_IS_AVIVO(rdev)) {
1596 		rdev->ddev->mode_config.max_width = 8192;
1597 		rdev->ddev->mode_config.max_height = 8192;
1598 	} else {
1599 		rdev->ddev->mode_config.max_width = 4096;
1600 		rdev->ddev->mode_config.max_height = 4096;
1601 	}
1602 
1603 	rdev->ddev->mode_config.preferred_depth = 24;
1604 	rdev->ddev->mode_config.prefer_shadow = 1;
1605 
1606 	rdev->ddev->mode_config.fb_modifiers_not_supported = true;
1607 
1608 	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1609 
1610 	ret = radeon_modeset_create_props(rdev);
1611 	if (ret) {
1612 		return ret;
1613 	}
1614 
1615 	/* init i2c buses */
1616 	radeon_i2c_init(rdev);
1617 
1618 	/* check combios for a valid hardcoded EDID - Sun servers */
1619 	if (!rdev->is_atom_bios) {
1620 		/* check for hardcoded EDID in BIOS */
1621 		radeon_combios_check_hardcoded_edid(rdev);
1622 	}
1623 
1624 	/* allocate crtcs */
1625 	for (i = 0; i < rdev->num_crtc; i++) {
1626 		radeon_crtc_init(rdev->ddev, i);
1627 	}
1628 
1629 	/* okay we should have all the bios connectors */
1630 	ret = radeon_setup_enc_conn(rdev->ddev);
1631 	if (!ret) {
1632 		return ret;
1633 	}
1634 
1635 	/* init dig PHYs, disp eng pll */
1636 	if (rdev->is_atom_bios) {
1637 		radeon_atom_encoder_init(rdev);
1638 		radeon_atom_disp_eng_pll_init(rdev);
1639 	}
1640 
1641 	/* initialize hpd */
1642 	radeon_hpd_init(rdev);
1643 
1644 	/* setup afmt */
1645 	radeon_afmt_init(rdev);
1646 
1647 	radeon_fbdev_init(rdev);
1648 	drm_kms_helper_poll_init(rdev->ddev);
1649 
1650 	/* do pm late init */
1651 	ret = radeon_pm_late_init(rdev);
1652 
1653 	return 0;
1654 }
1655 
1656 void radeon_modeset_fini(struct radeon_device *rdev)
1657 {
1658 	if (rdev->mode_info.mode_config_initialized) {
1659 		drm_kms_helper_poll_fini(rdev->ddev);
1660 		radeon_hpd_fini(rdev);
1661 		drm_helper_force_disable_all(rdev->ddev);
1662 		radeon_fbdev_fini(rdev);
1663 		radeon_afmt_fini(rdev);
1664 		drm_mode_config_cleanup(rdev->ddev);
1665 		rdev->mode_info.mode_config_initialized = false;
1666 	}
1667 
1668 	kfree(rdev->mode_info.bios_hardcoded_edid);
1669 
1670 	/* free i2c buses */
1671 	radeon_i2c_fini(rdev);
1672 }
1673 
1674 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1675 {
1676 	/* try and guess if this is a tv or a monitor */
1677 	if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1678 	    (mode->vdisplay == 576) || /* 576p */
1679 	    (mode->vdisplay == 720) || /* 720p */
1680 	    (mode->vdisplay == 1080)) /* 1080p */
1681 		return true;
1682 	else
1683 		return false;
1684 }
1685 
1686 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1687 				const struct drm_display_mode *mode,
1688 				struct drm_display_mode *adjusted_mode)
1689 {
1690 	struct drm_device *dev = crtc->dev;
1691 	struct radeon_device *rdev = dev->dev_private;
1692 	struct drm_encoder *encoder;
1693 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1694 	struct radeon_encoder *radeon_encoder;
1695 	struct drm_connector *connector;
1696 	bool first = true;
1697 	u32 src_v = 1, dst_v = 1;
1698 	u32 src_h = 1, dst_h = 1;
1699 
1700 	radeon_crtc->h_border = 0;
1701 	radeon_crtc->v_border = 0;
1702 
1703 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1704 		if (encoder->crtc != crtc)
1705 			continue;
1706 		radeon_encoder = to_radeon_encoder(encoder);
1707 		connector = radeon_get_connector_for_encoder(encoder);
1708 
1709 		if (first) {
1710 			/* set scaling */
1711 			if (radeon_encoder->rmx_type == RMX_OFF)
1712 				radeon_crtc->rmx_type = RMX_OFF;
1713 			else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1714 				 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1715 				radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1716 			else
1717 				radeon_crtc->rmx_type = RMX_OFF;
1718 			/* copy native mode */
1719 			memcpy(&radeon_crtc->native_mode,
1720 			       &radeon_encoder->native_mode,
1721 				sizeof(struct drm_display_mode));
1722 			src_v = crtc->mode.vdisplay;
1723 			dst_v = radeon_crtc->native_mode.vdisplay;
1724 			src_h = crtc->mode.hdisplay;
1725 			dst_h = radeon_crtc->native_mode.hdisplay;
1726 
1727 			/* fix up for overscan on hdmi */
1728 			if (ASIC_IS_AVIVO(rdev) &&
1729 			    (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1730 			    ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1731 			     ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1732 			      drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1733 			      is_hdtv_mode(mode)))) {
1734 				if (radeon_encoder->underscan_hborder != 0)
1735 					radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1736 				else
1737 					radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1738 				if (radeon_encoder->underscan_vborder != 0)
1739 					radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1740 				else
1741 					radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1742 				radeon_crtc->rmx_type = RMX_FULL;
1743 				src_v = crtc->mode.vdisplay;
1744 				dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1745 				src_h = crtc->mode.hdisplay;
1746 				dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1747 			}
1748 			first = false;
1749 		} else {
1750 			if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1751 				/* WARNING: Right now this can't happen but
1752 				 * in the future we need to check that scaling
1753 				 * are consistent across different encoder
1754 				 * (ie all encoder can work with the same
1755 				 *  scaling).
1756 				 */
1757 				DRM_ERROR("Scaling not consistent across encoder.\n");
1758 				return false;
1759 			}
1760 		}
1761 	}
1762 	if (radeon_crtc->rmx_type != RMX_OFF) {
1763 		fixed20_12 a, b;
1764 		a.full = dfixed_const(src_v);
1765 		b.full = dfixed_const(dst_v);
1766 		radeon_crtc->vsc.full = dfixed_div(a, b);
1767 		a.full = dfixed_const(src_h);
1768 		b.full = dfixed_const(dst_h);
1769 		radeon_crtc->hsc.full = dfixed_div(a, b);
1770 	} else {
1771 		radeon_crtc->vsc.full = dfixed_const(1);
1772 		radeon_crtc->hsc.full = dfixed_const(1);
1773 	}
1774 	return true;
1775 }
1776 
1777 /*
1778  * Retrieve current video scanout position of crtc on a given gpu, and
1779  * an optional accurate timestamp of when query happened.
1780  *
1781  * \param dev Device to query.
1782  * \param crtc Crtc to query.
1783  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1784  *              For driver internal use only also supports these flags:
1785  *
1786  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1787  *              of a fudged earlier start of vblank.
1788  *
1789  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1790  *              fudged earlier start of vblank in *vpos and the distance
1791  *              to true start of vblank in *hpos.
1792  *
1793  * \param *vpos Location where vertical scanout position should be stored.
1794  * \param *hpos Location where horizontal scanout position should go.
1795  * \param *stime Target location for timestamp taken immediately before
1796  *               scanout position query. Can be NULL to skip timestamp.
1797  * \param *etime Target location for timestamp taken immediately after
1798  *               scanout position query. Can be NULL to skip timestamp.
1799  *
1800  * Returns vpos as a positive number while in active scanout area.
1801  * Returns vpos as a negative number inside vblank, counting the number
1802  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1803  * until start of active scanout / end of vblank."
1804  *
1805  * \return Flags, or'ed together as follows:
1806  *
1807  * DRM_SCANOUTPOS_VALID = Query successful.
1808  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1809  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1810  * this flag means that returned position may be offset by a constant but
1811  * unknown small number of scanlines wrt. real scanout position.
1812  *
1813  */
1814 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1815 			       unsigned int flags, int *vpos, int *hpos,
1816 			       ktime_t *stime, ktime_t *etime,
1817 			       const struct drm_display_mode *mode)
1818 {
1819 	u32 stat_crtc = 0, vbl = 0, position = 0;
1820 	int vbl_start, vbl_end, vtotal, ret = 0;
1821 	bool in_vbl = true;
1822 
1823 	struct radeon_device *rdev = dev->dev_private;
1824 
1825 	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1826 
1827 	/* Get optional system timestamp before query. */
1828 	if (stime)
1829 		*stime = ktime_get();
1830 
1831 	if (ASIC_IS_DCE4(rdev)) {
1832 		if (pipe == 0) {
1833 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1834 				     EVERGREEN_CRTC0_REGISTER_OFFSET);
1835 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1836 					  EVERGREEN_CRTC0_REGISTER_OFFSET);
1837 			ret |= DRM_SCANOUTPOS_VALID;
1838 		}
1839 		if (pipe == 1) {
1840 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1841 				     EVERGREEN_CRTC1_REGISTER_OFFSET);
1842 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1843 					  EVERGREEN_CRTC1_REGISTER_OFFSET);
1844 			ret |= DRM_SCANOUTPOS_VALID;
1845 		}
1846 		if (pipe == 2) {
1847 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1848 				     EVERGREEN_CRTC2_REGISTER_OFFSET);
1849 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1850 					  EVERGREEN_CRTC2_REGISTER_OFFSET);
1851 			ret |= DRM_SCANOUTPOS_VALID;
1852 		}
1853 		if (pipe == 3) {
1854 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1855 				     EVERGREEN_CRTC3_REGISTER_OFFSET);
1856 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1857 					  EVERGREEN_CRTC3_REGISTER_OFFSET);
1858 			ret |= DRM_SCANOUTPOS_VALID;
1859 		}
1860 		if (pipe == 4) {
1861 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1862 				     EVERGREEN_CRTC4_REGISTER_OFFSET);
1863 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1864 					  EVERGREEN_CRTC4_REGISTER_OFFSET);
1865 			ret |= DRM_SCANOUTPOS_VALID;
1866 		}
1867 		if (pipe == 5) {
1868 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1869 				     EVERGREEN_CRTC5_REGISTER_OFFSET);
1870 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1871 					  EVERGREEN_CRTC5_REGISTER_OFFSET);
1872 			ret |= DRM_SCANOUTPOS_VALID;
1873 		}
1874 	} else if (ASIC_IS_AVIVO(rdev)) {
1875 		if (pipe == 0) {
1876 			vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1877 			position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1878 			ret |= DRM_SCANOUTPOS_VALID;
1879 		}
1880 		if (pipe == 1) {
1881 			vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1882 			position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1883 			ret |= DRM_SCANOUTPOS_VALID;
1884 		}
1885 	} else {
1886 		/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1887 		if (pipe == 0) {
1888 			/* Assume vbl_end == 0, get vbl_start from
1889 			 * upper 16 bits.
1890 			 */
1891 			vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1892 				RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1893 			/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1894 			position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1895 			stat_crtc = RREG32(RADEON_CRTC_STATUS);
1896 			if (!(stat_crtc & 1))
1897 				in_vbl = false;
1898 
1899 			ret |= DRM_SCANOUTPOS_VALID;
1900 		}
1901 		if (pipe == 1) {
1902 			vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1903 				RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1904 			position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1905 			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1906 			if (!(stat_crtc & 1))
1907 				in_vbl = false;
1908 
1909 			ret |= DRM_SCANOUTPOS_VALID;
1910 		}
1911 	}
1912 
1913 	/* Get optional system timestamp after query. */
1914 	if (etime)
1915 		*etime = ktime_get();
1916 
1917 	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1918 
1919 	/* Decode into vertical and horizontal scanout position. */
1920 	*vpos = position & 0x1fff;
1921 	*hpos = (position >> 16) & 0x1fff;
1922 
1923 	/* Valid vblank area boundaries from gpu retrieved? */
1924 	if (vbl > 0) {
1925 		/* Yes: Decode. */
1926 		ret |= DRM_SCANOUTPOS_ACCURATE;
1927 		vbl_start = vbl & 0x1fff;
1928 		vbl_end = (vbl >> 16) & 0x1fff;
1929 	}
1930 	else {
1931 		/* No: Fake something reasonable which gives at least ok results. */
1932 		vbl_start = mode->crtc_vdisplay;
1933 		vbl_end = 0;
1934 	}
1935 
1936 	/* Called from driver internal vblank counter query code? */
1937 	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1938 	    /* Caller wants distance from real vbl_start in *hpos */
1939 	    *hpos = *vpos - vbl_start;
1940 	}
1941 
1942 	/* Fudge vblank to start a few scanlines earlier to handle the
1943 	 * problem that vblank irqs fire a few scanlines before start
1944 	 * of vblank. Some driver internal callers need the true vblank
1945 	 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1946 	 *
1947 	 * The cause of the "early" vblank irq is that the irq is triggered
1948 	 * by the line buffer logic when the line buffer read position enters
1949 	 * the vblank, whereas our crtc scanout position naturally lags the
1950 	 * line buffer read position.
1951 	 */
1952 	if (!(flags & USE_REAL_VBLANKSTART))
1953 		vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1954 
1955 	/* Test scanout position against vblank region. */
1956 	if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1957 		in_vbl = false;
1958 
1959 	/* In vblank? */
1960 	if (in_vbl)
1961 	    ret |= DRM_SCANOUTPOS_IN_VBLANK;
1962 
1963 	/* Called from driver internal vblank counter query code? */
1964 	if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1965 		/* Caller wants distance from fudged earlier vbl_start */
1966 		*vpos -= vbl_start;
1967 		return ret;
1968 	}
1969 
1970 	/* Check if inside vblank area and apply corrective offsets:
1971 	 * vpos will then be >=0 in video scanout area, but negative
1972 	 * within vblank area, counting down the number of lines until
1973 	 * start of scanout.
1974 	 */
1975 
1976 	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
1977 	if (in_vbl && (*vpos >= vbl_start)) {
1978 		vtotal = mode->crtc_vtotal;
1979 		*vpos = *vpos - vtotal;
1980 	}
1981 
1982 	/* Correct for shifted end of vbl at vbl_end. */
1983 	*vpos = *vpos - vbl_end;
1984 
1985 	return ret;
1986 }
1987 
1988 bool
1989 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1990 				 bool in_vblank_irq, int *vpos, int *hpos,
1991 				 ktime_t *stime, ktime_t *etime,
1992 				 const struct drm_display_mode *mode)
1993 {
1994 	struct drm_device *dev = crtc->dev;
1995 	unsigned int pipe = crtc->index;
1996 
1997 	return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1998 					  stime, etime, mode);
1999 }
2000