1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/radeon_drm.h> 28 #include "radeon.h" 29 30 #include "atom.h" 31 #include <asm/div64.h> 32 33 #include <linux/pm_runtime.h> 34 #include <drm/drm_crtc_helper.h> 35 #include <drm/drm_gem_framebuffer_helper.h> 36 #include <drm/drm_fb_helper.h> 37 #include <drm/drm_plane_helper.h> 38 #include <drm/drm_edid.h> 39 40 #include <linux/gcd.h> 41 42 static void avivo_crtc_load_lut(struct drm_crtc *crtc) 43 { 44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 45 struct drm_device *dev = crtc->dev; 46 struct radeon_device *rdev = dev->dev_private; 47 u16 *r, *g, *b; 48 int i; 49 50 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 51 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); 52 53 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 54 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 55 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 56 57 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 58 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 59 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 60 61 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); 62 WREG32(AVIVO_DC_LUT_RW_MODE, 0); 63 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); 64 65 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); 66 r = crtc->gamma_store; 67 g = r + crtc->gamma_size; 68 b = g + crtc->gamma_size; 69 for (i = 0; i < 256; i++) { 70 WREG32(AVIVO_DC_LUT_30_COLOR, 71 ((*r++ & 0xffc0) << 14) | 72 ((*g++ & 0xffc0) << 4) | 73 (*b++ >> 6)); 74 } 75 76 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 77 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 78 } 79 80 static void dce4_crtc_load_lut(struct drm_crtc *crtc) 81 { 82 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 83 struct drm_device *dev = crtc->dev; 84 struct radeon_device *rdev = dev->dev_private; 85 u16 *r, *g, *b; 86 int i; 87 88 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 89 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 90 91 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 92 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 93 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 94 95 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 96 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 97 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 98 99 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 100 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 101 102 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 103 r = crtc->gamma_store; 104 g = r + crtc->gamma_size; 105 b = g + crtc->gamma_size; 106 for (i = 0; i < 256; i++) { 107 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 108 ((*r++ & 0xffc0) << 14) | 109 ((*g++ & 0xffc0) << 4) | 110 (*b++ >> 6)); 111 } 112 } 113 114 static void dce5_crtc_load_lut(struct drm_crtc *crtc) 115 { 116 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 117 struct drm_device *dev = crtc->dev; 118 struct radeon_device *rdev = dev->dev_private; 119 u16 *r, *g, *b; 120 int i; 121 122 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); 123 124 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 125 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | 126 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); 127 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, 128 NI_GRPH_PRESCALE_BYPASS); 129 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, 130 NI_OVL_PRESCALE_BYPASS); 131 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, 132 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | 133 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); 134 135 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); 136 137 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); 138 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); 139 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); 140 141 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); 142 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); 143 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); 144 145 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); 146 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); 147 148 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); 149 r = crtc->gamma_store; 150 g = r + crtc->gamma_size; 151 b = g + crtc->gamma_size; 152 for (i = 0; i < 256; i++) { 153 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, 154 ((*r++ & 0xffc0) << 14) | 155 ((*g++ & 0xffc0) << 4) | 156 (*b++ >> 6)); 157 } 158 159 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, 160 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 161 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 162 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | 163 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); 164 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, 165 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | 166 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); 167 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, 168 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | 169 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); 170 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, 171 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | 172 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); 173 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 174 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); 175 if (ASIC_IS_DCE8(rdev)) { 176 /* XXX this only needs to be programmed once per crtc at startup, 177 * not sure where the best place for it is 178 */ 179 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, 180 CIK_CURSOR_ALPHA_BLND_ENA); 181 } 182 } 183 184 static void legacy_crtc_load_lut(struct drm_crtc *crtc) 185 { 186 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 187 struct drm_device *dev = crtc->dev; 188 struct radeon_device *rdev = dev->dev_private; 189 u16 *r, *g, *b; 190 int i; 191 uint32_t dac2_cntl; 192 193 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 194 if (radeon_crtc->crtc_id == 0) 195 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; 196 else 197 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; 198 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 199 200 WREG8(RADEON_PALETTE_INDEX, 0); 201 r = crtc->gamma_store; 202 g = r + crtc->gamma_size; 203 b = g + crtc->gamma_size; 204 for (i = 0; i < 256; i++) { 205 WREG32(RADEON_PALETTE_30_DATA, 206 ((*r++ & 0xffc0) << 14) | 207 ((*g++ & 0xffc0) << 4) | 208 (*b++ >> 6)); 209 } 210 } 211 212 void radeon_crtc_load_lut(struct drm_crtc *crtc) 213 { 214 struct drm_device *dev = crtc->dev; 215 struct radeon_device *rdev = dev->dev_private; 216 217 if (!crtc->enabled) 218 return; 219 220 if (ASIC_IS_DCE5(rdev)) 221 dce5_crtc_load_lut(crtc); 222 else if (ASIC_IS_DCE4(rdev)) 223 dce4_crtc_load_lut(crtc); 224 else if (ASIC_IS_AVIVO(rdev)) 225 avivo_crtc_load_lut(crtc); 226 else 227 legacy_crtc_load_lut(crtc); 228 } 229 230 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 231 u16 *blue, uint32_t size, 232 struct drm_modeset_acquire_ctx *ctx) 233 { 234 radeon_crtc_load_lut(crtc); 235 236 return 0; 237 } 238 239 static void radeon_crtc_destroy(struct drm_crtc *crtc) 240 { 241 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 242 243 drm_crtc_cleanup(crtc); 244 destroy_workqueue(radeon_crtc->flip_queue); 245 kfree(radeon_crtc); 246 } 247 248 /** 249 * radeon_unpin_work_func - unpin old buffer object 250 * 251 * @__work - kernel work item 252 * 253 * Unpin the old frame buffer object outside of the interrupt handler 254 */ 255 static void radeon_unpin_work_func(struct work_struct *__work) 256 { 257 struct radeon_flip_work *work = 258 container_of(__work, struct radeon_flip_work, unpin_work); 259 int r; 260 261 /* unpin of the old buffer */ 262 r = radeon_bo_reserve(work->old_rbo, false); 263 if (likely(r == 0)) { 264 r = radeon_bo_unpin(work->old_rbo); 265 if (unlikely(r != 0)) { 266 DRM_ERROR("failed to unpin buffer after flip\n"); 267 } 268 radeon_bo_unreserve(work->old_rbo); 269 } else 270 DRM_ERROR("failed to reserve buffer after flip\n"); 271 272 drm_gem_object_put_unlocked(&work->old_rbo->gem_base); 273 kfree(work); 274 } 275 276 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) 277 { 278 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 279 unsigned long flags; 280 u32 update_pending; 281 int vpos, hpos; 282 283 /* can happen during initialization */ 284 if (radeon_crtc == NULL) 285 return; 286 287 /* Skip the pageflip completion check below (based on polling) on 288 * asics which reliably support hw pageflip completion irqs. pflip 289 * irqs are a reliable and race-free method of handling pageflip 290 * completion detection. A use_pflipirq module parameter < 2 allows 291 * to override this in case of asics with faulty pflip irqs. 292 * A module parameter of 0 would only use this polling based path, 293 * a parameter of 1 would use pflip irq only as a backup to this 294 * path, as in Linux 3.16. 295 */ 296 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) 297 return; 298 299 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 300 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 301 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 302 "RADEON_FLIP_SUBMITTED(%d)\n", 303 radeon_crtc->flip_status, 304 RADEON_FLIP_SUBMITTED); 305 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 306 return; 307 } 308 309 update_pending = radeon_page_flip_pending(rdev, crtc_id); 310 311 /* Has the pageflip already completed in crtc, or is it certain 312 * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides 313 * distance to start of "fudged earlier" vblank in vpos, distance to 314 * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in 315 * the last few scanlines before start of real vblank, where the vblank 316 * irq can fire, so we have sampled update_pending a bit too early and 317 * know the flip will complete at leading edge of the upcoming real 318 * vblank. On pre-AVIVO hardware, flips also complete inside the real 319 * vblank, not only at leading edge, so if update_pending for hpos >= 0 320 * == inside real vblank, the flip will complete almost immediately. 321 * Note that this method of completion handling is still not 100% race 322 * free, as we could execute before the radeon_flip_work_func managed 323 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, 324 * but the flip still gets programmed into hw and completed during 325 * vblank, leading to a delayed emission of the flip completion event. 326 * This applies at least to pre-AVIVO hardware, where flips are always 327 * completing inside vblank, not only at leading edge of vblank. 328 */ 329 if (update_pending && 330 (DRM_SCANOUTPOS_VALID & 331 radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 332 GET_DISTANCE_TO_VBLANKSTART, 333 &vpos, &hpos, NULL, NULL, 334 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 335 ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) { 336 /* crtc didn't flip in this target vblank interval, 337 * but flip is pending in crtc. Based on the current 338 * scanout position we know that the current frame is 339 * (nearly) complete and the flip will (likely) 340 * complete before the start of the next frame. 341 */ 342 update_pending = 0; 343 } 344 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 345 if (!update_pending) 346 radeon_crtc_handle_flip(rdev, crtc_id); 347 } 348 349 /** 350 * radeon_crtc_handle_flip - page flip completed 351 * 352 * @rdev: radeon device pointer 353 * @crtc_id: crtc number this event is for 354 * 355 * Called when we are sure that a page flip for this crtc is completed. 356 */ 357 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) 358 { 359 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 360 struct radeon_flip_work *work; 361 unsigned long flags; 362 363 /* this can happen at init */ 364 if (radeon_crtc == NULL) 365 return; 366 367 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 368 work = radeon_crtc->flip_work; 369 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { 370 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " 371 "RADEON_FLIP_SUBMITTED(%d)\n", 372 radeon_crtc->flip_status, 373 RADEON_FLIP_SUBMITTED); 374 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 375 return; 376 } 377 378 /* Pageflip completed. Clean up. */ 379 radeon_crtc->flip_status = RADEON_FLIP_NONE; 380 radeon_crtc->flip_work = NULL; 381 382 /* wakeup userspace */ 383 if (work->event) 384 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); 385 386 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 387 388 drm_crtc_vblank_put(&radeon_crtc->base); 389 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 390 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 391 } 392 393 /** 394 * radeon_flip_work_func - page flip framebuffer 395 * 396 * @work - kernel work item 397 * 398 * Wait for the buffer object to become idle and do the actual page flip 399 */ 400 static void radeon_flip_work_func(struct work_struct *__work) 401 { 402 struct radeon_flip_work *work = 403 container_of(__work, struct radeon_flip_work, flip_work); 404 struct radeon_device *rdev = work->rdev; 405 struct drm_device *dev = rdev->ddev; 406 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; 407 408 struct drm_crtc *crtc = &radeon_crtc->base; 409 unsigned long flags; 410 int r; 411 int vpos, hpos; 412 413 down_read(&rdev->exclusive_lock); 414 if (work->fence) { 415 struct radeon_fence *fence; 416 417 fence = to_radeon_fence(work->fence); 418 if (fence && fence->rdev == rdev) { 419 r = radeon_fence_wait(fence, false); 420 if (r == -EDEADLK) { 421 up_read(&rdev->exclusive_lock); 422 do { 423 r = radeon_gpu_reset(rdev); 424 } while (r == -EAGAIN); 425 down_read(&rdev->exclusive_lock); 426 } 427 } else 428 r = dma_fence_wait(work->fence, false); 429 430 if (r) 431 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); 432 433 /* We continue with the page flip even if we failed to wait on 434 * the fence, otherwise the DRM core and userspace will be 435 * confused about which BO the CRTC is scanning out 436 */ 437 438 dma_fence_put(work->fence); 439 work->fence = NULL; 440 } 441 442 /* Wait until we're out of the vertical blank period before the one 443 * targeted by the flip. Always wait on pre DCE4 to avoid races with 444 * flip completion handling from vblank irq, as these old asics don't 445 * have reliable pageflip completion interrupts. 446 */ 447 while (radeon_crtc->enabled && 448 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, 449 &vpos, &hpos, NULL, NULL, 450 &crtc->hwmode) 451 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 452 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 453 (!ASIC_IS_AVIVO(rdev) || 454 ((int) (work->target_vblank - 455 dev->driver->get_vblank_counter(dev, work->crtc_id)) > 0))) 456 usleep_range(1000, 2000); 457 458 /* We borrow the event spin lock for protecting flip_status */ 459 spin_lock_irqsave(&crtc->dev->event_lock, flags); 460 461 /* set the proper interrupt */ 462 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 463 464 /* do the flip (mmio) */ 465 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); 466 467 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; 468 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 469 up_read(&rdev->exclusive_lock); 470 } 471 472 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, 473 struct drm_framebuffer *fb, 474 struct drm_pending_vblank_event *event, 475 uint32_t page_flip_flags, 476 uint32_t target, 477 struct drm_modeset_acquire_ctx *ctx) 478 { 479 struct drm_device *dev = crtc->dev; 480 struct radeon_device *rdev = dev->dev_private; 481 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 482 struct drm_gem_object *obj; 483 struct radeon_flip_work *work; 484 struct radeon_bo *new_rbo; 485 uint32_t tiling_flags, pitch_pixels; 486 uint64_t base; 487 unsigned long flags; 488 int r; 489 490 work = kzalloc(sizeof *work, GFP_KERNEL); 491 if (work == NULL) 492 return -ENOMEM; 493 494 INIT_WORK(&work->flip_work, radeon_flip_work_func); 495 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); 496 497 work->rdev = rdev; 498 work->crtc_id = radeon_crtc->crtc_id; 499 work->event = event; 500 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 501 502 /* schedule unpin of the old buffer */ 503 obj = crtc->primary->fb->obj[0]; 504 505 /* take a reference to the old object */ 506 drm_gem_object_get(obj); 507 work->old_rbo = gem_to_radeon_bo(obj); 508 509 obj = fb->obj[0]; 510 new_rbo = gem_to_radeon_bo(obj); 511 512 /* pin the new buffer */ 513 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", 514 work->old_rbo, new_rbo); 515 516 r = radeon_bo_reserve(new_rbo, false); 517 if (unlikely(r != 0)) { 518 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 519 goto cleanup; 520 } 521 /* Only 27 bit offset for legacy CRTC */ 522 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM, 523 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base); 524 if (unlikely(r != 0)) { 525 radeon_bo_unreserve(new_rbo); 526 r = -EINVAL; 527 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 528 goto cleanup; 529 } 530 work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv)); 531 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 532 radeon_bo_unreserve(new_rbo); 533 534 if (!ASIC_IS_AVIVO(rdev)) { 535 /* crtc offset is from display base addr not FB location */ 536 base -= radeon_crtc->legacy_display_base_addr; 537 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 538 539 if (tiling_flags & RADEON_TILING_MACRO) { 540 if (ASIC_IS_R300(rdev)) { 541 base &= ~0x7ff; 542 } else { 543 int byteshift = fb->format->cpp[0] * 8 >> 4; 544 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; 545 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); 546 } 547 } else { 548 int offset = crtc->y * pitch_pixels + crtc->x; 549 switch (fb->format->cpp[0] * 8) { 550 case 8: 551 default: 552 offset *= 1; 553 break; 554 case 15: 555 case 16: 556 offset *= 2; 557 break; 558 case 24: 559 offset *= 3; 560 break; 561 case 32: 562 offset *= 4; 563 break; 564 } 565 base += offset; 566 } 567 base &= ~7; 568 } 569 work->base = base; 570 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 571 dev->driver->get_vblank_counter(dev, work->crtc_id); 572 573 /* We borrow the event spin lock for protecting flip_work */ 574 spin_lock_irqsave(&crtc->dev->event_lock, flags); 575 576 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { 577 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 578 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 579 r = -EBUSY; 580 goto pflip_cleanup; 581 } 582 radeon_crtc->flip_status = RADEON_FLIP_PENDING; 583 radeon_crtc->flip_work = work; 584 585 /* update crtc fb */ 586 crtc->primary->fb = fb; 587 588 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 589 590 queue_work(radeon_crtc->flip_queue, &work->flip_work); 591 return 0; 592 593 pflip_cleanup: 594 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) { 595 DRM_ERROR("failed to reserve new rbo in error path\n"); 596 goto cleanup; 597 } 598 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) { 599 DRM_ERROR("failed to unpin new rbo in error path\n"); 600 } 601 radeon_bo_unreserve(new_rbo); 602 603 cleanup: 604 drm_gem_object_put_unlocked(&work->old_rbo->gem_base); 605 dma_fence_put(work->fence); 606 kfree(work); 607 return r; 608 } 609 610 static int 611 radeon_crtc_set_config(struct drm_mode_set *set, 612 struct drm_modeset_acquire_ctx *ctx) 613 { 614 struct drm_device *dev; 615 struct radeon_device *rdev; 616 struct drm_crtc *crtc; 617 bool active = false; 618 int ret; 619 620 if (!set || !set->crtc) 621 return -EINVAL; 622 623 dev = set->crtc->dev; 624 625 ret = pm_runtime_get_sync(dev->dev); 626 if (ret < 0) 627 return ret; 628 629 ret = drm_crtc_helper_set_config(set, ctx); 630 631 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 632 if (crtc->enabled) 633 active = true; 634 635 pm_runtime_mark_last_busy(dev->dev); 636 637 rdev = dev->dev_private; 638 /* if we have active crtcs and we don't have a power ref, 639 take the current one */ 640 if (active && !rdev->have_disp_power_ref) { 641 rdev->have_disp_power_ref = true; 642 return ret; 643 } 644 /* if we have no active crtcs, then drop the power ref 645 we got before */ 646 if (!active && rdev->have_disp_power_ref) { 647 pm_runtime_put_autosuspend(dev->dev); 648 rdev->have_disp_power_ref = false; 649 } 650 651 /* drop the power reference we got coming in here */ 652 pm_runtime_put_autosuspend(dev->dev); 653 return ret; 654 } 655 656 static const struct drm_crtc_funcs radeon_crtc_funcs = { 657 .cursor_set2 = radeon_crtc_cursor_set2, 658 .cursor_move = radeon_crtc_cursor_move, 659 .gamma_set = radeon_crtc_gamma_set, 660 .set_config = radeon_crtc_set_config, 661 .destroy = radeon_crtc_destroy, 662 .page_flip_target = radeon_crtc_page_flip_target, 663 }; 664 665 static void radeon_crtc_init(struct drm_device *dev, int index) 666 { 667 struct radeon_device *rdev = dev->dev_private; 668 struct radeon_crtc *radeon_crtc; 669 int i; 670 671 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 672 if (radeon_crtc == NULL) 673 return; 674 675 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); 676 677 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); 678 radeon_crtc->crtc_id = index; 679 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 680 rdev->mode_info.crtcs[index] = radeon_crtc; 681 682 if (rdev->family >= CHIP_BONAIRE) { 683 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 684 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 685 } else { 686 radeon_crtc->max_cursor_width = CURSOR_WIDTH; 687 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; 688 } 689 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; 690 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; 691 692 #if 0 693 radeon_crtc->mode_set.crtc = &radeon_crtc->base; 694 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); 695 radeon_crtc->mode_set.num_connectors = 0; 696 #endif 697 698 for (i = 0; i < 256; i++) { 699 radeon_crtc->lut_r[i] = i << 2; 700 radeon_crtc->lut_g[i] = i << 2; 701 radeon_crtc->lut_b[i] = i << 2; 702 } 703 704 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) 705 radeon_atombios_init_crtc(dev, radeon_crtc); 706 else 707 radeon_legacy_init_crtc(dev, radeon_crtc); 708 } 709 710 static const char *encoder_names[38] = { 711 "NONE", 712 "INTERNAL_LVDS", 713 "INTERNAL_TMDS1", 714 "INTERNAL_TMDS2", 715 "INTERNAL_DAC1", 716 "INTERNAL_DAC2", 717 "INTERNAL_SDVOA", 718 "INTERNAL_SDVOB", 719 "SI170B", 720 "CH7303", 721 "CH7301", 722 "INTERNAL_DVO1", 723 "EXTERNAL_SDVOA", 724 "EXTERNAL_SDVOB", 725 "TITFP513", 726 "INTERNAL_LVTM1", 727 "VT1623", 728 "HDMI_SI1930", 729 "HDMI_INTERNAL", 730 "INTERNAL_KLDSCP_TMDS1", 731 "INTERNAL_KLDSCP_DVO1", 732 "INTERNAL_KLDSCP_DAC1", 733 "INTERNAL_KLDSCP_DAC2", 734 "SI178", 735 "MVPU_FPGA", 736 "INTERNAL_DDI", 737 "VT1625", 738 "HDMI_SI1932", 739 "DP_AN9801", 740 "DP_DP501", 741 "INTERNAL_UNIPHY", 742 "INTERNAL_KLDSCP_LVTMA", 743 "INTERNAL_UNIPHY1", 744 "INTERNAL_UNIPHY2", 745 "NUTMEG", 746 "TRAVIS", 747 "INTERNAL_VCE", 748 "INTERNAL_UNIPHY3", 749 }; 750 751 static const char *hpd_names[6] = { 752 "HPD1", 753 "HPD2", 754 "HPD3", 755 "HPD4", 756 "HPD5", 757 "HPD6", 758 }; 759 760 static void radeon_print_display_setup(struct drm_device *dev) 761 { 762 struct drm_connector *connector; 763 struct radeon_connector *radeon_connector; 764 struct drm_encoder *encoder; 765 struct radeon_encoder *radeon_encoder; 766 uint32_t devices; 767 int i = 0; 768 769 DRM_INFO("Radeon Display Connectors\n"); 770 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 771 radeon_connector = to_radeon_connector(connector); 772 DRM_INFO("Connector %d:\n", i); 773 DRM_INFO(" %s\n", connector->name); 774 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 775 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 776 if (radeon_connector->ddc_bus) { 777 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 778 radeon_connector->ddc_bus->rec.mask_clk_reg, 779 radeon_connector->ddc_bus->rec.mask_data_reg, 780 radeon_connector->ddc_bus->rec.a_clk_reg, 781 radeon_connector->ddc_bus->rec.a_data_reg, 782 radeon_connector->ddc_bus->rec.en_clk_reg, 783 radeon_connector->ddc_bus->rec.en_data_reg, 784 radeon_connector->ddc_bus->rec.y_clk_reg, 785 radeon_connector->ddc_bus->rec.y_data_reg); 786 if (radeon_connector->router.ddc_valid) 787 DRM_INFO(" DDC Router 0x%x/0x%x\n", 788 radeon_connector->router.ddc_mux_control_pin, 789 radeon_connector->router.ddc_mux_state); 790 if (radeon_connector->router.cd_valid) 791 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 792 radeon_connector->router.cd_mux_control_pin, 793 radeon_connector->router.cd_mux_state); 794 } else { 795 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 796 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 797 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 798 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 799 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 800 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 801 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 802 } 803 DRM_INFO(" Encoders:\n"); 804 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 805 radeon_encoder = to_radeon_encoder(encoder); 806 devices = radeon_encoder->devices & radeon_connector->devices; 807 if (devices) { 808 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 809 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); 810 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 811 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); 812 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 813 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); 814 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 815 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); 816 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 817 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); 818 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 819 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); 820 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 821 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); 822 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 823 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); 824 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 825 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); 826 if (devices & ATOM_DEVICE_TV1_SUPPORT) 827 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); 828 if (devices & ATOM_DEVICE_CV_SUPPORT) 829 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); 830 } 831 } 832 i++; 833 } 834 } 835 836 static bool radeon_setup_enc_conn(struct drm_device *dev) 837 { 838 struct radeon_device *rdev = dev->dev_private; 839 bool ret = false; 840 841 if (rdev->bios) { 842 if (rdev->is_atom_bios) { 843 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); 844 if (ret == false) 845 ret = radeon_get_atom_connector_info_from_object_table(dev); 846 } else { 847 ret = radeon_get_legacy_connector_info_from_bios(dev); 848 if (ret == false) 849 ret = radeon_get_legacy_connector_info_from_table(dev); 850 } 851 } else { 852 if (!ASIC_IS_AVIVO(rdev)) 853 ret = radeon_get_legacy_connector_info_from_table(dev); 854 } 855 if (ret) { 856 radeon_setup_encoder_clones(dev); 857 radeon_print_display_setup(dev); 858 } 859 860 return ret; 861 } 862 863 /* avivo */ 864 865 /** 866 * avivo_reduce_ratio - fractional number reduction 867 * 868 * @nom: nominator 869 * @den: denominator 870 * @nom_min: minimum value for nominator 871 * @den_min: minimum value for denominator 872 * 873 * Find the greatest common divisor and apply it on both nominator and 874 * denominator, but make nominator and denominator are at least as large 875 * as their minimum values. 876 */ 877 static void avivo_reduce_ratio(unsigned *nom, unsigned *den, 878 unsigned nom_min, unsigned den_min) 879 { 880 unsigned tmp; 881 882 /* reduce the numbers to a simpler ratio */ 883 tmp = gcd(*nom, *den); 884 *nom /= tmp; 885 *den /= tmp; 886 887 /* make sure nominator is large enough */ 888 if (*nom < nom_min) { 889 tmp = DIV_ROUND_UP(nom_min, *nom); 890 *nom *= tmp; 891 *den *= tmp; 892 } 893 894 /* make sure the denominator is large enough */ 895 if (*den < den_min) { 896 tmp = DIV_ROUND_UP(den_min, *den); 897 *nom *= tmp; 898 *den *= tmp; 899 } 900 } 901 902 /** 903 * avivo_get_fb_ref_div - feedback and ref divider calculation 904 * 905 * @nom: nominator 906 * @den: denominator 907 * @post_div: post divider 908 * @fb_div_max: feedback divider maximum 909 * @ref_div_max: reference divider maximum 910 * @fb_div: resulting feedback divider 911 * @ref_div: resulting reference divider 912 * 913 * Calculate feedback and reference divider for a given post divider. Makes 914 * sure we stay within the limits. 915 */ 916 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, 917 unsigned fb_div_max, unsigned ref_div_max, 918 unsigned *fb_div, unsigned *ref_div) 919 { 920 /* limit reference * post divider to a maximum */ 921 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); 922 923 /* get matching reference and feedback divider */ 924 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); 925 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 926 927 /* limit fb divider to its maximum */ 928 if (*fb_div > fb_div_max) { 929 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 930 *fb_div = fb_div_max; 931 } 932 } 933 934 /** 935 * radeon_compute_pll_avivo - compute PLL paramaters 936 * 937 * @pll: information about the PLL 938 * @dot_clock_p: resulting pixel clock 939 * fb_div_p: resulting feedback divider 940 * frac_fb_div_p: fractional part of the feedback divider 941 * ref_div_p: resulting reference divider 942 * post_div_p: resulting reference divider 943 * 944 * Try to calculate the PLL parameters to generate the given frequency: 945 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 946 */ 947 void radeon_compute_pll_avivo(struct radeon_pll *pll, 948 u32 freq, 949 u32 *dot_clock_p, 950 u32 *fb_div_p, 951 u32 *frac_fb_div_p, 952 u32 *ref_div_p, 953 u32 *post_div_p) 954 { 955 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 956 freq : freq / 10; 957 958 unsigned fb_div_min, fb_div_max, fb_div; 959 unsigned post_div_min, post_div_max, post_div; 960 unsigned ref_div_min, ref_div_max, ref_div; 961 unsigned post_div_best, diff_best; 962 unsigned nom, den; 963 964 /* determine allowed feedback divider range */ 965 fb_div_min = pll->min_feedback_div; 966 fb_div_max = pll->max_feedback_div; 967 968 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 969 fb_div_min *= 10; 970 fb_div_max *= 10; 971 } 972 973 /* determine allowed ref divider range */ 974 if (pll->flags & RADEON_PLL_USE_REF_DIV) 975 ref_div_min = pll->reference_div; 976 else 977 ref_div_min = pll->min_ref_div; 978 979 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && 980 pll->flags & RADEON_PLL_USE_REF_DIV) 981 ref_div_max = pll->reference_div; 982 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 983 /* fix for problems on RS880 */ 984 ref_div_max = min(pll->max_ref_div, 7u); 985 else 986 ref_div_max = pll->max_ref_div; 987 988 /* determine allowed post divider range */ 989 if (pll->flags & RADEON_PLL_USE_POST_DIV) { 990 post_div_min = pll->post_div; 991 post_div_max = pll->post_div; 992 } else { 993 unsigned vco_min, vco_max; 994 995 if (pll->flags & RADEON_PLL_IS_LCD) { 996 vco_min = pll->lcd_pll_out_min; 997 vco_max = pll->lcd_pll_out_max; 998 } else { 999 vco_min = pll->pll_out_min; 1000 vco_max = pll->pll_out_max; 1001 } 1002 1003 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1004 vco_min *= 10; 1005 vco_max *= 10; 1006 } 1007 1008 post_div_min = vco_min / target_clock; 1009 if ((target_clock * post_div_min) < vco_min) 1010 ++post_div_min; 1011 if (post_div_min < pll->min_post_div) 1012 post_div_min = pll->min_post_div; 1013 1014 post_div_max = vco_max / target_clock; 1015 if ((target_clock * post_div_max) > vco_max) 1016 --post_div_max; 1017 if (post_div_max > pll->max_post_div) 1018 post_div_max = pll->max_post_div; 1019 } 1020 1021 /* represent the searched ratio as fractional number */ 1022 nom = target_clock; 1023 den = pll->reference_freq; 1024 1025 /* reduce the numbers to a simpler ratio */ 1026 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 1027 1028 /* now search for a post divider */ 1029 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) 1030 post_div_best = post_div_min; 1031 else 1032 post_div_best = post_div_max; 1033 diff_best = ~0; 1034 1035 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 1036 unsigned diff; 1037 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, 1038 ref_div_max, &fb_div, &ref_div); 1039 diff = abs(target_clock - (pll->reference_freq * fb_div) / 1040 (ref_div * post_div)); 1041 1042 if (diff < diff_best || (diff == diff_best && 1043 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { 1044 1045 post_div_best = post_div; 1046 diff_best = diff; 1047 } 1048 } 1049 post_div = post_div_best; 1050 1051 /* get the feedback and reference divider for the optimal value */ 1052 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, 1053 &fb_div, &ref_div); 1054 1055 /* reduce the numbers to a simpler ratio once more */ 1056 /* this also makes sure that the reference divider is large enough */ 1057 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 1058 1059 /* avoid high jitter with small fractional dividers */ 1060 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 1061 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); 1062 if (fb_div < fb_div_min) { 1063 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1064 fb_div *= tmp; 1065 ref_div *= tmp; 1066 } 1067 } 1068 1069 /* and finally save the result */ 1070 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1071 *fb_div_p = fb_div / 10; 1072 *frac_fb_div_p = fb_div % 10; 1073 } else { 1074 *fb_div_p = fb_div; 1075 *frac_fb_div_p = 0; 1076 } 1077 1078 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 1079 (pll->reference_freq * *frac_fb_div_p)) / 1080 (ref_div * post_div * 10); 1081 *ref_div_p = ref_div; 1082 *post_div_p = post_div; 1083 1084 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1085 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 1086 ref_div, post_div); 1087 } 1088 1089 /* pre-avivo */ 1090 static inline uint32_t radeon_div(uint64_t n, uint32_t d) 1091 { 1092 uint64_t mod; 1093 1094 n += d / 2; 1095 1096 mod = do_div(n, d); 1097 return n; 1098 } 1099 1100 void radeon_compute_pll_legacy(struct radeon_pll *pll, 1101 uint64_t freq, 1102 uint32_t *dot_clock_p, 1103 uint32_t *fb_div_p, 1104 uint32_t *frac_fb_div_p, 1105 uint32_t *ref_div_p, 1106 uint32_t *post_div_p) 1107 { 1108 uint32_t min_ref_div = pll->min_ref_div; 1109 uint32_t max_ref_div = pll->max_ref_div; 1110 uint32_t min_post_div = pll->min_post_div; 1111 uint32_t max_post_div = pll->max_post_div; 1112 uint32_t min_fractional_feed_div = 0; 1113 uint32_t max_fractional_feed_div = 0; 1114 uint32_t best_vco = pll->best_vco; 1115 uint32_t best_post_div = 1; 1116 uint32_t best_ref_div = 1; 1117 uint32_t best_feedback_div = 1; 1118 uint32_t best_frac_feedback_div = 0; 1119 uint32_t best_freq = -1; 1120 uint32_t best_error = 0xffffffff; 1121 uint32_t best_vco_diff = 1; 1122 uint32_t post_div; 1123 u32 pll_out_min, pll_out_max; 1124 1125 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 1126 freq = freq * 1000; 1127 1128 if (pll->flags & RADEON_PLL_IS_LCD) { 1129 pll_out_min = pll->lcd_pll_out_min; 1130 pll_out_max = pll->lcd_pll_out_max; 1131 } else { 1132 pll_out_min = pll->pll_out_min; 1133 pll_out_max = pll->pll_out_max; 1134 } 1135 1136 if (pll_out_min > 64800) 1137 pll_out_min = 64800; 1138 1139 if (pll->flags & RADEON_PLL_USE_REF_DIV) 1140 min_ref_div = max_ref_div = pll->reference_div; 1141 else { 1142 while (min_ref_div < max_ref_div-1) { 1143 uint32_t mid = (min_ref_div + max_ref_div) / 2; 1144 uint32_t pll_in = pll->reference_freq / mid; 1145 if (pll_in < pll->pll_in_min) 1146 max_ref_div = mid; 1147 else if (pll_in > pll->pll_in_max) 1148 min_ref_div = mid; 1149 else 1150 break; 1151 } 1152 } 1153 1154 if (pll->flags & RADEON_PLL_USE_POST_DIV) 1155 min_post_div = max_post_div = pll->post_div; 1156 1157 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 1158 min_fractional_feed_div = pll->min_frac_feedback_div; 1159 max_fractional_feed_div = pll->max_frac_feedback_div; 1160 } 1161 1162 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { 1163 uint32_t ref_div; 1164 1165 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 1166 continue; 1167 1168 /* legacy radeons only have a few post_divs */ 1169 if (pll->flags & RADEON_PLL_LEGACY) { 1170 if ((post_div == 5) || 1171 (post_div == 7) || 1172 (post_div == 9) || 1173 (post_div == 10) || 1174 (post_div == 11) || 1175 (post_div == 13) || 1176 (post_div == 14) || 1177 (post_div == 15)) 1178 continue; 1179 } 1180 1181 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { 1182 uint32_t feedback_div, current_freq = 0, error, vco_diff; 1183 uint32_t pll_in = pll->reference_freq / ref_div; 1184 uint32_t min_feed_div = pll->min_feedback_div; 1185 uint32_t max_feed_div = pll->max_feedback_div + 1; 1186 1187 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) 1188 continue; 1189 1190 while (min_feed_div < max_feed_div) { 1191 uint32_t vco; 1192 uint32_t min_frac_feed_div = min_fractional_feed_div; 1193 uint32_t max_frac_feed_div = max_fractional_feed_div + 1; 1194 uint32_t frac_feedback_div; 1195 uint64_t tmp; 1196 1197 feedback_div = (min_feed_div + max_feed_div) / 2; 1198 1199 tmp = (uint64_t)pll->reference_freq * feedback_div; 1200 vco = radeon_div(tmp, ref_div); 1201 1202 if (vco < pll_out_min) { 1203 min_feed_div = feedback_div + 1; 1204 continue; 1205 } else if (vco > pll_out_max) { 1206 max_feed_div = feedback_div; 1207 continue; 1208 } 1209 1210 while (min_frac_feed_div < max_frac_feed_div) { 1211 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; 1212 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; 1213 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 1214 current_freq = radeon_div(tmp, ref_div * post_div); 1215 1216 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 1217 if (freq < current_freq) 1218 error = 0xffffffff; 1219 else 1220 error = freq - current_freq; 1221 } else 1222 error = abs(current_freq - freq); 1223 vco_diff = abs(vco - best_vco); 1224 1225 if ((best_vco == 0 && error < best_error) || 1226 (best_vco != 0 && 1227 ((best_error > 100 && error < best_error - 100) || 1228 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { 1229 best_post_div = post_div; 1230 best_ref_div = ref_div; 1231 best_feedback_div = feedback_div; 1232 best_frac_feedback_div = frac_feedback_div; 1233 best_freq = current_freq; 1234 best_error = error; 1235 best_vco_diff = vco_diff; 1236 } else if (current_freq == freq) { 1237 if (best_freq == -1) { 1238 best_post_div = post_div; 1239 best_ref_div = ref_div; 1240 best_feedback_div = feedback_div; 1241 best_frac_feedback_div = frac_feedback_div; 1242 best_freq = current_freq; 1243 best_error = error; 1244 best_vco_diff = vco_diff; 1245 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 1246 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 1247 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 1248 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 1249 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 1250 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 1251 best_post_div = post_div; 1252 best_ref_div = ref_div; 1253 best_feedback_div = feedback_div; 1254 best_frac_feedback_div = frac_feedback_div; 1255 best_freq = current_freq; 1256 best_error = error; 1257 best_vco_diff = vco_diff; 1258 } 1259 } 1260 if (current_freq < freq) 1261 min_frac_feed_div = frac_feedback_div + 1; 1262 else 1263 max_frac_feed_div = frac_feedback_div; 1264 } 1265 if (current_freq < freq) 1266 min_feed_div = feedback_div + 1; 1267 else 1268 max_feed_div = feedback_div; 1269 } 1270 } 1271 } 1272 1273 *dot_clock_p = best_freq / 10000; 1274 *fb_div_p = best_feedback_div; 1275 *frac_fb_div_p = best_frac_feedback_div; 1276 *ref_div_p = best_ref_div; 1277 *post_div_p = best_post_div; 1278 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 1279 (long long)freq, 1280 best_freq / 1000, best_feedback_div, best_frac_feedback_div, 1281 best_ref_div, best_post_div); 1282 1283 } 1284 1285 static const struct drm_framebuffer_funcs radeon_fb_funcs = { 1286 .destroy = drm_gem_fb_destroy, 1287 .create_handle = drm_gem_fb_create_handle, 1288 }; 1289 1290 int 1291 radeon_framebuffer_init(struct drm_device *dev, 1292 struct drm_framebuffer *fb, 1293 const struct drm_mode_fb_cmd2 *mode_cmd, 1294 struct drm_gem_object *obj) 1295 { 1296 int ret; 1297 fb->obj[0] = obj; 1298 drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); 1299 ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs); 1300 if (ret) { 1301 fb->obj[0] = NULL; 1302 return ret; 1303 } 1304 return 0; 1305 } 1306 1307 static struct drm_framebuffer * 1308 radeon_user_framebuffer_create(struct drm_device *dev, 1309 struct drm_file *file_priv, 1310 const struct drm_mode_fb_cmd2 *mode_cmd) 1311 { 1312 struct drm_gem_object *obj; 1313 struct drm_framebuffer *fb; 1314 int ret; 1315 1316 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1317 if (obj == NULL) { 1318 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 1319 "can't create framebuffer\n", mode_cmd->handles[0]); 1320 return ERR_PTR(-ENOENT); 1321 } 1322 1323 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1324 if (obj->import_attach) { 1325 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 1326 return ERR_PTR(-EINVAL); 1327 } 1328 1329 fb = kzalloc(sizeof(*fb), GFP_KERNEL); 1330 if (fb == NULL) { 1331 drm_gem_object_put_unlocked(obj); 1332 return ERR_PTR(-ENOMEM); 1333 } 1334 1335 ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj); 1336 if (ret) { 1337 kfree(fb); 1338 drm_gem_object_put_unlocked(obj); 1339 return ERR_PTR(ret); 1340 } 1341 1342 return fb; 1343 } 1344 1345 static const struct drm_mode_config_funcs radeon_mode_funcs = { 1346 .fb_create = radeon_user_framebuffer_create, 1347 .output_poll_changed = drm_fb_helper_output_poll_changed, 1348 }; 1349 1350 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = 1351 { { 0, "driver" }, 1352 { 1, "bios" }, 1353 }; 1354 1355 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] = 1356 { { TV_STD_NTSC, "ntsc" }, 1357 { TV_STD_PAL, "pal" }, 1358 { TV_STD_PAL_M, "pal-m" }, 1359 { TV_STD_PAL_60, "pal-60" }, 1360 { TV_STD_NTSC_J, "ntsc-j" }, 1361 { TV_STD_SCART_PAL, "scart-pal" }, 1362 { TV_STD_PAL_CN, "pal-cn" }, 1363 { TV_STD_SECAM, "secam" }, 1364 }; 1365 1366 static const struct drm_prop_enum_list radeon_underscan_enum_list[] = 1367 { { UNDERSCAN_OFF, "off" }, 1368 { UNDERSCAN_ON, "on" }, 1369 { UNDERSCAN_AUTO, "auto" }, 1370 }; 1371 1372 static const struct drm_prop_enum_list radeon_audio_enum_list[] = 1373 { { RADEON_AUDIO_DISABLE, "off" }, 1374 { RADEON_AUDIO_ENABLE, "on" }, 1375 { RADEON_AUDIO_AUTO, "auto" }, 1376 }; 1377 1378 /* XXX support different dither options? spatial, temporal, both, etc. */ 1379 static const struct drm_prop_enum_list radeon_dither_enum_list[] = 1380 { { RADEON_FMT_DITHER_DISABLE, "off" }, 1381 { RADEON_FMT_DITHER_ENABLE, "on" }, 1382 }; 1383 1384 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] = 1385 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, 1386 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, 1387 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, 1388 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, 1389 }; 1390 1391 static int radeon_modeset_create_props(struct radeon_device *rdev) 1392 { 1393 int sz; 1394 1395 if (rdev->is_atom_bios) { 1396 rdev->mode_info.coherent_mode_property = 1397 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); 1398 if (!rdev->mode_info.coherent_mode_property) 1399 return -ENOMEM; 1400 } 1401 1402 if (!ASIC_IS_AVIVO(rdev)) { 1403 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); 1404 rdev->mode_info.tmds_pll_property = 1405 drm_property_create_enum(rdev->ddev, 0, 1406 "tmds_pll", 1407 radeon_tmds_pll_enum_list, sz); 1408 } 1409 1410 rdev->mode_info.load_detect_property = 1411 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); 1412 if (!rdev->mode_info.load_detect_property) 1413 return -ENOMEM; 1414 1415 drm_mode_create_scaling_mode_property(rdev->ddev); 1416 1417 sz = ARRAY_SIZE(radeon_tv_std_enum_list); 1418 rdev->mode_info.tv_std_property = 1419 drm_property_create_enum(rdev->ddev, 0, 1420 "tv standard", 1421 radeon_tv_std_enum_list, sz); 1422 1423 sz = ARRAY_SIZE(radeon_underscan_enum_list); 1424 rdev->mode_info.underscan_property = 1425 drm_property_create_enum(rdev->ddev, 0, 1426 "underscan", 1427 radeon_underscan_enum_list, sz); 1428 1429 rdev->mode_info.underscan_hborder_property = 1430 drm_property_create_range(rdev->ddev, 0, 1431 "underscan hborder", 0, 128); 1432 if (!rdev->mode_info.underscan_hborder_property) 1433 return -ENOMEM; 1434 1435 rdev->mode_info.underscan_vborder_property = 1436 drm_property_create_range(rdev->ddev, 0, 1437 "underscan vborder", 0, 128); 1438 if (!rdev->mode_info.underscan_vborder_property) 1439 return -ENOMEM; 1440 1441 sz = ARRAY_SIZE(radeon_audio_enum_list); 1442 rdev->mode_info.audio_property = 1443 drm_property_create_enum(rdev->ddev, 0, 1444 "audio", 1445 radeon_audio_enum_list, sz); 1446 1447 sz = ARRAY_SIZE(radeon_dither_enum_list); 1448 rdev->mode_info.dither_property = 1449 drm_property_create_enum(rdev->ddev, 0, 1450 "dither", 1451 radeon_dither_enum_list, sz); 1452 1453 sz = ARRAY_SIZE(radeon_output_csc_enum_list); 1454 rdev->mode_info.output_csc_property = 1455 drm_property_create_enum(rdev->ddev, 0, 1456 "output_csc", 1457 radeon_output_csc_enum_list, sz); 1458 1459 return 0; 1460 } 1461 1462 void radeon_update_display_priority(struct radeon_device *rdev) 1463 { 1464 /* adjustment options for the display watermarks */ 1465 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { 1466 /* set display priority to high for r3xx, rv515 chips 1467 * this avoids flickering due to underflow to the 1468 * display controllers during heavy acceleration. 1469 * Don't force high on rs4xx igp chips as it seems to 1470 * affect the sound card. See kernel bug 15982. 1471 */ 1472 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && 1473 !(rdev->flags & RADEON_IS_IGP)) 1474 rdev->disp_priority = 2; 1475 else 1476 rdev->disp_priority = 0; 1477 } else 1478 rdev->disp_priority = radeon_disp_priority; 1479 1480 } 1481 1482 /* 1483 * Allocate hdmi structs and determine register offsets 1484 */ 1485 static void radeon_afmt_init(struct radeon_device *rdev) 1486 { 1487 int i; 1488 1489 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) 1490 rdev->mode_info.afmt[i] = NULL; 1491 1492 if (ASIC_IS_NODCE(rdev)) { 1493 /* nothing to do */ 1494 } else if (ASIC_IS_DCE4(rdev)) { 1495 static uint32_t eg_offsets[] = { 1496 EVERGREEN_CRTC0_REGISTER_OFFSET, 1497 EVERGREEN_CRTC1_REGISTER_OFFSET, 1498 EVERGREEN_CRTC2_REGISTER_OFFSET, 1499 EVERGREEN_CRTC3_REGISTER_OFFSET, 1500 EVERGREEN_CRTC4_REGISTER_OFFSET, 1501 EVERGREEN_CRTC5_REGISTER_OFFSET, 1502 0x13830 - 0x7030, 1503 }; 1504 int num_afmt; 1505 1506 /* DCE8 has 7 audio blocks tied to DIG encoders */ 1507 /* DCE6 has 6 audio blocks tied to DIG encoders */ 1508 /* DCE4/5 has 6 audio blocks tied to DIG encoders */ 1509 /* DCE4.1 has 2 audio blocks tied to DIG encoders */ 1510 if (ASIC_IS_DCE8(rdev)) 1511 num_afmt = 7; 1512 else if (ASIC_IS_DCE6(rdev)) 1513 num_afmt = 6; 1514 else if (ASIC_IS_DCE5(rdev)) 1515 num_afmt = 6; 1516 else if (ASIC_IS_DCE41(rdev)) 1517 num_afmt = 2; 1518 else /* DCE4 */ 1519 num_afmt = 6; 1520 1521 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); 1522 for (i = 0; i < num_afmt; i++) { 1523 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1524 if (rdev->mode_info.afmt[i]) { 1525 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; 1526 rdev->mode_info.afmt[i]->id = i; 1527 } 1528 } 1529 } else if (ASIC_IS_DCE3(rdev)) { 1530 /* DCE3.x has 2 audio blocks tied to DIG encoders */ 1531 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1532 if (rdev->mode_info.afmt[0]) { 1533 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; 1534 rdev->mode_info.afmt[0]->id = 0; 1535 } 1536 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1537 if (rdev->mode_info.afmt[1]) { 1538 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; 1539 rdev->mode_info.afmt[1]->id = 1; 1540 } 1541 } else if (ASIC_IS_DCE2(rdev)) { 1542 /* DCE2 has at least 1 routable audio block */ 1543 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1544 if (rdev->mode_info.afmt[0]) { 1545 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; 1546 rdev->mode_info.afmt[0]->id = 0; 1547 } 1548 /* r6xx has 2 routable audio blocks */ 1549 if (rdev->family >= CHIP_R600) { 1550 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); 1551 if (rdev->mode_info.afmt[1]) { 1552 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; 1553 rdev->mode_info.afmt[1]->id = 1; 1554 } 1555 } 1556 } 1557 } 1558 1559 static void radeon_afmt_fini(struct radeon_device *rdev) 1560 { 1561 int i; 1562 1563 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { 1564 kfree(rdev->mode_info.afmt[i]); 1565 rdev->mode_info.afmt[i] = NULL; 1566 } 1567 } 1568 1569 int radeon_modeset_init(struct radeon_device *rdev) 1570 { 1571 int i; 1572 int ret; 1573 1574 drm_mode_config_init(rdev->ddev); 1575 rdev->mode_info.mode_config_initialized = true; 1576 1577 rdev->ddev->mode_config.funcs = &radeon_mode_funcs; 1578 1579 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) 1580 rdev->ddev->mode_config.async_page_flip = true; 1581 1582 if (ASIC_IS_DCE5(rdev)) { 1583 rdev->ddev->mode_config.max_width = 16384; 1584 rdev->ddev->mode_config.max_height = 16384; 1585 } else if (ASIC_IS_AVIVO(rdev)) { 1586 rdev->ddev->mode_config.max_width = 8192; 1587 rdev->ddev->mode_config.max_height = 8192; 1588 } else { 1589 rdev->ddev->mode_config.max_width = 4096; 1590 rdev->ddev->mode_config.max_height = 4096; 1591 } 1592 1593 rdev->ddev->mode_config.preferred_depth = 24; 1594 rdev->ddev->mode_config.prefer_shadow = 1; 1595 1596 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; 1597 1598 ret = radeon_modeset_create_props(rdev); 1599 if (ret) { 1600 return ret; 1601 } 1602 1603 /* init i2c buses */ 1604 radeon_i2c_init(rdev); 1605 1606 /* check combios for a valid hardcoded EDID - Sun servers */ 1607 if (!rdev->is_atom_bios) { 1608 /* check for hardcoded EDID in BIOS */ 1609 radeon_combios_check_hardcoded_edid(rdev); 1610 } 1611 1612 /* allocate crtcs */ 1613 for (i = 0; i < rdev->num_crtc; i++) { 1614 radeon_crtc_init(rdev->ddev, i); 1615 } 1616 1617 /* okay we should have all the bios connectors */ 1618 ret = radeon_setup_enc_conn(rdev->ddev); 1619 if (!ret) { 1620 return ret; 1621 } 1622 1623 /* init dig PHYs, disp eng pll */ 1624 if (rdev->is_atom_bios) { 1625 radeon_atom_encoder_init(rdev); 1626 radeon_atom_disp_eng_pll_init(rdev); 1627 } 1628 1629 /* initialize hpd */ 1630 radeon_hpd_init(rdev); 1631 1632 /* setup afmt */ 1633 radeon_afmt_init(rdev); 1634 1635 radeon_fbdev_init(rdev); 1636 drm_kms_helper_poll_init(rdev->ddev); 1637 1638 /* do pm late init */ 1639 ret = radeon_pm_late_init(rdev); 1640 1641 return 0; 1642 } 1643 1644 void radeon_modeset_fini(struct radeon_device *rdev) 1645 { 1646 if (rdev->mode_info.mode_config_initialized) { 1647 drm_kms_helper_poll_fini(rdev->ddev); 1648 radeon_hpd_fini(rdev); 1649 drm_crtc_force_disable_all(rdev->ddev); 1650 radeon_fbdev_fini(rdev); 1651 radeon_afmt_fini(rdev); 1652 drm_mode_config_cleanup(rdev->ddev); 1653 rdev->mode_info.mode_config_initialized = false; 1654 } 1655 1656 kfree(rdev->mode_info.bios_hardcoded_edid); 1657 1658 /* free i2c buses */ 1659 radeon_i2c_fini(rdev); 1660 } 1661 1662 static bool is_hdtv_mode(const struct drm_display_mode *mode) 1663 { 1664 /* try and guess if this is a tv or a monitor */ 1665 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1666 (mode->vdisplay == 576) || /* 576p */ 1667 (mode->vdisplay == 720) || /* 720p */ 1668 (mode->vdisplay == 1080)) /* 1080p */ 1669 return true; 1670 else 1671 return false; 1672 } 1673 1674 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1675 const struct drm_display_mode *mode, 1676 struct drm_display_mode *adjusted_mode) 1677 { 1678 struct drm_device *dev = crtc->dev; 1679 struct radeon_device *rdev = dev->dev_private; 1680 struct drm_encoder *encoder; 1681 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1682 struct radeon_encoder *radeon_encoder; 1683 struct drm_connector *connector; 1684 struct radeon_connector *radeon_connector; 1685 bool first = true; 1686 u32 src_v = 1, dst_v = 1; 1687 u32 src_h = 1, dst_h = 1; 1688 1689 radeon_crtc->h_border = 0; 1690 radeon_crtc->v_border = 0; 1691 1692 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1693 if (encoder->crtc != crtc) 1694 continue; 1695 radeon_encoder = to_radeon_encoder(encoder); 1696 connector = radeon_get_connector_for_encoder(encoder); 1697 radeon_connector = to_radeon_connector(connector); 1698 1699 if (first) { 1700 /* set scaling */ 1701 if (radeon_encoder->rmx_type == RMX_OFF) 1702 radeon_crtc->rmx_type = RMX_OFF; 1703 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || 1704 mode->vdisplay < radeon_encoder->native_mode.vdisplay) 1705 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 1706 else 1707 radeon_crtc->rmx_type = RMX_OFF; 1708 /* copy native mode */ 1709 memcpy(&radeon_crtc->native_mode, 1710 &radeon_encoder->native_mode, 1711 sizeof(struct drm_display_mode)); 1712 src_v = crtc->mode.vdisplay; 1713 dst_v = radeon_crtc->native_mode.vdisplay; 1714 src_h = crtc->mode.hdisplay; 1715 dst_h = radeon_crtc->native_mode.hdisplay; 1716 1717 /* fix up for overscan on hdmi */ 1718 if (ASIC_IS_AVIVO(rdev) && 1719 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1720 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || 1721 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && 1722 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && 1723 is_hdtv_mode(mode)))) { 1724 if (radeon_encoder->underscan_hborder != 0) 1725 radeon_crtc->h_border = radeon_encoder->underscan_hborder; 1726 else 1727 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; 1728 if (radeon_encoder->underscan_vborder != 0) 1729 radeon_crtc->v_border = radeon_encoder->underscan_vborder; 1730 else 1731 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; 1732 radeon_crtc->rmx_type = RMX_FULL; 1733 src_v = crtc->mode.vdisplay; 1734 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); 1735 src_h = crtc->mode.hdisplay; 1736 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); 1737 } 1738 first = false; 1739 } else { 1740 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 1741 /* WARNING: Right now this can't happen but 1742 * in the future we need to check that scaling 1743 * are consistent across different encoder 1744 * (ie all encoder can work with the same 1745 * scaling). 1746 */ 1747 DRM_ERROR("Scaling not consistent across encoder.\n"); 1748 return false; 1749 } 1750 } 1751 } 1752 if (radeon_crtc->rmx_type != RMX_OFF) { 1753 fixed20_12 a, b; 1754 a.full = dfixed_const(src_v); 1755 b.full = dfixed_const(dst_v); 1756 radeon_crtc->vsc.full = dfixed_div(a, b); 1757 a.full = dfixed_const(src_h); 1758 b.full = dfixed_const(dst_h); 1759 radeon_crtc->hsc.full = dfixed_div(a, b); 1760 } else { 1761 radeon_crtc->vsc.full = dfixed_const(1); 1762 radeon_crtc->hsc.full = dfixed_const(1); 1763 } 1764 return true; 1765 } 1766 1767 /* 1768 * Retrieve current video scanout position of crtc on a given gpu, and 1769 * an optional accurate timestamp of when query happened. 1770 * 1771 * \param dev Device to query. 1772 * \param crtc Crtc to query. 1773 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1774 * For driver internal use only also supports these flags: 1775 * 1776 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1777 * of a fudged earlier start of vblank. 1778 * 1779 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1780 * fudged earlier start of vblank in *vpos and the distance 1781 * to true start of vblank in *hpos. 1782 * 1783 * \param *vpos Location where vertical scanout position should be stored. 1784 * \param *hpos Location where horizontal scanout position should go. 1785 * \param *stime Target location for timestamp taken immediately before 1786 * scanout position query. Can be NULL to skip timestamp. 1787 * \param *etime Target location for timestamp taken immediately after 1788 * scanout position query. Can be NULL to skip timestamp. 1789 * 1790 * Returns vpos as a positive number while in active scanout area. 1791 * Returns vpos as a negative number inside vblank, counting the number 1792 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1793 * until start of active scanout / end of vblank." 1794 * 1795 * \return Flags, or'ed together as follows: 1796 * 1797 * DRM_SCANOUTPOS_VALID = Query successful. 1798 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1799 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1800 * this flag means that returned position may be offset by a constant but 1801 * unknown small number of scanlines wrt. real scanout position. 1802 * 1803 */ 1804 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 1805 unsigned int flags, int *vpos, int *hpos, 1806 ktime_t *stime, ktime_t *etime, 1807 const struct drm_display_mode *mode) 1808 { 1809 u32 stat_crtc = 0, vbl = 0, position = 0; 1810 int vbl_start, vbl_end, vtotal, ret = 0; 1811 bool in_vbl = true; 1812 1813 struct radeon_device *rdev = dev->dev_private; 1814 1815 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1816 1817 /* Get optional system timestamp before query. */ 1818 if (stime) 1819 *stime = ktime_get(); 1820 1821 if (ASIC_IS_DCE4(rdev)) { 1822 if (pipe == 0) { 1823 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1824 EVERGREEN_CRTC0_REGISTER_OFFSET); 1825 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1826 EVERGREEN_CRTC0_REGISTER_OFFSET); 1827 ret |= DRM_SCANOUTPOS_VALID; 1828 } 1829 if (pipe == 1) { 1830 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1831 EVERGREEN_CRTC1_REGISTER_OFFSET); 1832 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1833 EVERGREEN_CRTC1_REGISTER_OFFSET); 1834 ret |= DRM_SCANOUTPOS_VALID; 1835 } 1836 if (pipe == 2) { 1837 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1838 EVERGREEN_CRTC2_REGISTER_OFFSET); 1839 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1840 EVERGREEN_CRTC2_REGISTER_OFFSET); 1841 ret |= DRM_SCANOUTPOS_VALID; 1842 } 1843 if (pipe == 3) { 1844 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1845 EVERGREEN_CRTC3_REGISTER_OFFSET); 1846 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1847 EVERGREEN_CRTC3_REGISTER_OFFSET); 1848 ret |= DRM_SCANOUTPOS_VALID; 1849 } 1850 if (pipe == 4) { 1851 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1852 EVERGREEN_CRTC4_REGISTER_OFFSET); 1853 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1854 EVERGREEN_CRTC4_REGISTER_OFFSET); 1855 ret |= DRM_SCANOUTPOS_VALID; 1856 } 1857 if (pipe == 5) { 1858 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + 1859 EVERGREEN_CRTC5_REGISTER_OFFSET); 1860 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + 1861 EVERGREEN_CRTC5_REGISTER_OFFSET); 1862 ret |= DRM_SCANOUTPOS_VALID; 1863 } 1864 } else if (ASIC_IS_AVIVO(rdev)) { 1865 if (pipe == 0) { 1866 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); 1867 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); 1868 ret |= DRM_SCANOUTPOS_VALID; 1869 } 1870 if (pipe == 1) { 1871 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); 1872 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); 1873 ret |= DRM_SCANOUTPOS_VALID; 1874 } 1875 } else { 1876 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ 1877 if (pipe == 0) { 1878 /* Assume vbl_end == 0, get vbl_start from 1879 * upper 16 bits. 1880 */ 1881 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & 1882 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1883 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ 1884 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1885 stat_crtc = RREG32(RADEON_CRTC_STATUS); 1886 if (!(stat_crtc & 1)) 1887 in_vbl = false; 1888 1889 ret |= DRM_SCANOUTPOS_VALID; 1890 } 1891 if (pipe == 1) { 1892 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & 1893 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; 1894 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 1895 stat_crtc = RREG32(RADEON_CRTC2_STATUS); 1896 if (!(stat_crtc & 1)) 1897 in_vbl = false; 1898 1899 ret |= DRM_SCANOUTPOS_VALID; 1900 } 1901 } 1902 1903 /* Get optional system timestamp after query. */ 1904 if (etime) 1905 *etime = ktime_get(); 1906 1907 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1908 1909 /* Decode into vertical and horizontal scanout position. */ 1910 *vpos = position & 0x1fff; 1911 *hpos = (position >> 16) & 0x1fff; 1912 1913 /* Valid vblank area boundaries from gpu retrieved? */ 1914 if (vbl > 0) { 1915 /* Yes: Decode. */ 1916 ret |= DRM_SCANOUTPOS_ACCURATE; 1917 vbl_start = vbl & 0x1fff; 1918 vbl_end = (vbl >> 16) & 0x1fff; 1919 } 1920 else { 1921 /* No: Fake something reasonable which gives at least ok results. */ 1922 vbl_start = mode->crtc_vdisplay; 1923 vbl_end = 0; 1924 } 1925 1926 /* Called from driver internal vblank counter query code? */ 1927 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1928 /* Caller wants distance from real vbl_start in *hpos */ 1929 *hpos = *vpos - vbl_start; 1930 } 1931 1932 /* Fudge vblank to start a few scanlines earlier to handle the 1933 * problem that vblank irqs fire a few scanlines before start 1934 * of vblank. Some driver internal callers need the true vblank 1935 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1936 * 1937 * The cause of the "early" vblank irq is that the irq is triggered 1938 * by the line buffer logic when the line buffer read position enters 1939 * the vblank, whereas our crtc scanout position naturally lags the 1940 * line buffer read position. 1941 */ 1942 if (!(flags & USE_REAL_VBLANKSTART)) 1943 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1944 1945 /* Test scanout position against vblank region. */ 1946 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1947 in_vbl = false; 1948 1949 /* In vblank? */ 1950 if (in_vbl) 1951 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1952 1953 /* Called from driver internal vblank counter query code? */ 1954 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1955 /* Caller wants distance from fudged earlier vbl_start */ 1956 *vpos -= vbl_start; 1957 return ret; 1958 } 1959 1960 /* Check if inside vblank area and apply corrective offsets: 1961 * vpos will then be >=0 in video scanout area, but negative 1962 * within vblank area, counting down the number of lines until 1963 * start of scanout. 1964 */ 1965 1966 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1967 if (in_vbl && (*vpos >= vbl_start)) { 1968 vtotal = mode->crtc_vtotal; 1969 *vpos = *vpos - vtotal; 1970 } 1971 1972 /* Correct for shifted end of vbl at vbl_end. */ 1973 *vpos = *vpos - vbl_end; 1974 1975 return ret; 1976 } 1977