1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include <linux/efi.h> 36 #include "radeon_reg.h" 37 #include "radeon.h" 38 #include "atom.h" 39 40 static const char radeon_family_name[][16] = { 41 "R100", 42 "RV100", 43 "RS100", 44 "RV200", 45 "RS200", 46 "R200", 47 "RV250", 48 "RS300", 49 "RV280", 50 "R300", 51 "R350", 52 "RV350", 53 "RV380", 54 "R420", 55 "R423", 56 "RV410", 57 "RS400", 58 "RS480", 59 "RS600", 60 "RS690", 61 "RS740", 62 "RV515", 63 "R520", 64 "RV530", 65 "RV560", 66 "RV570", 67 "R580", 68 "R600", 69 "RV610", 70 "RV630", 71 "RV670", 72 "RV620", 73 "RV635", 74 "RS780", 75 "RS880", 76 "RV770", 77 "RV730", 78 "RV710", 79 "RV740", 80 "CEDAR", 81 "REDWOOD", 82 "JUNIPER", 83 "CYPRESS", 84 "HEMLOCK", 85 "PALM", 86 "SUMO", 87 "SUMO2", 88 "BARTS", 89 "TURKS", 90 "CAICOS", 91 "CAYMAN", 92 "ARUBA", 93 "TAHITI", 94 "PITCAIRN", 95 "VERDE", 96 "OLAND", 97 "LAST", 98 }; 99 100 /** 101 * radeon_program_register_sequence - program an array of registers. 102 * 103 * @rdev: radeon_device pointer 104 * @registers: pointer to the register array 105 * @array_size: size of the register array 106 * 107 * Programs an array or registers with and and or masks. 108 * This is a helper for setting golden registers. 109 */ 110 void radeon_program_register_sequence(struct radeon_device *rdev, 111 const u32 *registers, 112 const u32 array_size) 113 { 114 u32 tmp, reg, and_mask, or_mask; 115 int i; 116 117 if (array_size % 3) 118 return; 119 120 for (i = 0; i < array_size; i +=3) { 121 reg = registers[i + 0]; 122 and_mask = registers[i + 1]; 123 or_mask = registers[i + 2]; 124 125 if (and_mask == 0xffffffff) { 126 tmp = or_mask; 127 } else { 128 tmp = RREG32(reg); 129 tmp &= ~and_mask; 130 tmp |= or_mask; 131 } 132 WREG32(reg, tmp); 133 } 134 } 135 136 /** 137 * radeon_surface_init - Clear GPU surface registers. 138 * 139 * @rdev: radeon_device pointer 140 * 141 * Clear GPU surface registers (r1xx-r5xx). 142 */ 143 void radeon_surface_init(struct radeon_device *rdev) 144 { 145 /* FIXME: check this out */ 146 if (rdev->family < CHIP_R600) { 147 int i; 148 149 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 150 if (rdev->surface_regs[i].bo) 151 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 152 else 153 radeon_clear_surface_reg(rdev, i); 154 } 155 /* enable surfaces */ 156 WREG32(RADEON_SURFACE_CNTL, 0); 157 } 158 } 159 160 /* 161 * GPU scratch registers helpers function. 162 */ 163 /** 164 * radeon_scratch_init - Init scratch register driver information. 165 * 166 * @rdev: radeon_device pointer 167 * 168 * Init CP scratch register driver information (r1xx-r5xx) 169 */ 170 void radeon_scratch_init(struct radeon_device *rdev) 171 { 172 int i; 173 174 /* FIXME: check this out */ 175 if (rdev->family < CHIP_R300) { 176 rdev->scratch.num_reg = 5; 177 } else { 178 rdev->scratch.num_reg = 7; 179 } 180 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 181 for (i = 0; i < rdev->scratch.num_reg; i++) { 182 rdev->scratch.free[i] = true; 183 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 184 } 185 } 186 187 /** 188 * radeon_scratch_get - Allocate a scratch register 189 * 190 * @rdev: radeon_device pointer 191 * @reg: scratch register mmio offset 192 * 193 * Allocate a CP scratch register for use by the driver (all asics). 194 * Returns 0 on success or -EINVAL on failure. 195 */ 196 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 197 { 198 int i; 199 200 for (i = 0; i < rdev->scratch.num_reg; i++) { 201 if (rdev->scratch.free[i]) { 202 rdev->scratch.free[i] = false; 203 *reg = rdev->scratch.reg[i]; 204 return 0; 205 } 206 } 207 return -EINVAL; 208 } 209 210 /** 211 * radeon_scratch_free - Free a scratch register 212 * 213 * @rdev: radeon_device pointer 214 * @reg: scratch register mmio offset 215 * 216 * Free a CP scratch register allocated for use by the driver (all asics) 217 */ 218 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 219 { 220 int i; 221 222 for (i = 0; i < rdev->scratch.num_reg; i++) { 223 if (rdev->scratch.reg[i] == reg) { 224 rdev->scratch.free[i] = true; 225 return; 226 } 227 } 228 } 229 230 /* 231 * radeon_wb_*() 232 * Writeback is the the method by which the the GPU updates special pages 233 * in memory with the status of certain GPU events (fences, ring pointers, 234 * etc.). 235 */ 236 237 /** 238 * radeon_wb_disable - Disable Writeback 239 * 240 * @rdev: radeon_device pointer 241 * 242 * Disables Writeback (all asics). Used for suspend. 243 */ 244 void radeon_wb_disable(struct radeon_device *rdev) 245 { 246 int r; 247 248 if (rdev->wb.wb_obj) { 249 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 250 if (unlikely(r != 0)) 251 return; 252 radeon_bo_kunmap(rdev->wb.wb_obj); 253 radeon_bo_unpin(rdev->wb.wb_obj); 254 radeon_bo_unreserve(rdev->wb.wb_obj); 255 } 256 rdev->wb.enabled = false; 257 } 258 259 /** 260 * radeon_wb_fini - Disable Writeback and free memory 261 * 262 * @rdev: radeon_device pointer 263 * 264 * Disables Writeback and frees the Writeback memory (all asics). 265 * Used at driver shutdown. 266 */ 267 void radeon_wb_fini(struct radeon_device *rdev) 268 { 269 radeon_wb_disable(rdev); 270 if (rdev->wb.wb_obj) { 271 radeon_bo_unref(&rdev->wb.wb_obj); 272 rdev->wb.wb = NULL; 273 rdev->wb.wb_obj = NULL; 274 } 275 } 276 277 /** 278 * radeon_wb_init- Init Writeback driver info and allocate memory 279 * 280 * @rdev: radeon_device pointer 281 * 282 * Disables Writeback and frees the Writeback memory (all asics). 283 * Used at driver startup. 284 * Returns 0 on success or an -error on failure. 285 */ 286 int radeon_wb_init(struct radeon_device *rdev) 287 { 288 int r; 289 290 if (rdev->wb.wb_obj == NULL) { 291 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 292 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); 293 if (r) { 294 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 295 return r; 296 } 297 } 298 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 299 if (unlikely(r != 0)) { 300 radeon_wb_fini(rdev); 301 return r; 302 } 303 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 304 &rdev->wb.gpu_addr); 305 if (r) { 306 radeon_bo_unreserve(rdev->wb.wb_obj); 307 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 308 radeon_wb_fini(rdev); 309 return r; 310 } 311 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 312 radeon_bo_unreserve(rdev->wb.wb_obj); 313 if (r) { 314 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 315 radeon_wb_fini(rdev); 316 return r; 317 } 318 319 /* clear wb memory */ 320 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 321 /* disable event_write fences */ 322 rdev->wb.use_event = false; 323 /* disabled via module param */ 324 if (radeon_no_wb == 1) { 325 rdev->wb.enabled = false; 326 } else { 327 if (rdev->flags & RADEON_IS_AGP) { 328 /* often unreliable on AGP */ 329 rdev->wb.enabled = false; 330 } else if (rdev->family < CHIP_R300) { 331 /* often unreliable on pre-r300 */ 332 rdev->wb.enabled = false; 333 } else { 334 rdev->wb.enabled = true; 335 /* event_write fences are only available on r600+ */ 336 if (rdev->family >= CHIP_R600) { 337 rdev->wb.use_event = true; 338 } 339 } 340 } 341 /* always use writeback/events on NI, APUs */ 342 if (rdev->family >= CHIP_PALM) { 343 rdev->wb.enabled = true; 344 rdev->wb.use_event = true; 345 } 346 347 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 348 349 return 0; 350 } 351 352 /** 353 * radeon_vram_location - try to find VRAM location 354 * @rdev: radeon device structure holding all necessary informations 355 * @mc: memory controller structure holding memory informations 356 * @base: base address at which to put VRAM 357 * 358 * Function will place try to place VRAM at base address provided 359 * as parameter (which is so far either PCI aperture address or 360 * for IGP TOM base address). 361 * 362 * If there is not enough space to fit the unvisible VRAM in the 32bits 363 * address space then we limit the VRAM size to the aperture. 364 * 365 * If we are using AGP and if the AGP aperture doesn't allow us to have 366 * room for all the VRAM than we restrict the VRAM to the PCI aperture 367 * size and print a warning. 368 * 369 * This function will never fails, worst case are limiting VRAM. 370 * 371 * Note: GTT start, end, size should be initialized before calling this 372 * function on AGP platform. 373 * 374 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 375 * this shouldn't be a problem as we are using the PCI aperture as a reference. 376 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 377 * not IGP. 378 * 379 * Note: we use mc_vram_size as on some board we need to program the mc to 380 * cover the whole aperture even if VRAM size is inferior to aperture size 381 * Novell bug 204882 + along with lots of ubuntu ones 382 * 383 * Note: when limiting vram it's safe to overwritte real_vram_size because 384 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 385 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 386 * ones) 387 * 388 * Note: IGP TOM addr should be the same as the aperture addr, we don't 389 * explicitly check for that thought. 390 * 391 * FIXME: when reducing VRAM size align new size on power of 2. 392 */ 393 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 394 { 395 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 396 397 mc->vram_start = base; 398 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 399 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 400 mc->real_vram_size = mc->aper_size; 401 mc->mc_vram_size = mc->aper_size; 402 } 403 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 404 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 405 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 406 mc->real_vram_size = mc->aper_size; 407 mc->mc_vram_size = mc->aper_size; 408 } 409 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 410 if (limit && limit < mc->real_vram_size) 411 mc->real_vram_size = limit; 412 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 413 mc->mc_vram_size >> 20, mc->vram_start, 414 mc->vram_end, mc->real_vram_size >> 20); 415 } 416 417 /** 418 * radeon_gtt_location - try to find GTT location 419 * @rdev: radeon device structure holding all necessary informations 420 * @mc: memory controller structure holding memory informations 421 * 422 * Function will place try to place GTT before or after VRAM. 423 * 424 * If GTT size is bigger than space left then we ajust GTT size. 425 * Thus function will never fails. 426 * 427 * FIXME: when reducing GTT size align new size on power of 2. 428 */ 429 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 430 { 431 u64 size_af, size_bf; 432 433 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 434 size_bf = mc->vram_start & ~mc->gtt_base_align; 435 if (size_bf > size_af) { 436 if (mc->gtt_size > size_bf) { 437 dev_warn(rdev->dev, "limiting GTT\n"); 438 mc->gtt_size = size_bf; 439 } 440 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 441 } else { 442 if (mc->gtt_size > size_af) { 443 dev_warn(rdev->dev, "limiting GTT\n"); 444 mc->gtt_size = size_af; 445 } 446 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 447 } 448 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 449 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 450 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 451 } 452 453 /* 454 * GPU helpers function. 455 */ 456 /** 457 * radeon_card_posted - check if the hw has already been initialized 458 * 459 * @rdev: radeon_device pointer 460 * 461 * Check if the asic has been initialized (all asics). 462 * Used at driver startup. 463 * Returns true if initialized or false if not. 464 */ 465 bool radeon_card_posted(struct radeon_device *rdev) 466 { 467 uint32_t reg; 468 469 if (efi_enabled(EFI_BOOT) && 470 rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) 471 return false; 472 473 /* first check CRTCs */ 474 if (ASIC_IS_DCE41(rdev)) { 475 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 476 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 477 if (reg & EVERGREEN_CRTC_MASTER_EN) 478 return true; 479 } else if (ASIC_IS_DCE4(rdev)) { 480 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 481 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 482 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 483 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 484 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 485 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 486 if (reg & EVERGREEN_CRTC_MASTER_EN) 487 return true; 488 } else if (ASIC_IS_AVIVO(rdev)) { 489 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 490 RREG32(AVIVO_D2CRTC_CONTROL); 491 if (reg & AVIVO_CRTC_EN) { 492 return true; 493 } 494 } else { 495 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 496 RREG32(RADEON_CRTC2_GEN_CNTL); 497 if (reg & RADEON_CRTC_EN) { 498 return true; 499 } 500 } 501 502 /* then check MEM_SIZE, in case the crtcs are off */ 503 if (rdev->family >= CHIP_R600) 504 reg = RREG32(R600_CONFIG_MEMSIZE); 505 else 506 reg = RREG32(RADEON_CONFIG_MEMSIZE); 507 508 if (reg) 509 return true; 510 511 return false; 512 513 } 514 515 /** 516 * radeon_update_bandwidth_info - update display bandwidth params 517 * 518 * @rdev: radeon_device pointer 519 * 520 * Used when sclk/mclk are switched or display modes are set. 521 * params are used to calculate display watermarks (all asics) 522 */ 523 void radeon_update_bandwidth_info(struct radeon_device *rdev) 524 { 525 fixed20_12 a; 526 u32 sclk = rdev->pm.current_sclk; 527 u32 mclk = rdev->pm.current_mclk; 528 529 /* sclk/mclk in Mhz */ 530 a.full = dfixed_const(100); 531 rdev->pm.sclk.full = dfixed_const(sclk); 532 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 533 rdev->pm.mclk.full = dfixed_const(mclk); 534 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 535 536 if (rdev->flags & RADEON_IS_IGP) { 537 a.full = dfixed_const(16); 538 /* core_bandwidth = sclk(Mhz) * 16 */ 539 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 540 } 541 } 542 543 /** 544 * radeon_boot_test_post_card - check and possibly initialize the hw 545 * 546 * @rdev: radeon_device pointer 547 * 548 * Check if the asic is initialized and if not, attempt to initialize 549 * it (all asics). 550 * Returns true if initialized or false if not. 551 */ 552 bool radeon_boot_test_post_card(struct radeon_device *rdev) 553 { 554 if (radeon_card_posted(rdev)) 555 return true; 556 557 if (rdev->bios) { 558 DRM_INFO("GPU not posted. posting now...\n"); 559 if (rdev->is_atom_bios) 560 atom_asic_init(rdev->mode_info.atom_context); 561 else 562 radeon_combios_asic_init(rdev->ddev); 563 return true; 564 } else { 565 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 566 return false; 567 } 568 } 569 570 /** 571 * radeon_dummy_page_init - init dummy page used by the driver 572 * 573 * @rdev: radeon_device pointer 574 * 575 * Allocate the dummy page used by the driver (all asics). 576 * This dummy page is used by the driver as a filler for gart entries 577 * when pages are taken out of the GART 578 * Returns 0 on sucess, -ENOMEM on failure. 579 */ 580 int radeon_dummy_page_init(struct radeon_device *rdev) 581 { 582 if (rdev->dummy_page.page) 583 return 0; 584 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 585 if (rdev->dummy_page.page == NULL) 586 return -ENOMEM; 587 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 588 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 589 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 590 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 591 __free_page(rdev->dummy_page.page); 592 rdev->dummy_page.page = NULL; 593 return -ENOMEM; 594 } 595 return 0; 596 } 597 598 /** 599 * radeon_dummy_page_fini - free dummy page used by the driver 600 * 601 * @rdev: radeon_device pointer 602 * 603 * Frees the dummy page used by the driver (all asics). 604 */ 605 void radeon_dummy_page_fini(struct radeon_device *rdev) 606 { 607 if (rdev->dummy_page.page == NULL) 608 return; 609 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 610 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 611 __free_page(rdev->dummy_page.page); 612 rdev->dummy_page.page = NULL; 613 } 614 615 616 /* ATOM accessor methods */ 617 /* 618 * ATOM is an interpreted byte code stored in tables in the vbios. The 619 * driver registers callbacks to access registers and the interpreter 620 * in the driver parses the tables and executes then to program specific 621 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 622 * atombios.h, and atom.c 623 */ 624 625 /** 626 * cail_pll_read - read PLL register 627 * 628 * @info: atom card_info pointer 629 * @reg: PLL register offset 630 * 631 * Provides a PLL register accessor for the atom interpreter (r4xx+). 632 * Returns the value of the PLL register. 633 */ 634 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 635 { 636 struct radeon_device *rdev = info->dev->dev_private; 637 uint32_t r; 638 639 r = rdev->pll_rreg(rdev, reg); 640 return r; 641 } 642 643 /** 644 * cail_pll_write - write PLL register 645 * 646 * @info: atom card_info pointer 647 * @reg: PLL register offset 648 * @val: value to write to the pll register 649 * 650 * Provides a PLL register accessor for the atom interpreter (r4xx+). 651 */ 652 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 653 { 654 struct radeon_device *rdev = info->dev->dev_private; 655 656 rdev->pll_wreg(rdev, reg, val); 657 } 658 659 /** 660 * cail_mc_read - read MC (Memory Controller) register 661 * 662 * @info: atom card_info pointer 663 * @reg: MC register offset 664 * 665 * Provides an MC register accessor for the atom interpreter (r4xx+). 666 * Returns the value of the MC register. 667 */ 668 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 669 { 670 struct radeon_device *rdev = info->dev->dev_private; 671 uint32_t r; 672 673 r = rdev->mc_rreg(rdev, reg); 674 return r; 675 } 676 677 /** 678 * cail_mc_write - write MC (Memory Controller) register 679 * 680 * @info: atom card_info pointer 681 * @reg: MC register offset 682 * @val: value to write to the pll register 683 * 684 * Provides a MC register accessor for the atom interpreter (r4xx+). 685 */ 686 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 687 { 688 struct radeon_device *rdev = info->dev->dev_private; 689 690 rdev->mc_wreg(rdev, reg, val); 691 } 692 693 /** 694 * cail_reg_write - write MMIO register 695 * 696 * @info: atom card_info pointer 697 * @reg: MMIO register offset 698 * @val: value to write to the pll register 699 * 700 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 701 */ 702 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 703 { 704 struct radeon_device *rdev = info->dev->dev_private; 705 706 WREG32(reg*4, val); 707 } 708 709 /** 710 * cail_reg_read - read MMIO register 711 * 712 * @info: atom card_info pointer 713 * @reg: MMIO register offset 714 * 715 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 716 * Returns the value of the MMIO register. 717 */ 718 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 719 { 720 struct radeon_device *rdev = info->dev->dev_private; 721 uint32_t r; 722 723 r = RREG32(reg*4); 724 return r; 725 } 726 727 /** 728 * cail_ioreg_write - write IO register 729 * 730 * @info: atom card_info pointer 731 * @reg: IO register offset 732 * @val: value to write to the pll register 733 * 734 * Provides a IO register accessor for the atom interpreter (r4xx+). 735 */ 736 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 737 { 738 struct radeon_device *rdev = info->dev->dev_private; 739 740 WREG32_IO(reg*4, val); 741 } 742 743 /** 744 * cail_ioreg_read - read IO register 745 * 746 * @info: atom card_info pointer 747 * @reg: IO register offset 748 * 749 * Provides an IO register accessor for the atom interpreter (r4xx+). 750 * Returns the value of the IO register. 751 */ 752 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 753 { 754 struct radeon_device *rdev = info->dev->dev_private; 755 uint32_t r; 756 757 r = RREG32_IO(reg*4); 758 return r; 759 } 760 761 /** 762 * radeon_atombios_init - init the driver info and callbacks for atombios 763 * 764 * @rdev: radeon_device pointer 765 * 766 * Initializes the driver info and register access callbacks for the 767 * ATOM interpreter (r4xx+). 768 * Returns 0 on sucess, -ENOMEM on failure. 769 * Called at driver startup. 770 */ 771 int radeon_atombios_init(struct radeon_device *rdev) 772 { 773 struct card_info *atom_card_info = 774 kzalloc(sizeof(struct card_info), GFP_KERNEL); 775 776 if (!atom_card_info) 777 return -ENOMEM; 778 779 rdev->mode_info.atom_card_info = atom_card_info; 780 atom_card_info->dev = rdev->ddev; 781 atom_card_info->reg_read = cail_reg_read; 782 atom_card_info->reg_write = cail_reg_write; 783 /* needed for iio ops */ 784 if (rdev->rio_mem) { 785 atom_card_info->ioreg_read = cail_ioreg_read; 786 atom_card_info->ioreg_write = cail_ioreg_write; 787 } else { 788 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 789 atom_card_info->ioreg_read = cail_reg_read; 790 atom_card_info->ioreg_write = cail_reg_write; 791 } 792 atom_card_info->mc_read = cail_mc_read; 793 atom_card_info->mc_write = cail_mc_write; 794 atom_card_info->pll_read = cail_pll_read; 795 atom_card_info->pll_write = cail_pll_write; 796 797 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 798 if (!rdev->mode_info.atom_context) { 799 radeon_atombios_fini(rdev); 800 return -ENOMEM; 801 } 802 803 mutex_init(&rdev->mode_info.atom_context->mutex); 804 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 805 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 806 return 0; 807 } 808 809 /** 810 * radeon_atombios_fini - free the driver info and callbacks for atombios 811 * 812 * @rdev: radeon_device pointer 813 * 814 * Frees the driver info and register access callbacks for the ATOM 815 * interpreter (r4xx+). 816 * Called at driver shutdown. 817 */ 818 void radeon_atombios_fini(struct radeon_device *rdev) 819 { 820 if (rdev->mode_info.atom_context) { 821 kfree(rdev->mode_info.atom_context->scratch); 822 } 823 kfree(rdev->mode_info.atom_context); 824 rdev->mode_info.atom_context = NULL; 825 kfree(rdev->mode_info.atom_card_info); 826 rdev->mode_info.atom_card_info = NULL; 827 } 828 829 /* COMBIOS */ 830 /* 831 * COMBIOS is the bios format prior to ATOM. It provides 832 * command tables similar to ATOM, but doesn't have a unified 833 * parser. See radeon_combios.c 834 */ 835 836 /** 837 * radeon_combios_init - init the driver info for combios 838 * 839 * @rdev: radeon_device pointer 840 * 841 * Initializes the driver info for combios (r1xx-r3xx). 842 * Returns 0 on sucess. 843 * Called at driver startup. 844 */ 845 int radeon_combios_init(struct radeon_device *rdev) 846 { 847 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 848 return 0; 849 } 850 851 /** 852 * radeon_combios_fini - free the driver info for combios 853 * 854 * @rdev: radeon_device pointer 855 * 856 * Frees the driver info for combios (r1xx-r3xx). 857 * Called at driver shutdown. 858 */ 859 void radeon_combios_fini(struct radeon_device *rdev) 860 { 861 } 862 863 /* if we get transitioned to only one device, take VGA back */ 864 /** 865 * radeon_vga_set_decode - enable/disable vga decode 866 * 867 * @cookie: radeon_device pointer 868 * @state: enable/disable vga decode 869 * 870 * Enable/disable vga decode (all asics). 871 * Returns VGA resource flags. 872 */ 873 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 874 { 875 struct radeon_device *rdev = cookie; 876 radeon_vga_set_state(rdev, state); 877 if (state) 878 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 879 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 880 else 881 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 882 } 883 884 /** 885 * radeon_check_pot_argument - check that argument is a power of two 886 * 887 * @arg: value to check 888 * 889 * Validates that a certain argument is a power of two (all asics). 890 * Returns true if argument is valid. 891 */ 892 static bool radeon_check_pot_argument(int arg) 893 { 894 return (arg & (arg - 1)) == 0; 895 } 896 897 /** 898 * radeon_check_arguments - validate module params 899 * 900 * @rdev: radeon_device pointer 901 * 902 * Validates certain module parameters and updates 903 * the associated values used by the driver (all asics). 904 */ 905 static void radeon_check_arguments(struct radeon_device *rdev) 906 { 907 /* vramlimit must be a power of two */ 908 if (!radeon_check_pot_argument(radeon_vram_limit)) { 909 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 910 radeon_vram_limit); 911 radeon_vram_limit = 0; 912 } 913 914 /* gtt size must be power of two and greater or equal to 32M */ 915 if (radeon_gart_size < 32) { 916 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 917 radeon_gart_size); 918 radeon_gart_size = 512; 919 920 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 921 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 922 radeon_gart_size); 923 radeon_gart_size = 512; 924 } 925 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 926 927 /* AGP mode can only be -1, 1, 2, 4, 8 */ 928 switch (radeon_agpmode) { 929 case -1: 930 case 0: 931 case 1: 932 case 2: 933 case 4: 934 case 8: 935 break; 936 default: 937 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 938 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 939 radeon_agpmode = 0; 940 break; 941 } 942 } 943 944 /** 945 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is 946 * needed for waking up. 947 * 948 * @pdev: pci dev pointer 949 */ 950 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev) 951 { 952 953 /* 6600m in a macbook pro */ 954 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 955 pdev->subsystem_device == 0x00e2) { 956 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n"); 957 return true; 958 } 959 960 return false; 961 } 962 963 /** 964 * radeon_switcheroo_set_state - set switcheroo state 965 * 966 * @pdev: pci dev pointer 967 * @state: vga switcheroo state 968 * 969 * Callback for the switcheroo driver. Suspends or resumes the 970 * the asics before or after it is powered up using ACPI methods. 971 */ 972 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 973 { 974 struct drm_device *dev = pci_get_drvdata(pdev); 975 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 976 if (state == VGA_SWITCHEROO_ON) { 977 unsigned d3_delay = dev->pdev->d3_delay; 978 979 printk(KERN_INFO "radeon: switched on\n"); 980 /* don't suspend or resume card normally */ 981 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 982 983 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev)) 984 dev->pdev->d3_delay = 20; 985 986 radeon_resume_kms(dev); 987 988 dev->pdev->d3_delay = d3_delay; 989 990 dev->switch_power_state = DRM_SWITCH_POWER_ON; 991 drm_kms_helper_poll_enable(dev); 992 } else { 993 printk(KERN_INFO "radeon: switched off\n"); 994 drm_kms_helper_poll_disable(dev); 995 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 996 radeon_suspend_kms(dev, pmm); 997 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 998 } 999 } 1000 1001 /** 1002 * radeon_switcheroo_can_switch - see if switcheroo state can change 1003 * 1004 * @pdev: pci dev pointer 1005 * 1006 * Callback for the switcheroo driver. Check of the switcheroo 1007 * state can be changed. 1008 * Returns true if the state can be changed, false if not. 1009 */ 1010 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1011 { 1012 struct drm_device *dev = pci_get_drvdata(pdev); 1013 bool can_switch; 1014 1015 spin_lock(&dev->count_lock); 1016 can_switch = (dev->open_count == 0); 1017 spin_unlock(&dev->count_lock); 1018 return can_switch; 1019 } 1020 1021 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1022 .set_gpu_state = radeon_switcheroo_set_state, 1023 .reprobe = NULL, 1024 .can_switch = radeon_switcheroo_can_switch, 1025 }; 1026 1027 /** 1028 * radeon_device_init - initialize the driver 1029 * 1030 * @rdev: radeon_device pointer 1031 * @pdev: drm dev pointer 1032 * @pdev: pci dev pointer 1033 * @flags: driver flags 1034 * 1035 * Initializes the driver info and hw (all asics). 1036 * Returns 0 for success or an error on failure. 1037 * Called at driver startup. 1038 */ 1039 int radeon_device_init(struct radeon_device *rdev, 1040 struct drm_device *ddev, 1041 struct pci_dev *pdev, 1042 uint32_t flags) 1043 { 1044 int r, i; 1045 int dma_bits; 1046 1047 rdev->shutdown = false; 1048 rdev->dev = &pdev->dev; 1049 rdev->ddev = ddev; 1050 rdev->pdev = pdev; 1051 rdev->flags = flags; 1052 rdev->family = flags & RADEON_FAMILY_MASK; 1053 rdev->is_atom_bios = false; 1054 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1055 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 1056 rdev->accel_working = false; 1057 /* set up ring ids */ 1058 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1059 rdev->ring[i].idx = i; 1060 } 1061 1062 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1063 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1064 pdev->subsystem_vendor, pdev->subsystem_device); 1065 1066 /* mutex initialization are all done here so we 1067 * can recall function without having locking issues */ 1068 mutex_init(&rdev->ring_lock); 1069 mutex_init(&rdev->dc_hw_i2c_mutex); 1070 atomic_set(&rdev->ih.lock, 0); 1071 mutex_init(&rdev->gem.mutex); 1072 mutex_init(&rdev->pm.mutex); 1073 mutex_init(&rdev->gpu_clock_mutex); 1074 init_rwsem(&rdev->pm.mclk_lock); 1075 init_rwsem(&rdev->exclusive_lock); 1076 init_waitqueue_head(&rdev->irq.vblank_queue); 1077 r = radeon_gem_init(rdev); 1078 if (r) 1079 return r; 1080 /* initialize vm here */ 1081 mutex_init(&rdev->vm_manager.lock); 1082 /* Adjust VM size here. 1083 * Currently set to 4GB ((1 << 20) 4k pages). 1084 * Max GPUVM size for cayman and SI is 40 bits. 1085 */ 1086 rdev->vm_manager.max_pfn = 1 << 20; 1087 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 1088 1089 /* Set asic functions */ 1090 r = radeon_asic_init(rdev); 1091 if (r) 1092 return r; 1093 radeon_check_arguments(rdev); 1094 1095 /* all of the newer IGP chips have an internal gart 1096 * However some rs4xx report as AGP, so remove that here. 1097 */ 1098 if ((rdev->family >= CHIP_RS400) && 1099 (rdev->flags & RADEON_IS_IGP)) { 1100 rdev->flags &= ~RADEON_IS_AGP; 1101 } 1102 1103 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1104 radeon_agp_disable(rdev); 1105 } 1106 1107 /* Set the internal MC address mask 1108 * This is the max address of the GPU's 1109 * internal address space. 1110 */ 1111 if (rdev->family >= CHIP_CAYMAN) 1112 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1113 else if (rdev->family >= CHIP_CEDAR) 1114 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1115 else 1116 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1117 1118 /* set DMA mask + need_dma32 flags. 1119 * PCIE - can handle 40-bits. 1120 * IGP - can handle 40-bits 1121 * AGP - generally dma32 is safest 1122 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1123 */ 1124 rdev->need_dma32 = false; 1125 if (rdev->flags & RADEON_IS_AGP) 1126 rdev->need_dma32 = true; 1127 if ((rdev->flags & RADEON_IS_PCI) && 1128 (rdev->family <= CHIP_RS740)) 1129 rdev->need_dma32 = true; 1130 1131 dma_bits = rdev->need_dma32 ? 32 : 40; 1132 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1133 if (r) { 1134 rdev->need_dma32 = true; 1135 dma_bits = 32; 1136 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1137 } 1138 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1139 if (r) { 1140 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1141 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1142 } 1143 1144 /* Registers mapping */ 1145 /* TODO: block userspace mapping of io register */ 1146 spin_lock_init(&rdev->mmio_idx_lock); 1147 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1148 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1149 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1150 if (rdev->rmmio == NULL) { 1151 return -ENOMEM; 1152 } 1153 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1154 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1155 1156 /* io port mapping */ 1157 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1158 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1159 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1160 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1161 break; 1162 } 1163 } 1164 if (rdev->rio_mem == NULL) 1165 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1166 1167 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1168 /* this will fail for cards that aren't VGA class devices, just 1169 * ignore it */ 1170 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1171 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops); 1172 1173 r = radeon_init(rdev); 1174 if (r) 1175 return r; 1176 1177 r = radeon_ib_ring_tests(rdev); 1178 if (r) 1179 DRM_ERROR("ib ring test failed (%d).\n", r); 1180 1181 r = radeon_gem_debugfs_init(rdev); 1182 if (r) { 1183 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1184 } 1185 1186 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1187 /* Acceleration not working on AGP card try again 1188 * with fallback to PCI or PCIE GART 1189 */ 1190 radeon_asic_reset(rdev); 1191 radeon_fini(rdev); 1192 radeon_agp_disable(rdev); 1193 r = radeon_init(rdev); 1194 if (r) 1195 return r; 1196 } 1197 if ((radeon_testing & 1)) { 1198 radeon_test_moves(rdev); 1199 } 1200 if ((radeon_testing & 2)) { 1201 radeon_test_syncing(rdev); 1202 } 1203 if (radeon_benchmarking) { 1204 radeon_benchmark(rdev, radeon_benchmarking); 1205 } 1206 return 0; 1207 } 1208 1209 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1210 1211 /** 1212 * radeon_device_fini - tear down the driver 1213 * 1214 * @rdev: radeon_device pointer 1215 * 1216 * Tear down the driver info (all asics). 1217 * Called at driver shutdown. 1218 */ 1219 void radeon_device_fini(struct radeon_device *rdev) 1220 { 1221 DRM_INFO("radeon: finishing device.\n"); 1222 rdev->shutdown = true; 1223 /* evict vram memory */ 1224 radeon_bo_evict_vram(rdev); 1225 radeon_fini(rdev); 1226 vga_switcheroo_unregister_client(rdev->pdev); 1227 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1228 if (rdev->rio_mem) 1229 pci_iounmap(rdev->pdev, rdev->rio_mem); 1230 rdev->rio_mem = NULL; 1231 iounmap(rdev->rmmio); 1232 rdev->rmmio = NULL; 1233 radeon_debugfs_remove_files(rdev); 1234 } 1235 1236 1237 /* 1238 * Suspend & resume. 1239 */ 1240 /** 1241 * radeon_suspend_kms - initiate device suspend 1242 * 1243 * @pdev: drm dev pointer 1244 * @state: suspend state 1245 * 1246 * Puts the hw in the suspend state (all asics). 1247 * Returns 0 for success or an error on failure. 1248 * Called at driver suspend. 1249 */ 1250 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 1251 { 1252 struct radeon_device *rdev; 1253 struct drm_crtc *crtc; 1254 struct drm_connector *connector; 1255 int i, r; 1256 bool force_completion = false; 1257 1258 if (dev == NULL || dev->dev_private == NULL) { 1259 return -ENODEV; 1260 } 1261 if (state.event == PM_EVENT_PRETHAW) { 1262 return 0; 1263 } 1264 rdev = dev->dev_private; 1265 1266 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1267 return 0; 1268 1269 drm_kms_helper_poll_disable(dev); 1270 1271 /* turn off display hw */ 1272 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1273 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1274 } 1275 1276 /* unpin the front buffers */ 1277 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1278 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 1279 struct radeon_bo *robj; 1280 1281 if (rfb == NULL || rfb->obj == NULL) { 1282 continue; 1283 } 1284 robj = gem_to_radeon_bo(rfb->obj); 1285 /* don't unpin kernel fb objects */ 1286 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1287 r = radeon_bo_reserve(robj, false); 1288 if (r == 0) { 1289 radeon_bo_unpin(robj); 1290 radeon_bo_unreserve(robj); 1291 } 1292 } 1293 } 1294 /* evict vram memory */ 1295 radeon_bo_evict_vram(rdev); 1296 1297 mutex_lock(&rdev->ring_lock); 1298 /* wait for gpu to finish processing current batch */ 1299 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1300 r = radeon_fence_wait_empty_locked(rdev, i); 1301 if (r) { 1302 /* delay GPU reset to resume */ 1303 force_completion = true; 1304 } 1305 } 1306 if (force_completion) { 1307 radeon_fence_driver_force_completion(rdev); 1308 } 1309 mutex_unlock(&rdev->ring_lock); 1310 1311 radeon_save_bios_scratch_regs(rdev); 1312 1313 radeon_pm_suspend(rdev); 1314 radeon_suspend(rdev); 1315 radeon_hpd_fini(rdev); 1316 /* evict remaining vram memory */ 1317 radeon_bo_evict_vram(rdev); 1318 1319 radeon_agp_suspend(rdev); 1320 1321 pci_save_state(dev->pdev); 1322 if (state.event == PM_EVENT_SUSPEND) { 1323 /* Shut down the device */ 1324 pci_disable_device(dev->pdev); 1325 pci_set_power_state(dev->pdev, PCI_D3hot); 1326 } 1327 console_lock(); 1328 radeon_fbdev_set_suspend(rdev, 1); 1329 console_unlock(); 1330 return 0; 1331 } 1332 1333 /** 1334 * radeon_resume_kms - initiate device resume 1335 * 1336 * @pdev: drm dev pointer 1337 * 1338 * Bring the hw back to operating state (all asics). 1339 * Returns 0 for success or an error on failure. 1340 * Called at driver resume. 1341 */ 1342 int radeon_resume_kms(struct drm_device *dev) 1343 { 1344 struct drm_connector *connector; 1345 struct radeon_device *rdev = dev->dev_private; 1346 int r; 1347 1348 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1349 return 0; 1350 1351 console_lock(); 1352 pci_set_power_state(dev->pdev, PCI_D0); 1353 pci_restore_state(dev->pdev); 1354 if (pci_enable_device(dev->pdev)) { 1355 console_unlock(); 1356 return -1; 1357 } 1358 /* resume AGP if in use */ 1359 radeon_agp_resume(rdev); 1360 radeon_resume(rdev); 1361 1362 r = radeon_ib_ring_tests(rdev); 1363 if (r) 1364 DRM_ERROR("ib ring test failed (%d).\n", r); 1365 1366 radeon_pm_resume(rdev); 1367 radeon_restore_bios_scratch_regs(rdev); 1368 1369 radeon_fbdev_set_suspend(rdev, 0); 1370 console_unlock(); 1371 1372 /* init dig PHYs, disp eng pll */ 1373 if (rdev->is_atom_bios) { 1374 radeon_atom_encoder_init(rdev); 1375 radeon_atom_disp_eng_pll_init(rdev); 1376 /* turn on the BL */ 1377 if (rdev->mode_info.bl_encoder) { 1378 u8 bl_level = radeon_get_backlight_level(rdev, 1379 rdev->mode_info.bl_encoder); 1380 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1381 bl_level); 1382 } 1383 } 1384 /* reset hpd state */ 1385 radeon_hpd_init(rdev); 1386 /* blat the mode back in */ 1387 drm_helper_resume_force_mode(dev); 1388 /* turn on display hw */ 1389 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1390 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1391 } 1392 1393 drm_kms_helper_poll_enable(dev); 1394 return 0; 1395 } 1396 1397 /** 1398 * radeon_gpu_reset - reset the asic 1399 * 1400 * @rdev: radeon device pointer 1401 * 1402 * Attempt the reset the GPU if it has hung (all asics). 1403 * Returns 0 for success or an error on failure. 1404 */ 1405 int radeon_gpu_reset(struct radeon_device *rdev) 1406 { 1407 unsigned ring_sizes[RADEON_NUM_RINGS]; 1408 uint32_t *ring_data[RADEON_NUM_RINGS]; 1409 1410 bool saved = false; 1411 1412 int i, r; 1413 int resched; 1414 1415 down_write(&rdev->exclusive_lock); 1416 radeon_save_bios_scratch_regs(rdev); 1417 /* block TTM */ 1418 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1419 radeon_suspend(rdev); 1420 1421 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1422 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1423 &ring_data[i]); 1424 if (ring_sizes[i]) { 1425 saved = true; 1426 dev_info(rdev->dev, "Saved %d dwords of commands " 1427 "on ring %d.\n", ring_sizes[i], i); 1428 } 1429 } 1430 1431 retry: 1432 r = radeon_asic_reset(rdev); 1433 if (!r) { 1434 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1435 radeon_resume(rdev); 1436 } 1437 1438 radeon_restore_bios_scratch_regs(rdev); 1439 1440 if (!r) { 1441 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1442 radeon_ring_restore(rdev, &rdev->ring[i], 1443 ring_sizes[i], ring_data[i]); 1444 ring_sizes[i] = 0; 1445 ring_data[i] = NULL; 1446 } 1447 1448 r = radeon_ib_ring_tests(rdev); 1449 if (r) { 1450 dev_err(rdev->dev, "ib ring test failed (%d).\n", r); 1451 if (saved) { 1452 saved = false; 1453 radeon_suspend(rdev); 1454 goto retry; 1455 } 1456 } 1457 } else { 1458 radeon_fence_driver_force_completion(rdev); 1459 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1460 kfree(ring_data[i]); 1461 } 1462 } 1463 1464 drm_helper_resume_force_mode(rdev->ddev); 1465 1466 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1467 if (r) { 1468 /* bad news, how to tell it to userspace ? */ 1469 dev_info(rdev->dev, "GPU reset failed\n"); 1470 } 1471 1472 up_write(&rdev->exclusive_lock); 1473 return r; 1474 } 1475 1476 1477 /* 1478 * Debugfs 1479 */ 1480 int radeon_debugfs_add_files(struct radeon_device *rdev, 1481 struct drm_info_list *files, 1482 unsigned nfiles) 1483 { 1484 unsigned i; 1485 1486 for (i = 0; i < rdev->debugfs_count; i++) { 1487 if (rdev->debugfs[i].files == files) { 1488 /* Already registered */ 1489 return 0; 1490 } 1491 } 1492 1493 i = rdev->debugfs_count + 1; 1494 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1495 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1496 DRM_ERROR("Report so we increase " 1497 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1498 return -EINVAL; 1499 } 1500 rdev->debugfs[rdev->debugfs_count].files = files; 1501 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1502 rdev->debugfs_count = i; 1503 #if defined(CONFIG_DEBUG_FS) 1504 drm_debugfs_create_files(files, nfiles, 1505 rdev->ddev->control->debugfs_root, 1506 rdev->ddev->control); 1507 drm_debugfs_create_files(files, nfiles, 1508 rdev->ddev->primary->debugfs_root, 1509 rdev->ddev->primary); 1510 #endif 1511 return 0; 1512 } 1513 1514 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1515 { 1516 #if defined(CONFIG_DEBUG_FS) 1517 unsigned i; 1518 1519 for (i = 0; i < rdev->debugfs_count; i++) { 1520 drm_debugfs_remove_files(rdev->debugfs[i].files, 1521 rdev->debugfs[i].num_files, 1522 rdev->ddev->control); 1523 drm_debugfs_remove_files(rdev->debugfs[i].files, 1524 rdev->debugfs[i].num_files, 1525 rdev->ddev->primary); 1526 } 1527 #endif 1528 } 1529 1530 #if defined(CONFIG_DEBUG_FS) 1531 int radeon_debugfs_init(struct drm_minor *minor) 1532 { 1533 return 0; 1534 } 1535 1536 void radeon_debugfs_cleanup(struct drm_minor *minor) 1537 { 1538 } 1539 #endif 1540