1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/console.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/radeon_drm.h> 33 #include <linux/vgaarb.h> 34 #include <linux/vga_switcheroo.h> 35 #include <linux/efi.h> 36 #include "radeon_reg.h" 37 #include "radeon.h" 38 #include "atom.h" 39 40 static const char radeon_family_name[][16] = { 41 "R100", 42 "RV100", 43 "RS100", 44 "RV200", 45 "RS200", 46 "R200", 47 "RV250", 48 "RS300", 49 "RV280", 50 "R300", 51 "R350", 52 "RV350", 53 "RV380", 54 "R420", 55 "R423", 56 "RV410", 57 "RS400", 58 "RS480", 59 "RS600", 60 "RS690", 61 "RS740", 62 "RV515", 63 "R520", 64 "RV530", 65 "RV560", 66 "RV570", 67 "R580", 68 "R600", 69 "RV610", 70 "RV630", 71 "RV670", 72 "RV620", 73 "RV635", 74 "RS780", 75 "RS880", 76 "RV770", 77 "RV730", 78 "RV710", 79 "RV740", 80 "CEDAR", 81 "REDWOOD", 82 "JUNIPER", 83 "CYPRESS", 84 "HEMLOCK", 85 "PALM", 86 "SUMO", 87 "SUMO2", 88 "BARTS", 89 "TURKS", 90 "CAICOS", 91 "CAYMAN", 92 "ARUBA", 93 "TAHITI", 94 "PITCAIRN", 95 "VERDE", 96 "OLAND", 97 "HAINAN", 98 "LAST", 99 }; 100 101 /** 102 * radeon_program_register_sequence - program an array of registers. 103 * 104 * @rdev: radeon_device pointer 105 * @registers: pointer to the register array 106 * @array_size: size of the register array 107 * 108 * Programs an array or registers with and and or masks. 109 * This is a helper for setting golden registers. 110 */ 111 void radeon_program_register_sequence(struct radeon_device *rdev, 112 const u32 *registers, 113 const u32 array_size) 114 { 115 u32 tmp, reg, and_mask, or_mask; 116 int i; 117 118 if (array_size % 3) 119 return; 120 121 for (i = 0; i < array_size; i +=3) { 122 reg = registers[i + 0]; 123 and_mask = registers[i + 1]; 124 or_mask = registers[i + 2]; 125 126 if (and_mask == 0xffffffff) { 127 tmp = or_mask; 128 } else { 129 tmp = RREG32(reg); 130 tmp &= ~and_mask; 131 tmp |= or_mask; 132 } 133 WREG32(reg, tmp); 134 } 135 } 136 137 /** 138 * radeon_surface_init - Clear GPU surface registers. 139 * 140 * @rdev: radeon_device pointer 141 * 142 * Clear GPU surface registers (r1xx-r5xx). 143 */ 144 void radeon_surface_init(struct radeon_device *rdev) 145 { 146 /* FIXME: check this out */ 147 if (rdev->family < CHIP_R600) { 148 int i; 149 150 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 151 if (rdev->surface_regs[i].bo) 152 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 153 else 154 radeon_clear_surface_reg(rdev, i); 155 } 156 /* enable surfaces */ 157 WREG32(RADEON_SURFACE_CNTL, 0); 158 } 159 } 160 161 /* 162 * GPU scratch registers helpers function. 163 */ 164 /** 165 * radeon_scratch_init - Init scratch register driver information. 166 * 167 * @rdev: radeon_device pointer 168 * 169 * Init CP scratch register driver information (r1xx-r5xx) 170 */ 171 void radeon_scratch_init(struct radeon_device *rdev) 172 { 173 int i; 174 175 /* FIXME: check this out */ 176 if (rdev->family < CHIP_R300) { 177 rdev->scratch.num_reg = 5; 178 } else { 179 rdev->scratch.num_reg = 7; 180 } 181 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 182 for (i = 0; i < rdev->scratch.num_reg; i++) { 183 rdev->scratch.free[i] = true; 184 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 185 } 186 } 187 188 /** 189 * radeon_scratch_get - Allocate a scratch register 190 * 191 * @rdev: radeon_device pointer 192 * @reg: scratch register mmio offset 193 * 194 * Allocate a CP scratch register for use by the driver (all asics). 195 * Returns 0 on success or -EINVAL on failure. 196 */ 197 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 198 { 199 int i; 200 201 for (i = 0; i < rdev->scratch.num_reg; i++) { 202 if (rdev->scratch.free[i]) { 203 rdev->scratch.free[i] = false; 204 *reg = rdev->scratch.reg[i]; 205 return 0; 206 } 207 } 208 return -EINVAL; 209 } 210 211 /** 212 * radeon_scratch_free - Free a scratch register 213 * 214 * @rdev: radeon_device pointer 215 * @reg: scratch register mmio offset 216 * 217 * Free a CP scratch register allocated for use by the driver (all asics) 218 */ 219 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 220 { 221 int i; 222 223 for (i = 0; i < rdev->scratch.num_reg; i++) { 224 if (rdev->scratch.reg[i] == reg) { 225 rdev->scratch.free[i] = true; 226 return; 227 } 228 } 229 } 230 231 /* 232 * radeon_wb_*() 233 * Writeback is the the method by which the the GPU updates special pages 234 * in memory with the status of certain GPU events (fences, ring pointers, 235 * etc.). 236 */ 237 238 /** 239 * radeon_wb_disable - Disable Writeback 240 * 241 * @rdev: radeon_device pointer 242 * 243 * Disables Writeback (all asics). Used for suspend. 244 */ 245 void radeon_wb_disable(struct radeon_device *rdev) 246 { 247 int r; 248 249 if (rdev->wb.wb_obj) { 250 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 251 if (unlikely(r != 0)) 252 return; 253 radeon_bo_kunmap(rdev->wb.wb_obj); 254 radeon_bo_unpin(rdev->wb.wb_obj); 255 radeon_bo_unreserve(rdev->wb.wb_obj); 256 } 257 rdev->wb.enabled = false; 258 } 259 260 /** 261 * radeon_wb_fini - Disable Writeback and free memory 262 * 263 * @rdev: radeon_device pointer 264 * 265 * Disables Writeback and frees the Writeback memory (all asics). 266 * Used at driver shutdown. 267 */ 268 void radeon_wb_fini(struct radeon_device *rdev) 269 { 270 radeon_wb_disable(rdev); 271 if (rdev->wb.wb_obj) { 272 radeon_bo_unref(&rdev->wb.wb_obj); 273 rdev->wb.wb = NULL; 274 rdev->wb.wb_obj = NULL; 275 } 276 } 277 278 /** 279 * radeon_wb_init- Init Writeback driver info and allocate memory 280 * 281 * @rdev: radeon_device pointer 282 * 283 * Disables Writeback and frees the Writeback memory (all asics). 284 * Used at driver startup. 285 * Returns 0 on success or an -error on failure. 286 */ 287 int radeon_wb_init(struct radeon_device *rdev) 288 { 289 int r; 290 291 if (rdev->wb.wb_obj == NULL) { 292 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 293 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); 294 if (r) { 295 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 296 return r; 297 } 298 } 299 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 300 if (unlikely(r != 0)) { 301 radeon_wb_fini(rdev); 302 return r; 303 } 304 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 305 &rdev->wb.gpu_addr); 306 if (r) { 307 radeon_bo_unreserve(rdev->wb.wb_obj); 308 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 309 radeon_wb_fini(rdev); 310 return r; 311 } 312 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 313 radeon_bo_unreserve(rdev->wb.wb_obj); 314 if (r) { 315 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 316 radeon_wb_fini(rdev); 317 return r; 318 } 319 320 /* clear wb memory */ 321 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 322 /* disable event_write fences */ 323 rdev->wb.use_event = false; 324 /* disabled via module param */ 325 if (radeon_no_wb == 1) { 326 rdev->wb.enabled = false; 327 } else { 328 if (rdev->flags & RADEON_IS_AGP) { 329 /* often unreliable on AGP */ 330 rdev->wb.enabled = false; 331 } else if (rdev->family < CHIP_R300) { 332 /* often unreliable on pre-r300 */ 333 rdev->wb.enabled = false; 334 } else { 335 rdev->wb.enabled = true; 336 /* event_write fences are only available on r600+ */ 337 if (rdev->family >= CHIP_R600) { 338 rdev->wb.use_event = true; 339 } 340 } 341 } 342 /* always use writeback/events on NI, APUs */ 343 if (rdev->family >= CHIP_PALM) { 344 rdev->wb.enabled = true; 345 rdev->wb.use_event = true; 346 } 347 348 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 349 350 return 0; 351 } 352 353 /** 354 * radeon_vram_location - try to find VRAM location 355 * @rdev: radeon device structure holding all necessary informations 356 * @mc: memory controller structure holding memory informations 357 * @base: base address at which to put VRAM 358 * 359 * Function will place try to place VRAM at base address provided 360 * as parameter (which is so far either PCI aperture address or 361 * for IGP TOM base address). 362 * 363 * If there is not enough space to fit the unvisible VRAM in the 32bits 364 * address space then we limit the VRAM size to the aperture. 365 * 366 * If we are using AGP and if the AGP aperture doesn't allow us to have 367 * room for all the VRAM than we restrict the VRAM to the PCI aperture 368 * size and print a warning. 369 * 370 * This function will never fails, worst case are limiting VRAM. 371 * 372 * Note: GTT start, end, size should be initialized before calling this 373 * function on AGP platform. 374 * 375 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 376 * this shouldn't be a problem as we are using the PCI aperture as a reference. 377 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 378 * not IGP. 379 * 380 * Note: we use mc_vram_size as on some board we need to program the mc to 381 * cover the whole aperture even if VRAM size is inferior to aperture size 382 * Novell bug 204882 + along with lots of ubuntu ones 383 * 384 * Note: when limiting vram it's safe to overwritte real_vram_size because 385 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 386 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 387 * ones) 388 * 389 * Note: IGP TOM addr should be the same as the aperture addr, we don't 390 * explicitly check for that thought. 391 * 392 * FIXME: when reducing VRAM size align new size on power of 2. 393 */ 394 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 395 { 396 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 397 398 mc->vram_start = base; 399 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 400 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 401 mc->real_vram_size = mc->aper_size; 402 mc->mc_vram_size = mc->aper_size; 403 } 404 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 405 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 406 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 407 mc->real_vram_size = mc->aper_size; 408 mc->mc_vram_size = mc->aper_size; 409 } 410 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 411 if (limit && limit < mc->real_vram_size) 412 mc->real_vram_size = limit; 413 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 414 mc->mc_vram_size >> 20, mc->vram_start, 415 mc->vram_end, mc->real_vram_size >> 20); 416 } 417 418 /** 419 * radeon_gtt_location - try to find GTT location 420 * @rdev: radeon device structure holding all necessary informations 421 * @mc: memory controller structure holding memory informations 422 * 423 * Function will place try to place GTT before or after VRAM. 424 * 425 * If GTT size is bigger than space left then we ajust GTT size. 426 * Thus function will never fails. 427 * 428 * FIXME: when reducing GTT size align new size on power of 2. 429 */ 430 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 431 { 432 u64 size_af, size_bf; 433 434 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 435 size_bf = mc->vram_start & ~mc->gtt_base_align; 436 if (size_bf > size_af) { 437 if (mc->gtt_size > size_bf) { 438 dev_warn(rdev->dev, "limiting GTT\n"); 439 mc->gtt_size = size_bf; 440 } 441 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 442 } else { 443 if (mc->gtt_size > size_af) { 444 dev_warn(rdev->dev, "limiting GTT\n"); 445 mc->gtt_size = size_af; 446 } 447 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 448 } 449 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 450 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 451 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 452 } 453 454 /* 455 * GPU helpers function. 456 */ 457 /** 458 * radeon_card_posted - check if the hw has already been initialized 459 * 460 * @rdev: radeon_device pointer 461 * 462 * Check if the asic has been initialized (all asics). 463 * Used at driver startup. 464 * Returns true if initialized or false if not. 465 */ 466 bool radeon_card_posted(struct radeon_device *rdev) 467 { 468 uint32_t reg; 469 470 if (efi_enabled(EFI_BOOT) && 471 rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) 472 return false; 473 474 /* first check CRTCs */ 475 if (ASIC_IS_DCE41(rdev)) { 476 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 477 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 478 if (reg & EVERGREEN_CRTC_MASTER_EN) 479 return true; 480 } else if (ASIC_IS_DCE4(rdev)) { 481 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 482 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 483 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 484 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 485 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 486 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 487 if (reg & EVERGREEN_CRTC_MASTER_EN) 488 return true; 489 } else if (ASIC_IS_AVIVO(rdev)) { 490 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 491 RREG32(AVIVO_D2CRTC_CONTROL); 492 if (reg & AVIVO_CRTC_EN) { 493 return true; 494 } 495 } else { 496 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 497 RREG32(RADEON_CRTC2_GEN_CNTL); 498 if (reg & RADEON_CRTC_EN) { 499 return true; 500 } 501 } 502 503 /* then check MEM_SIZE, in case the crtcs are off */ 504 if (rdev->family >= CHIP_R600) 505 reg = RREG32(R600_CONFIG_MEMSIZE); 506 else 507 reg = RREG32(RADEON_CONFIG_MEMSIZE); 508 509 if (reg) 510 return true; 511 512 return false; 513 514 } 515 516 /** 517 * radeon_update_bandwidth_info - update display bandwidth params 518 * 519 * @rdev: radeon_device pointer 520 * 521 * Used when sclk/mclk are switched or display modes are set. 522 * params are used to calculate display watermarks (all asics) 523 */ 524 void radeon_update_bandwidth_info(struct radeon_device *rdev) 525 { 526 fixed20_12 a; 527 u32 sclk = rdev->pm.current_sclk; 528 u32 mclk = rdev->pm.current_mclk; 529 530 /* sclk/mclk in Mhz */ 531 a.full = dfixed_const(100); 532 rdev->pm.sclk.full = dfixed_const(sclk); 533 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 534 rdev->pm.mclk.full = dfixed_const(mclk); 535 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 536 537 if (rdev->flags & RADEON_IS_IGP) { 538 a.full = dfixed_const(16); 539 /* core_bandwidth = sclk(Mhz) * 16 */ 540 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 541 } 542 } 543 544 /** 545 * radeon_boot_test_post_card - check and possibly initialize the hw 546 * 547 * @rdev: radeon_device pointer 548 * 549 * Check if the asic is initialized and if not, attempt to initialize 550 * it (all asics). 551 * Returns true if initialized or false if not. 552 */ 553 bool radeon_boot_test_post_card(struct radeon_device *rdev) 554 { 555 if (radeon_card_posted(rdev)) 556 return true; 557 558 if (rdev->bios) { 559 DRM_INFO("GPU not posted. posting now...\n"); 560 if (rdev->is_atom_bios) 561 atom_asic_init(rdev->mode_info.atom_context); 562 else 563 radeon_combios_asic_init(rdev->ddev); 564 return true; 565 } else { 566 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 567 return false; 568 } 569 } 570 571 /** 572 * radeon_dummy_page_init - init dummy page used by the driver 573 * 574 * @rdev: radeon_device pointer 575 * 576 * Allocate the dummy page used by the driver (all asics). 577 * This dummy page is used by the driver as a filler for gart entries 578 * when pages are taken out of the GART 579 * Returns 0 on sucess, -ENOMEM on failure. 580 */ 581 int radeon_dummy_page_init(struct radeon_device *rdev) 582 { 583 if (rdev->dummy_page.page) 584 return 0; 585 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 586 if (rdev->dummy_page.page == NULL) 587 return -ENOMEM; 588 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 589 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 590 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 591 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 592 __free_page(rdev->dummy_page.page); 593 rdev->dummy_page.page = NULL; 594 return -ENOMEM; 595 } 596 return 0; 597 } 598 599 /** 600 * radeon_dummy_page_fini - free dummy page used by the driver 601 * 602 * @rdev: radeon_device pointer 603 * 604 * Frees the dummy page used by the driver (all asics). 605 */ 606 void radeon_dummy_page_fini(struct radeon_device *rdev) 607 { 608 if (rdev->dummy_page.page == NULL) 609 return; 610 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 611 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 612 __free_page(rdev->dummy_page.page); 613 rdev->dummy_page.page = NULL; 614 } 615 616 617 /* ATOM accessor methods */ 618 /* 619 * ATOM is an interpreted byte code stored in tables in the vbios. The 620 * driver registers callbacks to access registers and the interpreter 621 * in the driver parses the tables and executes then to program specific 622 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 623 * atombios.h, and atom.c 624 */ 625 626 /** 627 * cail_pll_read - read PLL register 628 * 629 * @info: atom card_info pointer 630 * @reg: PLL register offset 631 * 632 * Provides a PLL register accessor for the atom interpreter (r4xx+). 633 * Returns the value of the PLL register. 634 */ 635 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 636 { 637 struct radeon_device *rdev = info->dev->dev_private; 638 uint32_t r; 639 640 r = rdev->pll_rreg(rdev, reg); 641 return r; 642 } 643 644 /** 645 * cail_pll_write - write PLL register 646 * 647 * @info: atom card_info pointer 648 * @reg: PLL register offset 649 * @val: value to write to the pll register 650 * 651 * Provides a PLL register accessor for the atom interpreter (r4xx+). 652 */ 653 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 654 { 655 struct radeon_device *rdev = info->dev->dev_private; 656 657 rdev->pll_wreg(rdev, reg, val); 658 } 659 660 /** 661 * cail_mc_read - read MC (Memory Controller) register 662 * 663 * @info: atom card_info pointer 664 * @reg: MC register offset 665 * 666 * Provides an MC register accessor for the atom interpreter (r4xx+). 667 * Returns the value of the MC register. 668 */ 669 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 670 { 671 struct radeon_device *rdev = info->dev->dev_private; 672 uint32_t r; 673 674 r = rdev->mc_rreg(rdev, reg); 675 return r; 676 } 677 678 /** 679 * cail_mc_write - write MC (Memory Controller) register 680 * 681 * @info: atom card_info pointer 682 * @reg: MC register offset 683 * @val: value to write to the pll register 684 * 685 * Provides a MC register accessor for the atom interpreter (r4xx+). 686 */ 687 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 688 { 689 struct radeon_device *rdev = info->dev->dev_private; 690 691 rdev->mc_wreg(rdev, reg, val); 692 } 693 694 /** 695 * cail_reg_write - write MMIO register 696 * 697 * @info: atom card_info pointer 698 * @reg: MMIO register offset 699 * @val: value to write to the pll register 700 * 701 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 702 */ 703 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 704 { 705 struct radeon_device *rdev = info->dev->dev_private; 706 707 WREG32(reg*4, val); 708 } 709 710 /** 711 * cail_reg_read - read MMIO register 712 * 713 * @info: atom card_info pointer 714 * @reg: MMIO register offset 715 * 716 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 717 * Returns the value of the MMIO register. 718 */ 719 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 720 { 721 struct radeon_device *rdev = info->dev->dev_private; 722 uint32_t r; 723 724 r = RREG32(reg*4); 725 return r; 726 } 727 728 /** 729 * cail_ioreg_write - write IO register 730 * 731 * @info: atom card_info pointer 732 * @reg: IO register offset 733 * @val: value to write to the pll register 734 * 735 * Provides a IO register accessor for the atom interpreter (r4xx+). 736 */ 737 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 738 { 739 struct radeon_device *rdev = info->dev->dev_private; 740 741 WREG32_IO(reg*4, val); 742 } 743 744 /** 745 * cail_ioreg_read - read IO register 746 * 747 * @info: atom card_info pointer 748 * @reg: IO register offset 749 * 750 * Provides an IO register accessor for the atom interpreter (r4xx+). 751 * Returns the value of the IO register. 752 */ 753 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 754 { 755 struct radeon_device *rdev = info->dev->dev_private; 756 uint32_t r; 757 758 r = RREG32_IO(reg*4); 759 return r; 760 } 761 762 /** 763 * radeon_atombios_init - init the driver info and callbacks for atombios 764 * 765 * @rdev: radeon_device pointer 766 * 767 * Initializes the driver info and register access callbacks for the 768 * ATOM interpreter (r4xx+). 769 * Returns 0 on sucess, -ENOMEM on failure. 770 * Called at driver startup. 771 */ 772 int radeon_atombios_init(struct radeon_device *rdev) 773 { 774 struct card_info *atom_card_info = 775 kzalloc(sizeof(struct card_info), GFP_KERNEL); 776 777 if (!atom_card_info) 778 return -ENOMEM; 779 780 rdev->mode_info.atom_card_info = atom_card_info; 781 atom_card_info->dev = rdev->ddev; 782 atom_card_info->reg_read = cail_reg_read; 783 atom_card_info->reg_write = cail_reg_write; 784 /* needed for iio ops */ 785 if (rdev->rio_mem) { 786 atom_card_info->ioreg_read = cail_ioreg_read; 787 atom_card_info->ioreg_write = cail_ioreg_write; 788 } else { 789 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 790 atom_card_info->ioreg_read = cail_reg_read; 791 atom_card_info->ioreg_write = cail_reg_write; 792 } 793 atom_card_info->mc_read = cail_mc_read; 794 atom_card_info->mc_write = cail_mc_write; 795 atom_card_info->pll_read = cail_pll_read; 796 atom_card_info->pll_write = cail_pll_write; 797 798 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 799 if (!rdev->mode_info.atom_context) { 800 radeon_atombios_fini(rdev); 801 return -ENOMEM; 802 } 803 804 mutex_init(&rdev->mode_info.atom_context->mutex); 805 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 806 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 807 return 0; 808 } 809 810 /** 811 * radeon_atombios_fini - free the driver info and callbacks for atombios 812 * 813 * @rdev: radeon_device pointer 814 * 815 * Frees the driver info and register access callbacks for the ATOM 816 * interpreter (r4xx+). 817 * Called at driver shutdown. 818 */ 819 void radeon_atombios_fini(struct radeon_device *rdev) 820 { 821 if (rdev->mode_info.atom_context) { 822 kfree(rdev->mode_info.atom_context->scratch); 823 } 824 kfree(rdev->mode_info.atom_context); 825 rdev->mode_info.atom_context = NULL; 826 kfree(rdev->mode_info.atom_card_info); 827 rdev->mode_info.atom_card_info = NULL; 828 } 829 830 /* COMBIOS */ 831 /* 832 * COMBIOS is the bios format prior to ATOM. It provides 833 * command tables similar to ATOM, but doesn't have a unified 834 * parser. See radeon_combios.c 835 */ 836 837 /** 838 * radeon_combios_init - init the driver info for combios 839 * 840 * @rdev: radeon_device pointer 841 * 842 * Initializes the driver info for combios (r1xx-r3xx). 843 * Returns 0 on sucess. 844 * Called at driver startup. 845 */ 846 int radeon_combios_init(struct radeon_device *rdev) 847 { 848 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 849 return 0; 850 } 851 852 /** 853 * radeon_combios_fini - free the driver info for combios 854 * 855 * @rdev: radeon_device pointer 856 * 857 * Frees the driver info for combios (r1xx-r3xx). 858 * Called at driver shutdown. 859 */ 860 void radeon_combios_fini(struct radeon_device *rdev) 861 { 862 } 863 864 /* if we get transitioned to only one device, take VGA back */ 865 /** 866 * radeon_vga_set_decode - enable/disable vga decode 867 * 868 * @cookie: radeon_device pointer 869 * @state: enable/disable vga decode 870 * 871 * Enable/disable vga decode (all asics). 872 * Returns VGA resource flags. 873 */ 874 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 875 { 876 struct radeon_device *rdev = cookie; 877 radeon_vga_set_state(rdev, state); 878 if (state) 879 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 880 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 881 else 882 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 883 } 884 885 /** 886 * radeon_check_pot_argument - check that argument is a power of two 887 * 888 * @arg: value to check 889 * 890 * Validates that a certain argument is a power of two (all asics). 891 * Returns true if argument is valid. 892 */ 893 static bool radeon_check_pot_argument(int arg) 894 { 895 return (arg & (arg - 1)) == 0; 896 } 897 898 /** 899 * radeon_check_arguments - validate module params 900 * 901 * @rdev: radeon_device pointer 902 * 903 * Validates certain module parameters and updates 904 * the associated values used by the driver (all asics). 905 */ 906 static void radeon_check_arguments(struct radeon_device *rdev) 907 { 908 /* vramlimit must be a power of two */ 909 if (!radeon_check_pot_argument(radeon_vram_limit)) { 910 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 911 radeon_vram_limit); 912 radeon_vram_limit = 0; 913 } 914 915 /* gtt size must be power of two and greater or equal to 32M */ 916 if (radeon_gart_size < 32) { 917 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 918 radeon_gart_size); 919 radeon_gart_size = 512; 920 921 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 922 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 923 radeon_gart_size); 924 radeon_gart_size = 512; 925 } 926 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 927 928 /* AGP mode can only be -1, 1, 2, 4, 8 */ 929 switch (radeon_agpmode) { 930 case -1: 931 case 0: 932 case 1: 933 case 2: 934 case 4: 935 case 8: 936 break; 937 default: 938 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 939 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 940 radeon_agpmode = 0; 941 break; 942 } 943 } 944 945 /** 946 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is 947 * needed for waking up. 948 * 949 * @pdev: pci dev pointer 950 */ 951 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev) 952 { 953 954 /* 6600m in a macbook pro */ 955 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 956 pdev->subsystem_device == 0x00e2) { 957 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n"); 958 return true; 959 } 960 961 return false; 962 } 963 964 /** 965 * radeon_switcheroo_set_state - set switcheroo state 966 * 967 * @pdev: pci dev pointer 968 * @state: vga switcheroo state 969 * 970 * Callback for the switcheroo driver. Suspends or resumes the 971 * the asics before or after it is powered up using ACPI methods. 972 */ 973 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 974 { 975 struct drm_device *dev = pci_get_drvdata(pdev); 976 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 977 if (state == VGA_SWITCHEROO_ON) { 978 unsigned d3_delay = dev->pdev->d3_delay; 979 980 printk(KERN_INFO "radeon: switched on\n"); 981 /* don't suspend or resume card normally */ 982 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 983 984 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev)) 985 dev->pdev->d3_delay = 20; 986 987 radeon_resume_kms(dev); 988 989 dev->pdev->d3_delay = d3_delay; 990 991 dev->switch_power_state = DRM_SWITCH_POWER_ON; 992 drm_kms_helper_poll_enable(dev); 993 } else { 994 printk(KERN_INFO "radeon: switched off\n"); 995 drm_kms_helper_poll_disable(dev); 996 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 997 radeon_suspend_kms(dev, pmm); 998 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 999 } 1000 } 1001 1002 /** 1003 * radeon_switcheroo_can_switch - see if switcheroo state can change 1004 * 1005 * @pdev: pci dev pointer 1006 * 1007 * Callback for the switcheroo driver. Check of the switcheroo 1008 * state can be changed. 1009 * Returns true if the state can be changed, false if not. 1010 */ 1011 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1012 { 1013 struct drm_device *dev = pci_get_drvdata(pdev); 1014 bool can_switch; 1015 1016 spin_lock(&dev->count_lock); 1017 can_switch = (dev->open_count == 0); 1018 spin_unlock(&dev->count_lock); 1019 return can_switch; 1020 } 1021 1022 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1023 .set_gpu_state = radeon_switcheroo_set_state, 1024 .reprobe = NULL, 1025 .can_switch = radeon_switcheroo_can_switch, 1026 }; 1027 1028 /** 1029 * radeon_device_init - initialize the driver 1030 * 1031 * @rdev: radeon_device pointer 1032 * @pdev: drm dev pointer 1033 * @pdev: pci dev pointer 1034 * @flags: driver flags 1035 * 1036 * Initializes the driver info and hw (all asics). 1037 * Returns 0 for success or an error on failure. 1038 * Called at driver startup. 1039 */ 1040 int radeon_device_init(struct radeon_device *rdev, 1041 struct drm_device *ddev, 1042 struct pci_dev *pdev, 1043 uint32_t flags) 1044 { 1045 int r, i; 1046 int dma_bits; 1047 1048 rdev->shutdown = false; 1049 rdev->dev = &pdev->dev; 1050 rdev->ddev = ddev; 1051 rdev->pdev = pdev; 1052 rdev->flags = flags; 1053 rdev->family = flags & RADEON_FAMILY_MASK; 1054 rdev->is_atom_bios = false; 1055 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1056 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 1057 rdev->accel_working = false; 1058 /* set up ring ids */ 1059 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1060 rdev->ring[i].idx = i; 1061 } 1062 1063 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1064 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1065 pdev->subsystem_vendor, pdev->subsystem_device); 1066 1067 /* mutex initialization are all done here so we 1068 * can recall function without having locking issues */ 1069 mutex_init(&rdev->ring_lock); 1070 mutex_init(&rdev->dc_hw_i2c_mutex); 1071 atomic_set(&rdev->ih.lock, 0); 1072 mutex_init(&rdev->gem.mutex); 1073 mutex_init(&rdev->pm.mutex); 1074 mutex_init(&rdev->gpu_clock_mutex); 1075 init_rwsem(&rdev->pm.mclk_lock); 1076 init_rwsem(&rdev->exclusive_lock); 1077 init_waitqueue_head(&rdev->irq.vblank_queue); 1078 r = radeon_gem_init(rdev); 1079 if (r) 1080 return r; 1081 /* initialize vm here */ 1082 mutex_init(&rdev->vm_manager.lock); 1083 /* Adjust VM size here. 1084 * Currently set to 4GB ((1 << 20) 4k pages). 1085 * Max GPUVM size for cayman and SI is 40 bits. 1086 */ 1087 rdev->vm_manager.max_pfn = 1 << 20; 1088 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 1089 1090 /* Set asic functions */ 1091 r = radeon_asic_init(rdev); 1092 if (r) 1093 return r; 1094 radeon_check_arguments(rdev); 1095 1096 /* all of the newer IGP chips have an internal gart 1097 * However some rs4xx report as AGP, so remove that here. 1098 */ 1099 if ((rdev->family >= CHIP_RS400) && 1100 (rdev->flags & RADEON_IS_IGP)) { 1101 rdev->flags &= ~RADEON_IS_AGP; 1102 } 1103 1104 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1105 radeon_agp_disable(rdev); 1106 } 1107 1108 /* Set the internal MC address mask 1109 * This is the max address of the GPU's 1110 * internal address space. 1111 */ 1112 if (rdev->family >= CHIP_CAYMAN) 1113 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1114 else if (rdev->family >= CHIP_CEDAR) 1115 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1116 else 1117 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1118 1119 /* set DMA mask + need_dma32 flags. 1120 * PCIE - can handle 40-bits. 1121 * IGP - can handle 40-bits 1122 * AGP - generally dma32 is safest 1123 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1124 */ 1125 rdev->need_dma32 = false; 1126 if (rdev->flags & RADEON_IS_AGP) 1127 rdev->need_dma32 = true; 1128 if ((rdev->flags & RADEON_IS_PCI) && 1129 (rdev->family <= CHIP_RS740)) 1130 rdev->need_dma32 = true; 1131 1132 dma_bits = rdev->need_dma32 ? 32 : 40; 1133 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1134 if (r) { 1135 rdev->need_dma32 = true; 1136 dma_bits = 32; 1137 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1138 } 1139 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1140 if (r) { 1141 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1142 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1143 } 1144 1145 /* Registers mapping */ 1146 /* TODO: block userspace mapping of io register */ 1147 spin_lock_init(&rdev->mmio_idx_lock); 1148 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1149 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1150 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1151 if (rdev->rmmio == NULL) { 1152 return -ENOMEM; 1153 } 1154 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1155 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1156 1157 /* io port mapping */ 1158 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1159 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1160 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1161 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1162 break; 1163 } 1164 } 1165 if (rdev->rio_mem == NULL) 1166 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1167 1168 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1169 /* this will fail for cards that aren't VGA class devices, just 1170 * ignore it */ 1171 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1172 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops); 1173 1174 r = radeon_init(rdev); 1175 if (r) 1176 return r; 1177 1178 r = radeon_ib_ring_tests(rdev); 1179 if (r) 1180 DRM_ERROR("ib ring test failed (%d).\n", r); 1181 1182 r = radeon_gem_debugfs_init(rdev); 1183 if (r) { 1184 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1185 } 1186 1187 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1188 /* Acceleration not working on AGP card try again 1189 * with fallback to PCI or PCIE GART 1190 */ 1191 radeon_asic_reset(rdev); 1192 radeon_fini(rdev); 1193 radeon_agp_disable(rdev); 1194 r = radeon_init(rdev); 1195 if (r) 1196 return r; 1197 } 1198 if ((radeon_testing & 1)) { 1199 radeon_test_moves(rdev); 1200 } 1201 if ((radeon_testing & 2)) { 1202 radeon_test_syncing(rdev); 1203 } 1204 if (radeon_benchmarking) { 1205 radeon_benchmark(rdev, radeon_benchmarking); 1206 } 1207 return 0; 1208 } 1209 1210 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1211 1212 /** 1213 * radeon_device_fini - tear down the driver 1214 * 1215 * @rdev: radeon_device pointer 1216 * 1217 * Tear down the driver info (all asics). 1218 * Called at driver shutdown. 1219 */ 1220 void radeon_device_fini(struct radeon_device *rdev) 1221 { 1222 DRM_INFO("radeon: finishing device.\n"); 1223 rdev->shutdown = true; 1224 /* evict vram memory */ 1225 radeon_bo_evict_vram(rdev); 1226 radeon_fini(rdev); 1227 vga_switcheroo_unregister_client(rdev->pdev); 1228 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1229 if (rdev->rio_mem) 1230 pci_iounmap(rdev->pdev, rdev->rio_mem); 1231 rdev->rio_mem = NULL; 1232 iounmap(rdev->rmmio); 1233 rdev->rmmio = NULL; 1234 radeon_debugfs_remove_files(rdev); 1235 } 1236 1237 1238 /* 1239 * Suspend & resume. 1240 */ 1241 /** 1242 * radeon_suspend_kms - initiate device suspend 1243 * 1244 * @pdev: drm dev pointer 1245 * @state: suspend state 1246 * 1247 * Puts the hw in the suspend state (all asics). 1248 * Returns 0 for success or an error on failure. 1249 * Called at driver suspend. 1250 */ 1251 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) 1252 { 1253 struct radeon_device *rdev; 1254 struct drm_crtc *crtc; 1255 struct drm_connector *connector; 1256 int i, r; 1257 bool force_completion = false; 1258 1259 if (dev == NULL || dev->dev_private == NULL) { 1260 return -ENODEV; 1261 } 1262 if (state.event == PM_EVENT_PRETHAW) { 1263 return 0; 1264 } 1265 rdev = dev->dev_private; 1266 1267 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1268 return 0; 1269 1270 drm_kms_helper_poll_disable(dev); 1271 1272 /* turn off display hw */ 1273 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1274 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1275 } 1276 1277 /* unpin the front buffers */ 1278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1279 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 1280 struct radeon_bo *robj; 1281 1282 if (rfb == NULL || rfb->obj == NULL) { 1283 continue; 1284 } 1285 robj = gem_to_radeon_bo(rfb->obj); 1286 /* don't unpin kernel fb objects */ 1287 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1288 r = radeon_bo_reserve(robj, false); 1289 if (r == 0) { 1290 radeon_bo_unpin(robj); 1291 radeon_bo_unreserve(robj); 1292 } 1293 } 1294 } 1295 /* evict vram memory */ 1296 radeon_bo_evict_vram(rdev); 1297 1298 mutex_lock(&rdev->ring_lock); 1299 /* wait for gpu to finish processing current batch */ 1300 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1301 r = radeon_fence_wait_empty_locked(rdev, i); 1302 if (r) { 1303 /* delay GPU reset to resume */ 1304 force_completion = true; 1305 } 1306 } 1307 if (force_completion) { 1308 radeon_fence_driver_force_completion(rdev); 1309 } 1310 mutex_unlock(&rdev->ring_lock); 1311 1312 radeon_save_bios_scratch_regs(rdev); 1313 1314 radeon_pm_suspend(rdev); 1315 radeon_suspend(rdev); 1316 radeon_hpd_fini(rdev); 1317 /* evict remaining vram memory */ 1318 radeon_bo_evict_vram(rdev); 1319 1320 radeon_agp_suspend(rdev); 1321 1322 pci_save_state(dev->pdev); 1323 if (state.event == PM_EVENT_SUSPEND) { 1324 /* Shut down the device */ 1325 pci_disable_device(dev->pdev); 1326 pci_set_power_state(dev->pdev, PCI_D3hot); 1327 } 1328 console_lock(); 1329 radeon_fbdev_set_suspend(rdev, 1); 1330 console_unlock(); 1331 return 0; 1332 } 1333 1334 /** 1335 * radeon_resume_kms - initiate device resume 1336 * 1337 * @pdev: drm dev pointer 1338 * 1339 * Bring the hw back to operating state (all asics). 1340 * Returns 0 for success or an error on failure. 1341 * Called at driver resume. 1342 */ 1343 int radeon_resume_kms(struct drm_device *dev) 1344 { 1345 struct drm_connector *connector; 1346 struct radeon_device *rdev = dev->dev_private; 1347 int r; 1348 1349 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1350 return 0; 1351 1352 console_lock(); 1353 pci_set_power_state(dev->pdev, PCI_D0); 1354 pci_restore_state(dev->pdev); 1355 if (pci_enable_device(dev->pdev)) { 1356 console_unlock(); 1357 return -1; 1358 } 1359 /* resume AGP if in use */ 1360 radeon_agp_resume(rdev); 1361 radeon_resume(rdev); 1362 1363 r = radeon_ib_ring_tests(rdev); 1364 if (r) 1365 DRM_ERROR("ib ring test failed (%d).\n", r); 1366 1367 radeon_pm_resume(rdev); 1368 radeon_restore_bios_scratch_regs(rdev); 1369 1370 radeon_fbdev_set_suspend(rdev, 0); 1371 console_unlock(); 1372 1373 /* init dig PHYs, disp eng pll */ 1374 if (rdev->is_atom_bios) { 1375 radeon_atom_encoder_init(rdev); 1376 radeon_atom_disp_eng_pll_init(rdev); 1377 /* turn on the BL */ 1378 if (rdev->mode_info.bl_encoder) { 1379 u8 bl_level = radeon_get_backlight_level(rdev, 1380 rdev->mode_info.bl_encoder); 1381 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1382 bl_level); 1383 } 1384 } 1385 /* reset hpd state */ 1386 radeon_hpd_init(rdev); 1387 /* blat the mode back in */ 1388 drm_helper_resume_force_mode(dev); 1389 /* turn on display hw */ 1390 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1391 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1392 } 1393 1394 drm_kms_helper_poll_enable(dev); 1395 return 0; 1396 } 1397 1398 /** 1399 * radeon_gpu_reset - reset the asic 1400 * 1401 * @rdev: radeon device pointer 1402 * 1403 * Attempt the reset the GPU if it has hung (all asics). 1404 * Returns 0 for success or an error on failure. 1405 */ 1406 int radeon_gpu_reset(struct radeon_device *rdev) 1407 { 1408 unsigned ring_sizes[RADEON_NUM_RINGS]; 1409 uint32_t *ring_data[RADEON_NUM_RINGS]; 1410 1411 bool saved = false; 1412 1413 int i, r; 1414 int resched; 1415 1416 down_write(&rdev->exclusive_lock); 1417 radeon_save_bios_scratch_regs(rdev); 1418 /* block TTM */ 1419 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1420 radeon_suspend(rdev); 1421 1422 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1423 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1424 &ring_data[i]); 1425 if (ring_sizes[i]) { 1426 saved = true; 1427 dev_info(rdev->dev, "Saved %d dwords of commands " 1428 "on ring %d.\n", ring_sizes[i], i); 1429 } 1430 } 1431 1432 retry: 1433 r = radeon_asic_reset(rdev); 1434 if (!r) { 1435 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1436 radeon_resume(rdev); 1437 } 1438 1439 radeon_restore_bios_scratch_regs(rdev); 1440 1441 if (!r) { 1442 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1443 radeon_ring_restore(rdev, &rdev->ring[i], 1444 ring_sizes[i], ring_data[i]); 1445 ring_sizes[i] = 0; 1446 ring_data[i] = NULL; 1447 } 1448 1449 r = radeon_ib_ring_tests(rdev); 1450 if (r) { 1451 dev_err(rdev->dev, "ib ring test failed (%d).\n", r); 1452 if (saved) { 1453 saved = false; 1454 radeon_suspend(rdev); 1455 goto retry; 1456 } 1457 } 1458 } else { 1459 radeon_fence_driver_force_completion(rdev); 1460 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1461 kfree(ring_data[i]); 1462 } 1463 } 1464 1465 drm_helper_resume_force_mode(rdev->ddev); 1466 1467 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1468 if (r) { 1469 /* bad news, how to tell it to userspace ? */ 1470 dev_info(rdev->dev, "GPU reset failed\n"); 1471 } 1472 1473 up_write(&rdev->exclusive_lock); 1474 return r; 1475 } 1476 1477 1478 /* 1479 * Debugfs 1480 */ 1481 int radeon_debugfs_add_files(struct radeon_device *rdev, 1482 struct drm_info_list *files, 1483 unsigned nfiles) 1484 { 1485 unsigned i; 1486 1487 for (i = 0; i < rdev->debugfs_count; i++) { 1488 if (rdev->debugfs[i].files == files) { 1489 /* Already registered */ 1490 return 0; 1491 } 1492 } 1493 1494 i = rdev->debugfs_count + 1; 1495 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1496 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1497 DRM_ERROR("Report so we increase " 1498 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1499 return -EINVAL; 1500 } 1501 rdev->debugfs[rdev->debugfs_count].files = files; 1502 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1503 rdev->debugfs_count = i; 1504 #if defined(CONFIG_DEBUG_FS) 1505 drm_debugfs_create_files(files, nfiles, 1506 rdev->ddev->control->debugfs_root, 1507 rdev->ddev->control); 1508 drm_debugfs_create_files(files, nfiles, 1509 rdev->ddev->primary->debugfs_root, 1510 rdev->ddev->primary); 1511 #endif 1512 return 0; 1513 } 1514 1515 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1516 { 1517 #if defined(CONFIG_DEBUG_FS) 1518 unsigned i; 1519 1520 for (i = 0; i < rdev->debugfs_count; i++) { 1521 drm_debugfs_remove_files(rdev->debugfs[i].files, 1522 rdev->debugfs[i].num_files, 1523 rdev->ddev->control); 1524 drm_debugfs_remove_files(rdev->debugfs[i].files, 1525 rdev->debugfs[i].num_files, 1526 rdev->ddev->primary); 1527 } 1528 #endif 1529 } 1530 1531 #if defined(CONFIG_DEBUG_FS) 1532 int radeon_debugfs_init(struct drm_minor *minor) 1533 { 1534 return 0; 1535 } 1536 1537 void radeon_debugfs_cleanup(struct drm_minor *minor) 1538 { 1539 } 1540 #endif 1541