1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/console.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
37 #include "radeon.h"
38 #include "atom.h"
39 
40 static const char radeon_family_name[][16] = {
41 	"R100",
42 	"RV100",
43 	"RS100",
44 	"RV200",
45 	"RS200",
46 	"R200",
47 	"RV250",
48 	"RS300",
49 	"RV280",
50 	"R300",
51 	"R350",
52 	"RV350",
53 	"RV380",
54 	"R420",
55 	"R423",
56 	"RV410",
57 	"RS400",
58 	"RS480",
59 	"RS600",
60 	"RS690",
61 	"RS740",
62 	"RV515",
63 	"R520",
64 	"RV530",
65 	"RV560",
66 	"RV570",
67 	"R580",
68 	"R600",
69 	"RV610",
70 	"RV630",
71 	"RV670",
72 	"RV620",
73 	"RV635",
74 	"RS780",
75 	"RS880",
76 	"RV770",
77 	"RV730",
78 	"RV710",
79 	"RV740",
80 	"CEDAR",
81 	"REDWOOD",
82 	"JUNIPER",
83 	"CYPRESS",
84 	"HEMLOCK",
85 	"PALM",
86 	"SUMO",
87 	"SUMO2",
88 	"BARTS",
89 	"TURKS",
90 	"CAICOS",
91 	"CAYMAN",
92 	"ARUBA",
93 	"TAHITI",
94 	"PITCAIRN",
95 	"VERDE",
96 	"OLAND",
97 	"HAINAN",
98 	"BONAIRE",
99 	"KAVERI",
100 	"KABINI",
101 	"HAWAII",
102 	"MULLINS",
103 	"LAST",
104 };
105 
106 #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
107 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
108 
109 struct radeon_px_quirk {
110 	u32 chip_vendor;
111 	u32 chip_device;
112 	u32 subsys_vendor;
113 	u32 subsys_device;
114 	u32 px_quirk_flags;
115 };
116 
117 static struct radeon_px_quirk radeon_px_quirk_list[] = {
118 	/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
119 	 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
120 	 */
121 	{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
122 	/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
123 	 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
124 	 */
125 	{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
126 	/* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
127 	 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
128 	 */
129 	{ PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
130 	/* macbook pro 8.2 */
131 	{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
132 	{ 0, 0, 0, 0, 0 },
133 };
134 
135 bool radeon_is_px(struct drm_device *dev)
136 {
137 	struct radeon_device *rdev = dev->dev_private;
138 
139 	if (rdev->flags & RADEON_IS_PX)
140 		return true;
141 	return false;
142 }
143 
144 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
145 {
146 	struct radeon_px_quirk *p = radeon_px_quirk_list;
147 
148 	/* Apply PX quirks */
149 	while (p && p->chip_device != 0) {
150 		if (rdev->pdev->vendor == p->chip_vendor &&
151 		    rdev->pdev->device == p->chip_device &&
152 		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
153 		    rdev->pdev->subsystem_device == p->subsys_device) {
154 			rdev->px_quirk_flags = p->px_quirk_flags;
155 			break;
156 		}
157 		++p;
158 	}
159 
160 	if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
161 		rdev->flags &= ~RADEON_IS_PX;
162 }
163 
164 /**
165  * radeon_program_register_sequence - program an array of registers.
166  *
167  * @rdev: radeon_device pointer
168  * @registers: pointer to the register array
169  * @array_size: size of the register array
170  *
171  * Programs an array or registers with and and or masks.
172  * This is a helper for setting golden registers.
173  */
174 void radeon_program_register_sequence(struct radeon_device *rdev,
175 				      const u32 *registers,
176 				      const u32 array_size)
177 {
178 	u32 tmp, reg, and_mask, or_mask;
179 	int i;
180 
181 	if (array_size % 3)
182 		return;
183 
184 	for (i = 0; i < array_size; i +=3) {
185 		reg = registers[i + 0];
186 		and_mask = registers[i + 1];
187 		or_mask = registers[i + 2];
188 
189 		if (and_mask == 0xffffffff) {
190 			tmp = or_mask;
191 		} else {
192 			tmp = RREG32(reg);
193 			tmp &= ~and_mask;
194 			tmp |= or_mask;
195 		}
196 		WREG32(reg, tmp);
197 	}
198 }
199 
200 void radeon_pci_config_reset(struct radeon_device *rdev)
201 {
202 	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
203 }
204 
205 /**
206  * radeon_surface_init - Clear GPU surface registers.
207  *
208  * @rdev: radeon_device pointer
209  *
210  * Clear GPU surface registers (r1xx-r5xx).
211  */
212 void radeon_surface_init(struct radeon_device *rdev)
213 {
214 	/* FIXME: check this out */
215 	if (rdev->family < CHIP_R600) {
216 		int i;
217 
218 		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
219 			if (rdev->surface_regs[i].bo)
220 				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
221 			else
222 				radeon_clear_surface_reg(rdev, i);
223 		}
224 		/* enable surfaces */
225 		WREG32(RADEON_SURFACE_CNTL, 0);
226 	}
227 }
228 
229 /*
230  * GPU scratch registers helpers function.
231  */
232 /**
233  * radeon_scratch_init - Init scratch register driver information.
234  *
235  * @rdev: radeon_device pointer
236  *
237  * Init CP scratch register driver information (r1xx-r5xx)
238  */
239 void radeon_scratch_init(struct radeon_device *rdev)
240 {
241 	int i;
242 
243 	/* FIXME: check this out */
244 	if (rdev->family < CHIP_R300) {
245 		rdev->scratch.num_reg = 5;
246 	} else {
247 		rdev->scratch.num_reg = 7;
248 	}
249 	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
250 	for (i = 0; i < rdev->scratch.num_reg; i++) {
251 		rdev->scratch.free[i] = true;
252 		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
253 	}
254 }
255 
256 /**
257  * radeon_scratch_get - Allocate a scratch register
258  *
259  * @rdev: radeon_device pointer
260  * @reg: scratch register mmio offset
261  *
262  * Allocate a CP scratch register for use by the driver (all asics).
263  * Returns 0 on success or -EINVAL on failure.
264  */
265 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
266 {
267 	int i;
268 
269 	for (i = 0; i < rdev->scratch.num_reg; i++) {
270 		if (rdev->scratch.free[i]) {
271 			rdev->scratch.free[i] = false;
272 			*reg = rdev->scratch.reg[i];
273 			return 0;
274 		}
275 	}
276 	return -EINVAL;
277 }
278 
279 /**
280  * radeon_scratch_free - Free a scratch register
281  *
282  * @rdev: radeon_device pointer
283  * @reg: scratch register mmio offset
284  *
285  * Free a CP scratch register allocated for use by the driver (all asics)
286  */
287 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
288 {
289 	int i;
290 
291 	for (i = 0; i < rdev->scratch.num_reg; i++) {
292 		if (rdev->scratch.reg[i] == reg) {
293 			rdev->scratch.free[i] = true;
294 			return;
295 		}
296 	}
297 }
298 
299 /*
300  * GPU doorbell aperture helpers function.
301  */
302 /**
303  * radeon_doorbell_init - Init doorbell driver information.
304  *
305  * @rdev: radeon_device pointer
306  *
307  * Init doorbell driver information (CIK)
308  * Returns 0 on success, error on failure.
309  */
310 static int radeon_doorbell_init(struct radeon_device *rdev)
311 {
312 	/* doorbell bar mapping */
313 	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
314 	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
315 
316 	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
317 	if (rdev->doorbell.num_doorbells == 0)
318 		return -EINVAL;
319 
320 	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
321 	if (rdev->doorbell.ptr == NULL) {
322 		return -ENOMEM;
323 	}
324 	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
325 	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
326 
327 	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
328 
329 	return 0;
330 }
331 
332 /**
333  * radeon_doorbell_fini - Tear down doorbell driver information.
334  *
335  * @rdev: radeon_device pointer
336  *
337  * Tear down doorbell driver information (CIK)
338  */
339 static void radeon_doorbell_fini(struct radeon_device *rdev)
340 {
341 	iounmap(rdev->doorbell.ptr);
342 	rdev->doorbell.ptr = NULL;
343 }
344 
345 /**
346  * radeon_doorbell_get - Allocate a doorbell entry
347  *
348  * @rdev: radeon_device pointer
349  * @doorbell: doorbell index
350  *
351  * Allocate a doorbell for use by the driver (all asics).
352  * Returns 0 on success or -EINVAL on failure.
353  */
354 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
355 {
356 	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
357 	if (offset < rdev->doorbell.num_doorbells) {
358 		__set_bit(offset, rdev->doorbell.used);
359 		*doorbell = offset;
360 		return 0;
361 	} else {
362 		return -EINVAL;
363 	}
364 }
365 
366 /**
367  * radeon_doorbell_free - Free a doorbell entry
368  *
369  * @rdev: radeon_device pointer
370  * @doorbell: doorbell index
371  *
372  * Free a doorbell allocated for use by the driver (all asics)
373  */
374 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
375 {
376 	if (doorbell < rdev->doorbell.num_doorbells)
377 		__clear_bit(doorbell, rdev->doorbell.used);
378 }
379 
380 /*
381  * radeon_wb_*()
382  * Writeback is the the method by which the the GPU updates special pages
383  * in memory with the status of certain GPU events (fences, ring pointers,
384  * etc.).
385  */
386 
387 /**
388  * radeon_wb_disable - Disable Writeback
389  *
390  * @rdev: radeon_device pointer
391  *
392  * Disables Writeback (all asics).  Used for suspend.
393  */
394 void radeon_wb_disable(struct radeon_device *rdev)
395 {
396 	rdev->wb.enabled = false;
397 }
398 
399 /**
400  * radeon_wb_fini - Disable Writeback and free memory
401  *
402  * @rdev: radeon_device pointer
403  *
404  * Disables Writeback and frees the Writeback memory (all asics).
405  * Used at driver shutdown.
406  */
407 void radeon_wb_fini(struct radeon_device *rdev)
408 {
409 	radeon_wb_disable(rdev);
410 	if (rdev->wb.wb_obj) {
411 		if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
412 			radeon_bo_kunmap(rdev->wb.wb_obj);
413 			radeon_bo_unpin(rdev->wb.wb_obj);
414 			radeon_bo_unreserve(rdev->wb.wb_obj);
415 		}
416 		radeon_bo_unref(&rdev->wb.wb_obj);
417 		rdev->wb.wb = NULL;
418 		rdev->wb.wb_obj = NULL;
419 	}
420 }
421 
422 /**
423  * radeon_wb_init- Init Writeback driver info and allocate memory
424  *
425  * @rdev: radeon_device pointer
426  *
427  * Disables Writeback and frees the Writeback memory (all asics).
428  * Used at driver startup.
429  * Returns 0 on success or an -error on failure.
430  */
431 int radeon_wb_init(struct radeon_device *rdev)
432 {
433 	int r;
434 
435 	if (rdev->wb.wb_obj == NULL) {
436 		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
437 				     RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
438 				     &rdev->wb.wb_obj);
439 		if (r) {
440 			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
441 			return r;
442 		}
443 		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
444 		if (unlikely(r != 0)) {
445 			radeon_wb_fini(rdev);
446 			return r;
447 		}
448 		r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
449 				&rdev->wb.gpu_addr);
450 		if (r) {
451 			radeon_bo_unreserve(rdev->wb.wb_obj);
452 			dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
453 			radeon_wb_fini(rdev);
454 			return r;
455 		}
456 		r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
457 		radeon_bo_unreserve(rdev->wb.wb_obj);
458 		if (r) {
459 			dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
460 			radeon_wb_fini(rdev);
461 			return r;
462 		}
463 	}
464 
465 	/* clear wb memory */
466 	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
467 	/* disable event_write fences */
468 	rdev->wb.use_event = false;
469 	/* disabled via module param */
470 	if (radeon_no_wb == 1) {
471 		rdev->wb.enabled = false;
472 	} else {
473 		if (rdev->flags & RADEON_IS_AGP) {
474 			/* often unreliable on AGP */
475 			rdev->wb.enabled = false;
476 		} else if (rdev->family < CHIP_R300) {
477 			/* often unreliable on pre-r300 */
478 			rdev->wb.enabled = false;
479 		} else {
480 			rdev->wb.enabled = true;
481 			/* event_write fences are only available on r600+ */
482 			if (rdev->family >= CHIP_R600) {
483 				rdev->wb.use_event = true;
484 			}
485 		}
486 	}
487 	/* always use writeback/events on NI, APUs */
488 	if (rdev->family >= CHIP_PALM) {
489 		rdev->wb.enabled = true;
490 		rdev->wb.use_event = true;
491 	}
492 
493 	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
494 
495 	return 0;
496 }
497 
498 /**
499  * radeon_vram_location - try to find VRAM location
500  * @rdev: radeon device structure holding all necessary informations
501  * @mc: memory controller structure holding memory informations
502  * @base: base address at which to put VRAM
503  *
504  * Function will place try to place VRAM at base address provided
505  * as parameter (which is so far either PCI aperture address or
506  * for IGP TOM base address).
507  *
508  * If there is not enough space to fit the unvisible VRAM in the 32bits
509  * address space then we limit the VRAM size to the aperture.
510  *
511  * If we are using AGP and if the AGP aperture doesn't allow us to have
512  * room for all the VRAM than we restrict the VRAM to the PCI aperture
513  * size and print a warning.
514  *
515  * This function will never fails, worst case are limiting VRAM.
516  *
517  * Note: GTT start, end, size should be initialized before calling this
518  * function on AGP platform.
519  *
520  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
521  * this shouldn't be a problem as we are using the PCI aperture as a reference.
522  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
523  * not IGP.
524  *
525  * Note: we use mc_vram_size as on some board we need to program the mc to
526  * cover the whole aperture even if VRAM size is inferior to aperture size
527  * Novell bug 204882 + along with lots of ubuntu ones
528  *
529  * Note: when limiting vram it's safe to overwritte real_vram_size because
530  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
531  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
532  * ones)
533  *
534  * Note: IGP TOM addr should be the same as the aperture addr, we don't
535  * explicitly check for that thought.
536  *
537  * FIXME: when reducing VRAM size align new size on power of 2.
538  */
539 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
540 {
541 	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
542 
543 	mc->vram_start = base;
544 	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
545 		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
546 		mc->real_vram_size = mc->aper_size;
547 		mc->mc_vram_size = mc->aper_size;
548 	}
549 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
550 	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
551 		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
552 		mc->real_vram_size = mc->aper_size;
553 		mc->mc_vram_size = mc->aper_size;
554 	}
555 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
556 	if (limit && limit < mc->real_vram_size)
557 		mc->real_vram_size = limit;
558 	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
559 			mc->mc_vram_size >> 20, mc->vram_start,
560 			mc->vram_end, mc->real_vram_size >> 20);
561 }
562 
563 /**
564  * radeon_gtt_location - try to find GTT location
565  * @rdev: radeon device structure holding all necessary informations
566  * @mc: memory controller structure holding memory informations
567  *
568  * Function will place try to place GTT before or after VRAM.
569  *
570  * If GTT size is bigger than space left then we ajust GTT size.
571  * Thus function will never fails.
572  *
573  * FIXME: when reducing GTT size align new size on power of 2.
574  */
575 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
576 {
577 	u64 size_af, size_bf;
578 
579 	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
580 	size_bf = mc->vram_start & ~mc->gtt_base_align;
581 	if (size_bf > size_af) {
582 		if (mc->gtt_size > size_bf) {
583 			dev_warn(rdev->dev, "limiting GTT\n");
584 			mc->gtt_size = size_bf;
585 		}
586 		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
587 	} else {
588 		if (mc->gtt_size > size_af) {
589 			dev_warn(rdev->dev, "limiting GTT\n");
590 			mc->gtt_size = size_af;
591 		}
592 		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
593 	}
594 	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
595 	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
596 			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
597 }
598 
599 /*
600  * GPU helpers function.
601  */
602 /**
603  * radeon_card_posted - check if the hw has already been initialized
604  *
605  * @rdev: radeon_device pointer
606  *
607  * Check if the asic has been initialized (all asics).
608  * Used at driver startup.
609  * Returns true if initialized or false if not.
610  */
611 bool radeon_card_posted(struct radeon_device *rdev)
612 {
613 	uint32_t reg;
614 
615 	/* required for EFI mode on macbook2,1 which uses an r5xx asic */
616 	if (efi_enabled(EFI_BOOT) &&
617 	    (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
618 	    (rdev->family < CHIP_R600))
619 		return false;
620 
621 	if (ASIC_IS_NODCE(rdev))
622 		goto check_memsize;
623 
624 	/* first check CRTCs */
625 	if (ASIC_IS_DCE4(rdev)) {
626 		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
627 			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
628 			if (rdev->num_crtc >= 4) {
629 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
630 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
631 			}
632 			if (rdev->num_crtc >= 6) {
633 				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
634 					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
635 			}
636 		if (reg & EVERGREEN_CRTC_MASTER_EN)
637 			return true;
638 	} else if (ASIC_IS_AVIVO(rdev)) {
639 		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
640 		      RREG32(AVIVO_D2CRTC_CONTROL);
641 		if (reg & AVIVO_CRTC_EN) {
642 			return true;
643 		}
644 	} else {
645 		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
646 		      RREG32(RADEON_CRTC2_GEN_CNTL);
647 		if (reg & RADEON_CRTC_EN) {
648 			return true;
649 		}
650 	}
651 
652 check_memsize:
653 	/* then check MEM_SIZE, in case the crtcs are off */
654 	if (rdev->family >= CHIP_R600)
655 		reg = RREG32(R600_CONFIG_MEMSIZE);
656 	else
657 		reg = RREG32(RADEON_CONFIG_MEMSIZE);
658 
659 	if (reg)
660 		return true;
661 
662 	return false;
663 
664 }
665 
666 /**
667  * radeon_update_bandwidth_info - update display bandwidth params
668  *
669  * @rdev: radeon_device pointer
670  *
671  * Used when sclk/mclk are switched or display modes are set.
672  * params are used to calculate display watermarks (all asics)
673  */
674 void radeon_update_bandwidth_info(struct radeon_device *rdev)
675 {
676 	fixed20_12 a;
677 	u32 sclk = rdev->pm.current_sclk;
678 	u32 mclk = rdev->pm.current_mclk;
679 
680 	/* sclk/mclk in Mhz */
681 	a.full = dfixed_const(100);
682 	rdev->pm.sclk.full = dfixed_const(sclk);
683 	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
684 	rdev->pm.mclk.full = dfixed_const(mclk);
685 	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
686 
687 	if (rdev->flags & RADEON_IS_IGP) {
688 		a.full = dfixed_const(16);
689 		/* core_bandwidth = sclk(Mhz) * 16 */
690 		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
691 	}
692 }
693 
694 /**
695  * radeon_boot_test_post_card - check and possibly initialize the hw
696  *
697  * @rdev: radeon_device pointer
698  *
699  * Check if the asic is initialized and if not, attempt to initialize
700  * it (all asics).
701  * Returns true if initialized or false if not.
702  */
703 bool radeon_boot_test_post_card(struct radeon_device *rdev)
704 {
705 	if (radeon_card_posted(rdev))
706 		return true;
707 
708 	if (rdev->bios) {
709 		DRM_INFO("GPU not posted. posting now...\n");
710 		if (rdev->is_atom_bios)
711 			atom_asic_init(rdev->mode_info.atom_context);
712 		else
713 			radeon_combios_asic_init(rdev->ddev);
714 		return true;
715 	} else {
716 		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
717 		return false;
718 	}
719 }
720 
721 /**
722  * radeon_dummy_page_init - init dummy page used by the driver
723  *
724  * @rdev: radeon_device pointer
725  *
726  * Allocate the dummy page used by the driver (all asics).
727  * This dummy page is used by the driver as a filler for gart entries
728  * when pages are taken out of the GART
729  * Returns 0 on sucess, -ENOMEM on failure.
730  */
731 int radeon_dummy_page_init(struct radeon_device *rdev)
732 {
733 	if (rdev->dummy_page.page)
734 		return 0;
735 	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
736 	if (rdev->dummy_page.page == NULL)
737 		return -ENOMEM;
738 	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
739 					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
740 	if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
741 		dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
742 		__free_page(rdev->dummy_page.page);
743 		rdev->dummy_page.page = NULL;
744 		return -ENOMEM;
745 	}
746 	return 0;
747 }
748 
749 /**
750  * radeon_dummy_page_fini - free dummy page used by the driver
751  *
752  * @rdev: radeon_device pointer
753  *
754  * Frees the dummy page used by the driver (all asics).
755  */
756 void radeon_dummy_page_fini(struct radeon_device *rdev)
757 {
758 	if (rdev->dummy_page.page == NULL)
759 		return;
760 	pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
761 			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
762 	__free_page(rdev->dummy_page.page);
763 	rdev->dummy_page.page = NULL;
764 }
765 
766 
767 /* ATOM accessor methods */
768 /*
769  * ATOM is an interpreted byte code stored in tables in the vbios.  The
770  * driver registers callbacks to access registers and the interpreter
771  * in the driver parses the tables and executes then to program specific
772  * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
773  * atombios.h, and atom.c
774  */
775 
776 /**
777  * cail_pll_read - read PLL register
778  *
779  * @info: atom card_info pointer
780  * @reg: PLL register offset
781  *
782  * Provides a PLL register accessor for the atom interpreter (r4xx+).
783  * Returns the value of the PLL register.
784  */
785 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
786 {
787 	struct radeon_device *rdev = info->dev->dev_private;
788 	uint32_t r;
789 
790 	r = rdev->pll_rreg(rdev, reg);
791 	return r;
792 }
793 
794 /**
795  * cail_pll_write - write PLL register
796  *
797  * @info: atom card_info pointer
798  * @reg: PLL register offset
799  * @val: value to write to the pll register
800  *
801  * Provides a PLL register accessor for the atom interpreter (r4xx+).
802  */
803 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
804 {
805 	struct radeon_device *rdev = info->dev->dev_private;
806 
807 	rdev->pll_wreg(rdev, reg, val);
808 }
809 
810 /**
811  * cail_mc_read - read MC (Memory Controller) register
812  *
813  * @info: atom card_info pointer
814  * @reg: MC register offset
815  *
816  * Provides an MC register accessor for the atom interpreter (r4xx+).
817  * Returns the value of the MC register.
818  */
819 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
820 {
821 	struct radeon_device *rdev = info->dev->dev_private;
822 	uint32_t r;
823 
824 	r = rdev->mc_rreg(rdev, reg);
825 	return r;
826 }
827 
828 /**
829  * cail_mc_write - write MC (Memory Controller) register
830  *
831  * @info: atom card_info pointer
832  * @reg: MC register offset
833  * @val: value to write to the pll register
834  *
835  * Provides a MC register accessor for the atom interpreter (r4xx+).
836  */
837 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
838 {
839 	struct radeon_device *rdev = info->dev->dev_private;
840 
841 	rdev->mc_wreg(rdev, reg, val);
842 }
843 
844 /**
845  * cail_reg_write - write MMIO register
846  *
847  * @info: atom card_info pointer
848  * @reg: MMIO register offset
849  * @val: value to write to the pll register
850  *
851  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
852  */
853 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
854 {
855 	struct radeon_device *rdev = info->dev->dev_private;
856 
857 	WREG32(reg*4, val);
858 }
859 
860 /**
861  * cail_reg_read - read MMIO register
862  *
863  * @info: atom card_info pointer
864  * @reg: MMIO register offset
865  *
866  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
867  * Returns the value of the MMIO register.
868  */
869 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
870 {
871 	struct radeon_device *rdev = info->dev->dev_private;
872 	uint32_t r;
873 
874 	r = RREG32(reg*4);
875 	return r;
876 }
877 
878 /**
879  * cail_ioreg_write - write IO register
880  *
881  * @info: atom card_info pointer
882  * @reg: IO register offset
883  * @val: value to write to the pll register
884  *
885  * Provides a IO register accessor for the atom interpreter (r4xx+).
886  */
887 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
888 {
889 	struct radeon_device *rdev = info->dev->dev_private;
890 
891 	WREG32_IO(reg*4, val);
892 }
893 
894 /**
895  * cail_ioreg_read - read IO register
896  *
897  * @info: atom card_info pointer
898  * @reg: IO register offset
899  *
900  * Provides an IO register accessor for the atom interpreter (r4xx+).
901  * Returns the value of the IO register.
902  */
903 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
904 {
905 	struct radeon_device *rdev = info->dev->dev_private;
906 	uint32_t r;
907 
908 	r = RREG32_IO(reg*4);
909 	return r;
910 }
911 
912 /**
913  * radeon_atombios_init - init the driver info and callbacks for atombios
914  *
915  * @rdev: radeon_device pointer
916  *
917  * Initializes the driver info and register access callbacks for the
918  * ATOM interpreter (r4xx+).
919  * Returns 0 on sucess, -ENOMEM on failure.
920  * Called at driver startup.
921  */
922 int radeon_atombios_init(struct radeon_device *rdev)
923 {
924 	struct card_info *atom_card_info =
925 	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
926 
927 	if (!atom_card_info)
928 		return -ENOMEM;
929 
930 	rdev->mode_info.atom_card_info = atom_card_info;
931 	atom_card_info->dev = rdev->ddev;
932 	atom_card_info->reg_read = cail_reg_read;
933 	atom_card_info->reg_write = cail_reg_write;
934 	/* needed for iio ops */
935 	if (rdev->rio_mem) {
936 		atom_card_info->ioreg_read = cail_ioreg_read;
937 		atom_card_info->ioreg_write = cail_ioreg_write;
938 	} else {
939 		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
940 		atom_card_info->ioreg_read = cail_reg_read;
941 		atom_card_info->ioreg_write = cail_reg_write;
942 	}
943 	atom_card_info->mc_read = cail_mc_read;
944 	atom_card_info->mc_write = cail_mc_write;
945 	atom_card_info->pll_read = cail_pll_read;
946 	atom_card_info->pll_write = cail_pll_write;
947 
948 	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
949 	if (!rdev->mode_info.atom_context) {
950 		radeon_atombios_fini(rdev);
951 		return -ENOMEM;
952 	}
953 
954 	mutex_init(&rdev->mode_info.atom_context->mutex);
955 	mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
956 	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
957 	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
958 	return 0;
959 }
960 
961 /**
962  * radeon_atombios_fini - free the driver info and callbacks for atombios
963  *
964  * @rdev: radeon_device pointer
965  *
966  * Frees the driver info and register access callbacks for the ATOM
967  * interpreter (r4xx+).
968  * Called at driver shutdown.
969  */
970 void radeon_atombios_fini(struct radeon_device *rdev)
971 {
972 	if (rdev->mode_info.atom_context) {
973 		kfree(rdev->mode_info.atom_context->scratch);
974 	}
975 	kfree(rdev->mode_info.atom_context);
976 	rdev->mode_info.atom_context = NULL;
977 	kfree(rdev->mode_info.atom_card_info);
978 	rdev->mode_info.atom_card_info = NULL;
979 }
980 
981 /* COMBIOS */
982 /*
983  * COMBIOS is the bios format prior to ATOM. It provides
984  * command tables similar to ATOM, but doesn't have a unified
985  * parser.  See radeon_combios.c
986  */
987 
988 /**
989  * radeon_combios_init - init the driver info for combios
990  *
991  * @rdev: radeon_device pointer
992  *
993  * Initializes the driver info for combios (r1xx-r3xx).
994  * Returns 0 on sucess.
995  * Called at driver startup.
996  */
997 int radeon_combios_init(struct radeon_device *rdev)
998 {
999 	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1000 	return 0;
1001 }
1002 
1003 /**
1004  * radeon_combios_fini - free the driver info for combios
1005  *
1006  * @rdev: radeon_device pointer
1007  *
1008  * Frees the driver info for combios (r1xx-r3xx).
1009  * Called at driver shutdown.
1010  */
1011 void radeon_combios_fini(struct radeon_device *rdev)
1012 {
1013 }
1014 
1015 /* if we get transitioned to only one device, take VGA back */
1016 /**
1017  * radeon_vga_set_decode - enable/disable vga decode
1018  *
1019  * @cookie: radeon_device pointer
1020  * @state: enable/disable vga decode
1021  *
1022  * Enable/disable vga decode (all asics).
1023  * Returns VGA resource flags.
1024  */
1025 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1026 {
1027 	struct radeon_device *rdev = cookie;
1028 	radeon_vga_set_state(rdev, state);
1029 	if (state)
1030 		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1031 		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1032 	else
1033 		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1034 }
1035 
1036 /**
1037  * radeon_check_pot_argument - check that argument is a power of two
1038  *
1039  * @arg: value to check
1040  *
1041  * Validates that a certain argument is a power of two (all asics).
1042  * Returns true if argument is valid.
1043  */
1044 static bool radeon_check_pot_argument(int arg)
1045 {
1046 	return (arg & (arg - 1)) == 0;
1047 }
1048 
1049 /**
1050  * radeon_check_arguments - validate module params
1051  *
1052  * @rdev: radeon_device pointer
1053  *
1054  * Validates certain module parameters and updates
1055  * the associated values used by the driver (all asics).
1056  */
1057 static void radeon_check_arguments(struct radeon_device *rdev)
1058 {
1059 	/* vramlimit must be a power of two */
1060 	if (!radeon_check_pot_argument(radeon_vram_limit)) {
1061 		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1062 				radeon_vram_limit);
1063 		radeon_vram_limit = 0;
1064 	}
1065 
1066 	if (radeon_gart_size == -1) {
1067 		/* default to a larger gart size on newer asics */
1068 		if (rdev->family >= CHIP_RV770)
1069 			radeon_gart_size = 1024;
1070 		else
1071 			radeon_gart_size = 512;
1072 	}
1073 	/* gtt size must be power of two and greater or equal to 32M */
1074 	if (radeon_gart_size < 32) {
1075 		dev_warn(rdev->dev, "gart size (%d) too small\n",
1076 				radeon_gart_size);
1077 		if (rdev->family >= CHIP_RV770)
1078 			radeon_gart_size = 1024;
1079 		else
1080 			radeon_gart_size = 512;
1081 	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
1082 		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1083 				radeon_gart_size);
1084 		if (rdev->family >= CHIP_RV770)
1085 			radeon_gart_size = 1024;
1086 		else
1087 			radeon_gart_size = 512;
1088 	}
1089 	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1090 
1091 	/* AGP mode can only be -1, 1, 2, 4, 8 */
1092 	switch (radeon_agpmode) {
1093 	case -1:
1094 	case 0:
1095 	case 1:
1096 	case 2:
1097 	case 4:
1098 	case 8:
1099 		break;
1100 	default:
1101 		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1102 				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1103 		radeon_agpmode = 0;
1104 		break;
1105 	}
1106 
1107 	if (!radeon_check_pot_argument(radeon_vm_size)) {
1108 		dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1109 			 radeon_vm_size);
1110 		radeon_vm_size = 4;
1111 	}
1112 
1113 	if (radeon_vm_size < 1) {
1114 		dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
1115 			 radeon_vm_size);
1116 		radeon_vm_size = 4;
1117 	}
1118 
1119        /*
1120         * Max GPUVM size for Cayman, SI and CI are 40 bits.
1121         */
1122 	if (radeon_vm_size > 1024) {
1123 		dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1124 			 radeon_vm_size);
1125 		radeon_vm_size = 4;
1126 	}
1127 
1128 	/* defines number of bits in page table versus page directory,
1129 	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1130 	 * page table and the remaining bits are in the page directory */
1131 	if (radeon_vm_block_size == -1) {
1132 
1133 		/* Total bits covered by PD + PTs */
1134 		unsigned bits = ilog2(radeon_vm_size) + 18;
1135 
1136 		/* Make sure the PD is 4K in size up to 8GB address space.
1137 		   Above that split equal between PD and PTs */
1138 		if (radeon_vm_size <= 8)
1139 			radeon_vm_block_size = bits - 9;
1140 		else
1141 			radeon_vm_block_size = (bits + 3) / 2;
1142 
1143 	} else if (radeon_vm_block_size < 9) {
1144 		dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1145 			 radeon_vm_block_size);
1146 		radeon_vm_block_size = 9;
1147 	}
1148 
1149 	if (radeon_vm_block_size > 24 ||
1150 	    (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1151 		dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1152 			 radeon_vm_block_size);
1153 		radeon_vm_block_size = 9;
1154 	}
1155 }
1156 
1157 /**
1158  * radeon_switcheroo_set_state - set switcheroo state
1159  *
1160  * @pdev: pci dev pointer
1161  * @state: vga switcheroo state
1162  *
1163  * Callback for the switcheroo driver.  Suspends or resumes the
1164  * the asics before or after it is powered up using ACPI methods.
1165  */
1166 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1167 {
1168 	struct drm_device *dev = pci_get_drvdata(pdev);
1169 	struct radeon_device *rdev = dev->dev_private;
1170 
1171 	if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1172 		return;
1173 
1174 	if (state == VGA_SWITCHEROO_ON) {
1175 		unsigned d3_delay = dev->pdev->d3_delay;
1176 
1177 		printk(KERN_INFO "radeon: switched on\n");
1178 		/* don't suspend or resume card normally */
1179 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1180 
1181 		if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
1182 			dev->pdev->d3_delay = 20;
1183 
1184 		radeon_resume_kms(dev, true, true);
1185 
1186 		dev->pdev->d3_delay = d3_delay;
1187 
1188 		dev->switch_power_state = DRM_SWITCH_POWER_ON;
1189 		drm_kms_helper_poll_enable(dev);
1190 	} else {
1191 		printk(KERN_INFO "radeon: switched off\n");
1192 		drm_kms_helper_poll_disable(dev);
1193 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1194 		radeon_suspend_kms(dev, true, true);
1195 		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1196 	}
1197 }
1198 
1199 /**
1200  * radeon_switcheroo_can_switch - see if switcheroo state can change
1201  *
1202  * @pdev: pci dev pointer
1203  *
1204  * Callback for the switcheroo driver.  Check of the switcheroo
1205  * state can be changed.
1206  * Returns true if the state can be changed, false if not.
1207  */
1208 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1209 {
1210 	struct drm_device *dev = pci_get_drvdata(pdev);
1211 
1212 	/*
1213 	 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1214 	 * locking inversion with the driver load path. And the access here is
1215 	 * completely racy anyway. So don't bother with locking for now.
1216 	 */
1217 	return dev->open_count == 0;
1218 }
1219 
1220 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1221 	.set_gpu_state = radeon_switcheroo_set_state,
1222 	.reprobe = NULL,
1223 	.can_switch = radeon_switcheroo_can_switch,
1224 };
1225 
1226 /**
1227  * radeon_device_init - initialize the driver
1228  *
1229  * @rdev: radeon_device pointer
1230  * @pdev: drm dev pointer
1231  * @pdev: pci dev pointer
1232  * @flags: driver flags
1233  *
1234  * Initializes the driver info and hw (all asics).
1235  * Returns 0 for success or an error on failure.
1236  * Called at driver startup.
1237  */
1238 int radeon_device_init(struct radeon_device *rdev,
1239 		       struct drm_device *ddev,
1240 		       struct pci_dev *pdev,
1241 		       uint32_t flags)
1242 {
1243 	int r, i;
1244 	int dma_bits;
1245 	bool runtime = false;
1246 
1247 	rdev->shutdown = false;
1248 	rdev->dev = &pdev->dev;
1249 	rdev->ddev = ddev;
1250 	rdev->pdev = pdev;
1251 	rdev->flags = flags;
1252 	rdev->family = flags & RADEON_FAMILY_MASK;
1253 	rdev->is_atom_bios = false;
1254 	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1255 	rdev->mc.gtt_size = 512 * 1024 * 1024;
1256 	rdev->accel_working = false;
1257 	/* set up ring ids */
1258 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
1259 		rdev->ring[i].idx = i;
1260 	}
1261 	rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
1262 
1263 	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1264 		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1265 		pdev->subsystem_vendor, pdev->subsystem_device);
1266 
1267 	/* mutex initialization are all done here so we
1268 	 * can recall function without having locking issues */
1269 	mutex_init(&rdev->ring_lock);
1270 	mutex_init(&rdev->dc_hw_i2c_mutex);
1271 	atomic_set(&rdev->ih.lock, 0);
1272 	mutex_init(&rdev->gem.mutex);
1273 	mutex_init(&rdev->pm.mutex);
1274 	mutex_init(&rdev->gpu_clock_mutex);
1275 	mutex_init(&rdev->srbm_mutex);
1276 	init_rwsem(&rdev->pm.mclk_lock);
1277 	init_rwsem(&rdev->exclusive_lock);
1278 	init_waitqueue_head(&rdev->irq.vblank_queue);
1279 	mutex_init(&rdev->mn_lock);
1280 	hash_init(rdev->mn_hash);
1281 	r = radeon_gem_init(rdev);
1282 	if (r)
1283 		return r;
1284 
1285 	radeon_check_arguments(rdev);
1286 	/* Adjust VM size here.
1287 	 * Max GPUVM size for cayman+ is 40 bits.
1288 	 */
1289 	rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1290 
1291 	/* Set asic functions */
1292 	r = radeon_asic_init(rdev);
1293 	if (r)
1294 		return r;
1295 
1296 	/* all of the newer IGP chips have an internal gart
1297 	 * However some rs4xx report as AGP, so remove that here.
1298 	 */
1299 	if ((rdev->family >= CHIP_RS400) &&
1300 	    (rdev->flags & RADEON_IS_IGP)) {
1301 		rdev->flags &= ~RADEON_IS_AGP;
1302 	}
1303 
1304 	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1305 		radeon_agp_disable(rdev);
1306 	}
1307 
1308 	/* Set the internal MC address mask
1309 	 * This is the max address of the GPU's
1310 	 * internal address space.
1311 	 */
1312 	if (rdev->family >= CHIP_CAYMAN)
1313 		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1314 	else if (rdev->family >= CHIP_CEDAR)
1315 		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1316 	else
1317 		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1318 
1319 	/* set DMA mask + need_dma32 flags.
1320 	 * PCIE - can handle 40-bits.
1321 	 * IGP - can handle 40-bits
1322 	 * AGP - generally dma32 is safest
1323 	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1324 	 */
1325 	rdev->need_dma32 = false;
1326 	if (rdev->flags & RADEON_IS_AGP)
1327 		rdev->need_dma32 = true;
1328 	if ((rdev->flags & RADEON_IS_PCI) &&
1329 	    (rdev->family <= CHIP_RS740))
1330 		rdev->need_dma32 = true;
1331 
1332 	dma_bits = rdev->need_dma32 ? 32 : 40;
1333 	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1334 	if (r) {
1335 		rdev->need_dma32 = true;
1336 		dma_bits = 32;
1337 		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1338 	}
1339 	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1340 	if (r) {
1341 		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1342 		printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1343 	}
1344 
1345 	/* Registers mapping */
1346 	/* TODO: block userspace mapping of io register */
1347 	spin_lock_init(&rdev->mmio_idx_lock);
1348 	spin_lock_init(&rdev->smc_idx_lock);
1349 	spin_lock_init(&rdev->pll_idx_lock);
1350 	spin_lock_init(&rdev->mc_idx_lock);
1351 	spin_lock_init(&rdev->pcie_idx_lock);
1352 	spin_lock_init(&rdev->pciep_idx_lock);
1353 	spin_lock_init(&rdev->pif_idx_lock);
1354 	spin_lock_init(&rdev->cg_idx_lock);
1355 	spin_lock_init(&rdev->uvd_idx_lock);
1356 	spin_lock_init(&rdev->rcu_idx_lock);
1357 	spin_lock_init(&rdev->didt_idx_lock);
1358 	spin_lock_init(&rdev->end_idx_lock);
1359 	if (rdev->family >= CHIP_BONAIRE) {
1360 		rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1361 		rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1362 	} else {
1363 		rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1364 		rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1365 	}
1366 	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1367 	if (rdev->rmmio == NULL) {
1368 		return -ENOMEM;
1369 	}
1370 	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1371 	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1372 
1373 	/* doorbell bar mapping */
1374 	if (rdev->family >= CHIP_BONAIRE)
1375 		radeon_doorbell_init(rdev);
1376 
1377 	/* io port mapping */
1378 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1379 		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1380 			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1381 			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1382 			break;
1383 		}
1384 	}
1385 	if (rdev->rio_mem == NULL)
1386 		DRM_ERROR("Unable to find PCI I/O BAR\n");
1387 
1388 	if (rdev->flags & RADEON_IS_PX)
1389 		radeon_device_handle_px_quirks(rdev);
1390 
1391 	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
1392 	/* this will fail for cards that aren't VGA class devices, just
1393 	 * ignore it */
1394 	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1395 
1396 	if (rdev->flags & RADEON_IS_PX)
1397 		runtime = true;
1398 	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1399 	if (runtime)
1400 		vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1401 
1402 	r = radeon_init(rdev);
1403 	if (r)
1404 		goto failed;
1405 
1406 	r = radeon_gem_debugfs_init(rdev);
1407 	if (r) {
1408 		DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1409 	}
1410 
1411 	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1412 		/* Acceleration not working on AGP card try again
1413 		 * with fallback to PCI or PCIE GART
1414 		 */
1415 		radeon_asic_reset(rdev);
1416 		radeon_fini(rdev);
1417 		radeon_agp_disable(rdev);
1418 		r = radeon_init(rdev);
1419 		if (r)
1420 			goto failed;
1421 	}
1422 
1423 	r = radeon_ib_ring_tests(rdev);
1424 	if (r)
1425 		DRM_ERROR("ib ring test failed (%d).\n", r);
1426 
1427 	if ((radeon_testing & 1)) {
1428 		if (rdev->accel_working)
1429 			radeon_test_moves(rdev);
1430 		else
1431 			DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1432 	}
1433 	if ((radeon_testing & 2)) {
1434 		if (rdev->accel_working)
1435 			radeon_test_syncing(rdev);
1436 		else
1437 			DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1438 	}
1439 	if (radeon_benchmarking) {
1440 		if (rdev->accel_working)
1441 			radeon_benchmark(rdev, radeon_benchmarking);
1442 		else
1443 			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1444 	}
1445 	return 0;
1446 
1447 failed:
1448 	if (runtime)
1449 		vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1450 	return r;
1451 }
1452 
1453 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1454 
1455 /**
1456  * radeon_device_fini - tear down the driver
1457  *
1458  * @rdev: radeon_device pointer
1459  *
1460  * Tear down the driver info (all asics).
1461  * Called at driver shutdown.
1462  */
1463 void radeon_device_fini(struct radeon_device *rdev)
1464 {
1465 	DRM_INFO("radeon: finishing device.\n");
1466 	rdev->shutdown = true;
1467 	/* evict vram memory */
1468 	radeon_bo_evict_vram(rdev);
1469 	radeon_fini(rdev);
1470 	vga_switcheroo_unregister_client(rdev->pdev);
1471 	if (rdev->flags & RADEON_IS_PX)
1472 		vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1473 	vga_client_register(rdev->pdev, NULL, NULL, NULL);
1474 	if (rdev->rio_mem)
1475 		pci_iounmap(rdev->pdev, rdev->rio_mem);
1476 	rdev->rio_mem = NULL;
1477 	iounmap(rdev->rmmio);
1478 	rdev->rmmio = NULL;
1479 	if (rdev->family >= CHIP_BONAIRE)
1480 		radeon_doorbell_fini(rdev);
1481 	radeon_debugfs_remove_files(rdev);
1482 }
1483 
1484 
1485 /*
1486  * Suspend & resume.
1487  */
1488 /**
1489  * radeon_suspend_kms - initiate device suspend
1490  *
1491  * @pdev: drm dev pointer
1492  * @state: suspend state
1493  *
1494  * Puts the hw in the suspend state (all asics).
1495  * Returns 0 for success or an error on failure.
1496  * Called at driver suspend.
1497  */
1498 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1499 {
1500 	struct radeon_device *rdev;
1501 	struct drm_crtc *crtc;
1502 	struct drm_connector *connector;
1503 	int i, r;
1504 
1505 	if (dev == NULL || dev->dev_private == NULL) {
1506 		return -ENODEV;
1507 	}
1508 
1509 	rdev = dev->dev_private;
1510 
1511 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1512 		return 0;
1513 
1514 	drm_kms_helper_poll_disable(dev);
1515 
1516 	/* turn off display hw */
1517 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1518 		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1519 	}
1520 
1521 	/* unpin the front buffers */
1522 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1523 		struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1524 		struct radeon_bo *robj;
1525 
1526 		if (rfb == NULL || rfb->obj == NULL) {
1527 			continue;
1528 		}
1529 		robj = gem_to_radeon_bo(rfb->obj);
1530 		/* don't unpin kernel fb objects */
1531 		if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1532 			r = radeon_bo_reserve(robj, false);
1533 			if (r == 0) {
1534 				radeon_bo_unpin(robj);
1535 				radeon_bo_unreserve(robj);
1536 			}
1537 		}
1538 	}
1539 	/* evict vram memory */
1540 	radeon_bo_evict_vram(rdev);
1541 
1542 	/* wait for gpu to finish processing current batch */
1543 	for (i = 0; i < RADEON_NUM_RINGS; i++) {
1544 		r = radeon_fence_wait_empty(rdev, i);
1545 		if (r) {
1546 			/* delay GPU reset to resume */
1547 			radeon_fence_driver_force_completion(rdev, i);
1548 		}
1549 	}
1550 
1551 	radeon_save_bios_scratch_regs(rdev);
1552 
1553 	radeon_suspend(rdev);
1554 	radeon_hpd_fini(rdev);
1555 	/* evict remaining vram memory */
1556 	radeon_bo_evict_vram(rdev);
1557 
1558 	radeon_agp_suspend(rdev);
1559 
1560 	pci_save_state(dev->pdev);
1561 	if (suspend) {
1562 		/* Shut down the device */
1563 		pci_disable_device(dev->pdev);
1564 		pci_set_power_state(dev->pdev, PCI_D3hot);
1565 	}
1566 
1567 	if (fbcon) {
1568 		console_lock();
1569 		radeon_fbdev_set_suspend(rdev, 1);
1570 		console_unlock();
1571 	}
1572 	return 0;
1573 }
1574 
1575 /**
1576  * radeon_resume_kms - initiate device resume
1577  *
1578  * @pdev: drm dev pointer
1579  *
1580  * Bring the hw back to operating state (all asics).
1581  * Returns 0 for success or an error on failure.
1582  * Called at driver resume.
1583  */
1584 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1585 {
1586 	struct drm_connector *connector;
1587 	struct radeon_device *rdev = dev->dev_private;
1588 	int r;
1589 
1590 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1591 		return 0;
1592 
1593 	if (fbcon) {
1594 		console_lock();
1595 	}
1596 	if (resume) {
1597 		pci_set_power_state(dev->pdev, PCI_D0);
1598 		pci_restore_state(dev->pdev);
1599 		if (pci_enable_device(dev->pdev)) {
1600 			if (fbcon)
1601 				console_unlock();
1602 			return -1;
1603 		}
1604 	}
1605 	/* resume AGP if in use */
1606 	radeon_agp_resume(rdev);
1607 	radeon_resume(rdev);
1608 
1609 	r = radeon_ib_ring_tests(rdev);
1610 	if (r)
1611 		DRM_ERROR("ib ring test failed (%d).\n", r);
1612 
1613 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1614 		/* do dpm late init */
1615 		r = radeon_pm_late_init(rdev);
1616 		if (r) {
1617 			rdev->pm.dpm_enabled = false;
1618 			DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1619 		}
1620 	} else {
1621 		/* resume old pm late */
1622 		radeon_pm_resume(rdev);
1623 	}
1624 
1625 	radeon_restore_bios_scratch_regs(rdev);
1626 
1627 	/* init dig PHYs, disp eng pll */
1628 	if (rdev->is_atom_bios) {
1629 		radeon_atom_encoder_init(rdev);
1630 		radeon_atom_disp_eng_pll_init(rdev);
1631 		/* turn on the BL */
1632 		if (rdev->mode_info.bl_encoder) {
1633 			u8 bl_level = radeon_get_backlight_level(rdev,
1634 								 rdev->mode_info.bl_encoder);
1635 			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1636 						   bl_level);
1637 		}
1638 	}
1639 	/* reset hpd state */
1640 	radeon_hpd_init(rdev);
1641 	/* blat the mode back in */
1642 	if (fbcon) {
1643 		drm_helper_resume_force_mode(dev);
1644 		/* turn on display hw */
1645 		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1646 			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1647 		}
1648 	}
1649 
1650 	drm_kms_helper_poll_enable(dev);
1651 
1652 	/* set the power state here in case we are a PX system or headless */
1653 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1654 		radeon_pm_compute_clocks(rdev);
1655 
1656 	if (fbcon) {
1657 		radeon_fbdev_set_suspend(rdev, 0);
1658 		console_unlock();
1659 	}
1660 
1661 	return 0;
1662 }
1663 
1664 /**
1665  * radeon_gpu_reset - reset the asic
1666  *
1667  * @rdev: radeon device pointer
1668  *
1669  * Attempt the reset the GPU if it has hung (all asics).
1670  * Returns 0 for success or an error on failure.
1671  */
1672 int radeon_gpu_reset(struct radeon_device *rdev)
1673 {
1674 	unsigned ring_sizes[RADEON_NUM_RINGS];
1675 	uint32_t *ring_data[RADEON_NUM_RINGS];
1676 
1677 	bool saved = false;
1678 
1679 	int i, r;
1680 	int resched;
1681 
1682 	down_write(&rdev->exclusive_lock);
1683 
1684 	if (!rdev->needs_reset) {
1685 		up_write(&rdev->exclusive_lock);
1686 		return 0;
1687 	}
1688 
1689 	radeon_save_bios_scratch_regs(rdev);
1690 	/* block TTM */
1691 	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1692 	radeon_suspend(rdev);
1693 	radeon_hpd_fini(rdev);
1694 
1695 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1696 		ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1697 						   &ring_data[i]);
1698 		if (ring_sizes[i]) {
1699 			saved = true;
1700 			dev_info(rdev->dev, "Saved %d dwords of commands "
1701 				 "on ring %d.\n", ring_sizes[i], i);
1702 		}
1703 	}
1704 
1705 	r = radeon_asic_reset(rdev);
1706 	if (!r) {
1707 		dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1708 		radeon_resume(rdev);
1709 	}
1710 
1711 	radeon_restore_bios_scratch_regs(rdev);
1712 
1713 	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1714 		if (!r && ring_data[i]) {
1715 			radeon_ring_restore(rdev, &rdev->ring[i],
1716 					    ring_sizes[i], ring_data[i]);
1717 		} else {
1718 			radeon_fence_driver_force_completion(rdev, i);
1719 			kfree(ring_data[i]);
1720 		}
1721 	}
1722 
1723 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1724 		/* do dpm late init */
1725 		r = radeon_pm_late_init(rdev);
1726 		if (r) {
1727 			rdev->pm.dpm_enabled = false;
1728 			DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1729 		}
1730 	} else {
1731 		/* resume old pm late */
1732 		radeon_pm_resume(rdev);
1733 	}
1734 
1735 	/* init dig PHYs, disp eng pll */
1736 	if (rdev->is_atom_bios) {
1737 		radeon_atom_encoder_init(rdev);
1738 		radeon_atom_disp_eng_pll_init(rdev);
1739 		/* turn on the BL */
1740 		if (rdev->mode_info.bl_encoder) {
1741 			u8 bl_level = radeon_get_backlight_level(rdev,
1742 								 rdev->mode_info.bl_encoder);
1743 			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1744 						   bl_level);
1745 		}
1746 	}
1747 	/* reset hpd state */
1748 	radeon_hpd_init(rdev);
1749 
1750 	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1751 
1752 	rdev->in_reset = true;
1753 	rdev->needs_reset = false;
1754 
1755 	downgrade_write(&rdev->exclusive_lock);
1756 
1757 	drm_helper_resume_force_mode(rdev->ddev);
1758 
1759 	/* set the power state here in case we are a PX system or headless */
1760 	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1761 		radeon_pm_compute_clocks(rdev);
1762 
1763 	if (!r) {
1764 		r = radeon_ib_ring_tests(rdev);
1765 		if (r && saved)
1766 			r = -EAGAIN;
1767 	} else {
1768 		/* bad news, how to tell it to userspace ? */
1769 		dev_info(rdev->dev, "GPU reset failed\n");
1770 	}
1771 
1772 	rdev->needs_reset = r == -EAGAIN;
1773 	rdev->in_reset = false;
1774 
1775 	up_read(&rdev->exclusive_lock);
1776 	return r;
1777 }
1778 
1779 
1780 /*
1781  * Debugfs
1782  */
1783 int radeon_debugfs_add_files(struct radeon_device *rdev,
1784 			     struct drm_info_list *files,
1785 			     unsigned nfiles)
1786 {
1787 	unsigned i;
1788 
1789 	for (i = 0; i < rdev->debugfs_count; i++) {
1790 		if (rdev->debugfs[i].files == files) {
1791 			/* Already registered */
1792 			return 0;
1793 		}
1794 	}
1795 
1796 	i = rdev->debugfs_count + 1;
1797 	if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1798 		DRM_ERROR("Reached maximum number of debugfs components.\n");
1799 		DRM_ERROR("Report so we increase "
1800 		          "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1801 		return -EINVAL;
1802 	}
1803 	rdev->debugfs[rdev->debugfs_count].files = files;
1804 	rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1805 	rdev->debugfs_count = i;
1806 #if defined(CONFIG_DEBUG_FS)
1807 	drm_debugfs_create_files(files, nfiles,
1808 				 rdev->ddev->control->debugfs_root,
1809 				 rdev->ddev->control);
1810 	drm_debugfs_create_files(files, nfiles,
1811 				 rdev->ddev->primary->debugfs_root,
1812 				 rdev->ddev->primary);
1813 #endif
1814 	return 0;
1815 }
1816 
1817 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1818 {
1819 #if defined(CONFIG_DEBUG_FS)
1820 	unsigned i;
1821 
1822 	for (i = 0; i < rdev->debugfs_count; i++) {
1823 		drm_debugfs_remove_files(rdev->debugfs[i].files,
1824 					 rdev->debugfs[i].num_files,
1825 					 rdev->ddev->control);
1826 		drm_debugfs_remove_files(rdev->debugfs[i].files,
1827 					 rdev->debugfs[i].num_files,
1828 					 rdev->ddev->primary);
1829 	}
1830 #endif
1831 }
1832 
1833 #if defined(CONFIG_DEBUG_FS)
1834 int radeon_debugfs_init(struct drm_minor *minor)
1835 {
1836 	return 0;
1837 }
1838 
1839 void radeon_debugfs_cleanup(struct drm_minor *minor)
1840 {
1841 }
1842 #endif
1843